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From: "S, Deepak" <deepak.s@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH 2/5] drm/i915: Read the CCK fuse register from CCK
Date: Tue, 11 Nov 2014 21:09:42 +0530	[thread overview]
Message-ID: <54622DBE.6080304@intel.com> (raw)
In-Reply-To: <20141111152816.GD25711@phenom.ffwll.local>


On 11/11/2014 8:58 PM, Daniel Vetter wrote:
> On Wed, Nov 12, 2014 at 08:40:47AM +0530, Deepak S wrote:
>> On Saturday 08 November 2014 01:03 AM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> When reading a CCK register we should obviously read it from CCK not
>>> Punit. This problem has been present ever since this of code was
>>> introduced in
>>>
>>>   commit 67c3bf6f55a97a0915a0f9ea07278a3073cc9601
>>>   Author: Deepak S <deepak.s@linux.intel.com>
>>>   Date:   Thu Jul 10 13:16:24 2014 +0530
>>>
>>>      drm/i915: populate mem_freq/cz_clock for chv
>>>
>>> The problem was raised during review by Mika [1] but somehow slipped
>>> through the cracks, and the patch got applied with the problem unfixed.
>>>
>>> [1] http://lists.freedesktop.org/archives/intel-gfx/2014-July/048937.html
>>>
>>> Cc: Deepak S <deepak.s@linux.intel.com>
>>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
>>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 9285dee..befad36 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -5253,7 +5253,10 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>>>   	mutex_lock(&dev_priv->rps.hw_lock);
>>> -	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
>>> +	mutex_lock(&dev_priv->dpio_lock);
>>> +	val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
>>> +	mutex_unlock(&dev_priv->dpio_lock);
>>> +
>>>   	switch ((val >> 2) & 0x7) {
>>>   	case 0:
>>>   	case 1:
>>>
>>>
>> Oops i missed the  comment.
>> Reviewed-by: Deepak S <deepak.s@linux.intel.com>
> Queued for -next, thanks for the patch.
>
> Deepak, can you please review the other patches in Ville's series here,
> too?
Sure Daniel. Since CCK was a bug fix reviewed that first.
Other patches Just Started to review. I will send the comments. if any.
> Thanks, Daniel

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  reply	other threads:[~2014-11-11 15:40 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-07 19:33 [PATCH 0/5] drm/i915: Some VLV/CHV rc6/rps fixes/cleanups ville.syrjala
2014-11-07 19:33 ` [PATCH 1/5] drm/i915: Silence valleyview_set_rps() ville.syrjala
2014-11-18  8:26   ` Deepak S
2014-11-07 19:33 ` [PATCH 2/5] drm/i915: Read the CCK fuse register from CCK ville.syrjala
2014-11-12  3:10   ` Deepak S
2014-11-11 15:28     ` Daniel Vetter
2014-11-11 15:39       ` S, Deepak [this message]
2014-11-07 19:33 ` [PATCH 3/5] drm/i915: Add a name for the Punit GPLLENABLE bit ville.syrjala
2014-11-18  9:20   ` Deepak S
2014-11-07 19:33 ` [PATCH 4/5] drm/i915: Warn if GPLL isn't used on vlv/chv ville.syrjala
2014-11-18  9:19   ` Deepak S
2014-11-07 19:33 ` [PATCH 5/5] drm/i915: Improve PCBR debug information ville.syrjala
2014-11-18  9:18   ` Deepak S
2014-11-17 14:31     ` Daniel Vetter

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