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From: Deepak S <deepak.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup
Date: Tue, 18 Nov 2014 14:33:39 +0530	[thread overview]
Message-ID: <546B0B6B.9080404@intel.com> (raw)
In-Reply-To: <1415652915-28271-2-git-send-email-ville.syrjala@linux.intel.com>


On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The divider used in the GPU frequency calculations is compatible between
> vlv and chv. vlv just wants doubled values compared to chv.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 104 ++++++++++++++--------------------------
>   1 file changed, 35 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef8e055..03fbb45 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7283,99 +7283,65 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>   	return 0;
>   }
>   
> -static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +static int vlv_gpu_freq_div(unsigned int czclk_freq)
>   {
> -	int div;
> -
> -	/* 4 x czclk */
> -	switch (dev_priv->mem_freq) {
> -	case 800:
> -		div = 10;
> -		break;
> -	case 1066:
> -		div = 12;
> -		break;
> -	case 1333:
> -		div = 16;
> -		break;
> +	switch (czclk_freq) {
> +	case 200:
> +		return 10;
> +	case 267:
> +		return 12;
> +	case 320:
> +	case 333:
> +	case 400:
> +		return 16;
>   	default:
>   		return -1;
>   	}
> +}
>   
> -	return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
> +static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
> +{
> +	int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
> +
> +	div = vlv_gpu_freq_div(czclk_freq);
> +	if (div < 0)
> +		return div;
> +
> +	return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
>   }
>   
>   static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
>   {
> -	int mul;
> +	int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
>   
> -	/* 4 x czclk */
> -	switch (dev_priv->mem_freq) {
> -	case 800:
> -		mul = 10;
> -		break;
> -	case 1066:
> -		mul = 12;
> -		break;
> -	case 1333:
> -		mul = 16;
> -		break;
> -	default:
> -		return -1;
> -	}
> +	mul = vlv_gpu_freq_div(czclk_freq);
> +	if (mul < 0)
> +		return mul;
>   
> -	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
> +	return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
>   }
>   
>   static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
>   {
> -	int div, freq;
> -
> -	switch (dev_priv->rps.cz_freq) {
> -	case 200:
> -		div = 5;
> -		break;
> -	case 267:
> -		div = 6;
> -		break;
> -	case 320:
> -	case 333:
> -	case 400:
> -		div = 8;
> -		break;
> -	default:
> -		return -1;
> -	}
> +	int div, czclk_freq = dev_priv->rps.cz_freq;
>   
> -	freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
> +	div = vlv_gpu_freq_div(czclk_freq) / 2;
> +	if (div < 0)
> +		return div;
>   
> -	return freq;
> +	return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
>   }
>   
>   static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>   {
> -	int mul, opcode;
> +	int mul, czclk_freq = dev_priv->rps.cz_freq;
>   
> -	switch (dev_priv->rps.cz_freq) {
> -	case 200:
> -		mul = 5;
> -		break;
> -	case 267:
> -		mul = 6;
> -		break;
> -	case 320:
> -	case 333:
> -	case 400:
> -		mul = 8;
> -		break;
> -	default:
> -		return -1;
> -	}
> +	mul = vlv_gpu_freq_div(czclk_freq) / 2;
> +	if (mul < 0)
> +		return mul;
>   
>   	/* CHV needs even values */
> -	opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
> -
> -	return opcode;
> +	return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
>   }
>   
>   int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)

Nice Looks fine.
Reviewed-by: Deepak S <deepak.s@linux.intel.com>

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  reply	other threads:[~2014-11-17  9:06 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala
2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala
2014-11-18  9:03   ` Deepak S [this message]
2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala
2014-11-18  9:08   ` Deepak S
2014-11-17 11:35     ` Ville Syrjälä
2014-11-18 12:29       ` Deepak S
2014-11-17 12:41         ` Ville Syrjälä
2014-11-18 14:33           ` Deepak S
2014-11-17 15:39             ` Ville Syrjälä
2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala
2014-11-18  9:09   ` Deepak S
2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala
2014-11-11 18:09   ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq shuang.he
2014-11-18  9:14   ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S
2014-11-17 14:35     ` Daniel Vetter

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