* [PATCH 0/4] drm/i915: Additional CHV RPS fixes
@ 2014-11-10 20:55 ville.syrjala
2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: ville.syrjala @ 2014-11-10 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: "Deepak S", deepak.s
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I was staring at the GPU frquencies my BSW reports and they didn't seem
to match the docs exactly, so I set out to fix a few things. Now things
should match what the docs. No idea if the docs are correct anymore
though, but at least the date on the spreadsheet I used was fairly recent.
And I ended up doing a bit of refactoring on the way, so the LOC went
down a bit, which is always nice :)
Ville Syrjälä (4):
drm/i915: Refactor vlv/chv GPU frequency divider setup
drm/i915: Fix chv GPU freq<->opcode conversions
drm/i915: Add missing newline to 'DDR speed' debug messages
drm/i915: Change CHV SKU400 GPU freq divider to 10
drivers/gpu/drm/i915/intel_pm.c | 109 ++++++++++++++--------------------------
1 file changed, 38 insertions(+), 71 deletions(-)
--
2.0.4
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup 2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala @ 2014-11-10 20:55 ` ville.syrjala 2014-11-18 9:03 ` Deepak S 2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala ` (2 subsequent siblings) 3 siblings, 1 reply; 16+ messages in thread From: ville.syrjala @ 2014-11-10 20:55 UTC (permalink / raw) To: intel-gfx; +Cc: "Deepak S", deepak.s From: Ville Syrjälä <ville.syrjala@linux.intel.com> The divider used in the GPU frequency calculations is compatible between vlv and chv. vlv just wants doubled values compared to chv. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 104 ++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ef8e055..03fbb45 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7283,99 +7283,65 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) return 0; } -static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) +static int vlv_gpu_freq_div(unsigned int czclk_freq) { - int div; - - /* 4 x czclk */ - switch (dev_priv->mem_freq) { - case 800: - div = 10; - break; - case 1066: - div = 12; - break; - case 1333: - div = 16; - break; + switch (czclk_freq) { + case 200: + return 10; + case 267: + return 12; + case 320: + case 333: + case 400: + return 16; default: return -1; } +} - return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); +static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) +{ + int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); + + div = vlv_gpu_freq_div(czclk_freq); + if (div < 0) + return div; + + return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); } static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) { - int mul; + int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); - /* 4 x czclk */ - switch (dev_priv->mem_freq) { - case 800: - mul = 10; - break; - case 1066: - mul = 12; - break; - case 1333: - mul = 16; - break; - default: - return -1; - } + mul = vlv_gpu_freq_div(czclk_freq); + if (mul < 0) + return mul; - return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; + return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; } static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) { - int div, freq; - - switch (dev_priv->rps.cz_freq) { - case 200: - div = 5; - break; - case 267: - div = 6; - break; - case 320: - case 333: - case 400: - div = 8; - break; - default: - return -1; - } + int div, czclk_freq = dev_priv->rps.cz_freq; - freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); + div = vlv_gpu_freq_div(czclk_freq) / 2; + if (div < 0) + return div; - return freq; + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; } static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) { - int mul, opcode; + int mul, czclk_freq = dev_priv->rps.cz_freq; - switch (dev_priv->rps.cz_freq) { - case 200: - mul = 5; - break; - case 267: - mul = 6; - break; - case 320: - case 333: - case 400: - mul = 8; - break; - default: - return -1; - } + mul = vlv_gpu_freq_div(czclk_freq) / 2; + if (mul < 0) + return mul; /* CHV needs even values */ - opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); - - return opcode; + return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; } int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) -- 2.0.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup 2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala @ 2014-11-18 9:03 ` Deepak S 0 siblings, 0 replies; 16+ messages in thread From: Deepak S @ 2014-11-18 9:03 UTC (permalink / raw) To: intel-gfx On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The divider used in the GPU frequency calculations is compatible between > vlv and chv. vlv just wants doubled values compared to chv. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 104 ++++++++++++++-------------------------- > 1 file changed, 35 insertions(+), 69 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ef8e055..03fbb45 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7283,99 +7283,65 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > return 0; > } > > -static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) > +static int vlv_gpu_freq_div(unsigned int czclk_freq) > { > - int div; > - > - /* 4 x czclk */ > - switch (dev_priv->mem_freq) { > - case 800: > - div = 10; > - break; > - case 1066: > - div = 12; > - break; > - case 1333: > - div = 16; > - break; > + switch (czclk_freq) { > + case 200: > + return 10; > + case 267: > + return 12; > + case 320: > + case 333: > + case 400: > + return 16; > default: > return -1; > } > +} > > - return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); > +static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) > +{ > + int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); > + > + div = vlv_gpu_freq_div(czclk_freq); > + if (div < 0) > + return div; > + > + return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); > } > > static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) > { > - int mul; > + int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); > > - /* 4 x czclk */ > - switch (dev_priv->mem_freq) { > - case 800: > - mul = 10; > - break; > - case 1066: > - mul = 12; > - break; > - case 1333: > - mul = 16; > - break; > - default: > - return -1; > - } > + mul = vlv_gpu_freq_div(czclk_freq); > + if (mul < 0) > + return mul; > > - return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; > + return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; > } > > static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) > { > - int div, freq; > - > - switch (dev_priv->rps.cz_freq) { > - case 200: > - div = 5; > - break; > - case 267: > - div = 6; > - break; > - case 320: > - case 333: > - case 400: > - div = 8; > - break; > - default: > - return -1; > - } > + int div, czclk_freq = dev_priv->rps.cz_freq; > > - freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); > + div = vlv_gpu_freq_div(czclk_freq) / 2; > + if (div < 0) > + return div; > > - return freq; > + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; > } > > static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > { > - int mul, opcode; > + int mul, czclk_freq = dev_priv->rps.cz_freq; > > - switch (dev_priv->rps.cz_freq) { > - case 200: > - mul = 5; > - break; > - case 267: > - mul = 6; > - break; > - case 320: > - case 333: > - case 400: > - mul = 8; > - break; > - default: > - return -1; > - } > + mul = vlv_gpu_freq_div(czclk_freq) / 2; > + if (mul < 0) > + return mul; > > /* CHV needs even values */ > - opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); > - > - return opcode; > + return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; > } > > int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) Nice Looks fine. Reviewed-by: Deepak S <deepak.s@linux.intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala 2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala @ 2014-11-10 20:55 ` ville.syrjala 2014-11-18 9:08 ` Deepak S 2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala 2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala 3 siblings, 1 reply; 16+ messages in thread From: ville.syrjala @ 2014-11-10 20:55 UTC (permalink / raw) To: intel-gfx; +Cc: "Deepak S", deepak.s From: Ville Syrjälä <ville.syrjala@linux.intel.com> Currently we miscalculate the GPU frequency on chv. This causes us to report the GPU frequency as half of what it really is. Drop the extra factor of 2 from the calculations to get the correct answer. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 03fbb45..74e4293 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) if (div < 0) return div; - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); } static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) return mul; /* CHV needs even values */ - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; } int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) -- 2.0.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala @ 2014-11-18 9:08 ` Deepak S 2014-11-17 11:35 ` Ville Syrjälä 0 siblings, 1 reply; 16+ messages in thread From: Deepak S @ 2014-11-18 9:08 UTC (permalink / raw) To: intel-gfx On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Currently we miscalculate the GPU frequency on chv. This causes us to > report the GPU frequency as half of what it really is. Drop the extra > factor of 2 from the calculations to get the correct answer. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 03fbb45..74e4293 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) > if (div < 0) > return div; > > - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; > + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? > } > > static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > return mul; > > /* CHV needs even values */ > - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; > + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; > } > > int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-18 9:08 ` Deepak S @ 2014-11-17 11:35 ` Ville Syrjälä 2014-11-18 12:29 ` Deepak S 0 siblings, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2014-11-17 11:35 UTC (permalink / raw) To: Deepak S; +Cc: intel-gfx On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote: > > On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Currently we miscalculate the GPU frequency on chv. This causes us to > > report the GPU frequency as half of what it really is. Drop the extra > > factor of 2 from the calculations to get the correct answer. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 03fbb45..74e4293 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) > > if (div < 0) > > return div; > > > > - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; > > + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); > > I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? Hmm. Once again the docs are extremely unclear. Dropping the 2x factor gives me the same numbers that the tables in the docs have. But then the spreadsheet calls it a "2x clock" in some places, which does suggest it might get further divided down by 2. Oh, now I did find a somewhat clear note in the clock HAS: "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC, which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock." So based on that the original code does make more sense. > > > } > > > > static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > > @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > > return mul; > > > > /* CHV needs even values */ > > - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; > > + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; > > } > > > > int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-17 11:35 ` Ville Syrjälä @ 2014-11-18 12:29 ` Deepak S 2014-11-17 12:41 ` Ville Syrjälä 0 siblings, 1 reply; 16+ messages in thread From: Deepak S @ 2014-11-18 12:29 UTC (permalink / raw) To: intel-gfx On Monday 17 November 2014 05:05 PM, Ville Syrjälä wrote: > On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote: >> On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >>> >>> Currently we miscalculate the GPU frequency on chv. This causes us to >>> report the GPU frequency as half of what it really is. Drop the extra >>> factor of 2 from the calculations to get the correct answer. >>> >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>> --- >>> drivers/gpu/drm/i915/intel_pm.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >>> index 03fbb45..74e4293 100644 >>> --- a/drivers/gpu/drm/i915/intel_pm.c >>> +++ b/drivers/gpu/drm/i915/intel_pm.c >>> @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) >>> if (div < 0) >>> return div; >>> >>> - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; >>> + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); >> I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? > Hmm. Once again the docs are extremely unclear. Dropping the 2x factor > gives me the same numbers that the tables in the docs have. But then > the spreadsheet calls it a "2x clock" in some places, which does suggest > it might get further divided down by 2. > > Oh, now I did find a somewhat clear note in the clock HAS: > "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC, > which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock." > > So based on that the original code does make more sense. > Do we need to mention in comment about 2 * GFX clock? >>> } >>> >>> static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) >>> @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) >>> return mul; >>> >>> /* CHV needs even values */ >>> - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; >>> + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; >>> } >>> >>> int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-18 12:29 ` Deepak S @ 2014-11-17 12:41 ` Ville Syrjälä 2014-11-18 14:33 ` Deepak S 0 siblings, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2014-11-17 12:41 UTC (permalink / raw) To: Deepak S; +Cc: intel-gfx On Tue, Nov 18, 2014 at 05:59:07PM +0530, Deepak S wrote: > > On Monday 17 November 2014 05:05 PM, Ville Syrjälä wrote: > > On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote: > >> On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >>> > >>> Currently we miscalculate the GPU frequency on chv. This causes us to > >>> report the GPU frequency as half of what it really is. Drop the extra > >>> factor of 2 from the calculations to get the correct answer. > >>> > >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >>> --- > >>> drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > >>> 1 file changed, 2 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >>> index 03fbb45..74e4293 100644 > >>> --- a/drivers/gpu/drm/i915/intel_pm.c > >>> +++ b/drivers/gpu/drm/i915/intel_pm.c > >>> @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) > >>> if (div < 0) > >>> return div; > >>> > >>> - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; > >>> + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); > >> I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? > > Hmm. Once again the docs are extremely unclear. Dropping the 2x factor > > gives me the same numbers that the tables in the docs have. But then > > the spreadsheet calls it a "2x clock" in some places, which does suggest > > it might get further divided down by 2. > > > > Oh, now I did find a somewhat clear note in the clock HAS: > > "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC, > > which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock." > > > > So based on that the original code does make more sense. > > > Do we need to mention in comment about 2 * GFX clock? Yeah, a comment would probably be a good idea. Could avoid some confusion in the future if someone else looks at this code. > > > >>> } > >>> > >>> static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > >>> @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > >>> return mul; > >>> > >>> /* CHV needs even values */ > >>> - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; > >>> + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; > >>> } > >>> > >>> int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-17 12:41 ` Ville Syrjälä @ 2014-11-18 14:33 ` Deepak S 2014-11-17 15:39 ` Ville Syrjälä 0 siblings, 1 reply; 16+ messages in thread From: Deepak S @ 2014-11-18 14:33 UTC (permalink / raw) To: intel-gfx On Monday 17 November 2014 06:11 PM, Ville Syrjälä wrote: > On Tue, Nov 18, 2014 at 05:59:07PM +0530, Deepak S wrote: >> On Monday 17 November 2014 05:05 PM, Ville Syrjälä wrote: >>> On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote: >>>> On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: >>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >>>>> >>>>> Currently we miscalculate the GPU frequency on chv. This causes us to >>>>> report the GPU frequency as half of what it really is. Drop the extra >>>>> factor of 2 from the calculations to get the correct answer. >>>>> >>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>>>> --- >>>>> drivers/gpu/drm/i915/intel_pm.c | 4 ++-- >>>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >>>>> index 03fbb45..74e4293 100644 >>>>> --- a/drivers/gpu/drm/i915/intel_pm.c >>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c >>>>> @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) >>>>> if (div < 0) >>>>> return div; >>>>> >>>>> - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; >>>>> + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); >>>> I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? >>> Hmm. Once again the docs are extremely unclear. Dropping the 2x factor >>> gives me the same numbers that the tables in the docs have. But then >>> the spreadsheet calls it a "2x clock" in some places, which does suggest >>> it might get further divided down by 2. >>> >>> Oh, now I did find a somewhat clear note in the clock HAS: >>> "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC, >>> which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock." >>> >>> So based on that the original code does make more sense. >>> >> Do we need to mention in comment about 2 * GFX clock? > Yeah, a comment would probably be a good idea. Could avoid some confusion > in the future if someone else looks at this code. Will you add the comment and submit a patch? >> >>>>> } >>>>> >>>>> static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) >>>>> @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) >>>>> return mul; >>>>> >>>>> /* CHV needs even values */ >>>>> - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; >>>>> + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; >>>>> } >>>>> >>>>> int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) >>>> _______________________________________________ >>>> Intel-gfx mailing list >>>> Intel-gfx@lists.freedesktop.org >>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions 2014-11-18 14:33 ` Deepak S @ 2014-11-17 15:39 ` Ville Syrjälä 0 siblings, 0 replies; 16+ messages in thread From: Ville Syrjälä @ 2014-11-17 15:39 UTC (permalink / raw) To: Deepak S; +Cc: intel-gfx On Tue, Nov 18, 2014 at 08:03:15PM +0530, Deepak S wrote: > > On Monday 17 November 2014 06:11 PM, Ville Syrjälä wrote: > > On Tue, Nov 18, 2014 at 05:59:07PM +0530, Deepak S wrote: > >> On Monday 17 November 2014 05:05 PM, Ville Syrjälä wrote: > >>> On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote: > >>>> On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > >>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >>>>> > >>>>> Currently we miscalculate the GPU frequency on chv. This causes us to > >>>>> report the GPU frequency as half of what it really is. Drop the extra > >>>>> factor of 2 from the calculations to get the correct answer. > >>>>> > >>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >>>>> --- > >>>>> drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > >>>>> 1 file changed, 2 insertions(+), 2 deletions(-) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >>>>> index 03fbb45..74e4293 100644 > >>>>> --- a/drivers/gpu/drm/i915/intel_pm.c > >>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c > >>>>> @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) > >>>>> if (div < 0) > >>>>> return div; > >>>>> > >>>>> - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; > >>>>> + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div); > >>>> I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck? > >>> Hmm. Once again the docs are extremely unclear. Dropping the 2x factor > >>> gives me the same numbers that the tables in the docs have. But then > >>> the spreadsheet calls it a "2x clock" in some places, which does suggest > >>> it might get further divided down by 2. > >>> > >>> Oh, now I did find a somewhat clear note in the clock HAS: > >>> "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC, > >>> which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock." > >>> > >>> So based on that the original code does make more sense. > >>> > >> Do we need to mention in comment about 2 * GFX clock? > > Yeah, a comment would probably be a good idea. Could avoid some confusion > > in the future if someone else looks at this code. > > Will you add the comment and submit a patch? Actually I'm no longer sure about the 2x :( I also see the following note in the clock HAS: GT_GFCLK: This is the full rate clock, its max freq is 2000MHz. Which is sort of telling me that there's no /2 for gfclk. I guess it doesn't really matter what we report as long as we consistently do the conversion the the same way both ways. But it would be nice if we would end up reporting the frequency of the same clock that BDW reports. Unfortunately the BDW docs I have are even more useless in this regard. > > >> > >>>>> } > >>>>> > >>>>> static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > >>>>> @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) > >>>>> return mul; > >>>>> > >>>>> /* CHV needs even values */ > >>>>> - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; > >>>>> + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2; > >>>>> } > >>>>> > >>>>> int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) > >>>> _______________________________________________ > >>>> Intel-gfx mailing list > >>>> Intel-gfx@lists.freedesktop.org > >>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages 2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala 2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala 2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala @ 2014-11-10 20:55 ` ville.syrjala 2014-11-18 9:09 ` Deepak S 2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala 3 siblings, 1 reply; 16+ messages in thread From: ville.syrjala @ 2014-11-10 20:55 UTC (permalink / raw) To: intel-gfx; +Cc: "Deepak S", deepak.s From: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 74e4293..0f5c391 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5217,7 +5217,7 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) dev_priv->mem_freq = 1333; break; } - DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); + DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; @@ -5286,7 +5286,7 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) dev_priv->mem_freq = 1600; break; } - DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); + DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; -- 2.0.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages 2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala @ 2014-11-18 9:09 ` Deepak S 0 siblings, 0 replies; 16+ messages in thread From: Deepak S @ 2014-11-18 9:09 UTC (permalink / raw) To: intel-gfx On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 74e4293..0f5c391 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5217,7 +5217,7 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) > dev_priv->mem_freq = 1333; > break; > } > - DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > + DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); > > dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); > dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; > @@ -5286,7 +5286,7 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) > dev_priv->mem_freq = 1600; > break; > } > - DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > + DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); > > dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); > dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; :) Reviewed-by: Deepak S <deepak.s@linux.intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala ` (2 preceding siblings ...) 2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala @ 2014-11-10 20:55 ` ville.syrjala 2014-11-11 18:09 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq shuang.he 2014-11-18 9:14 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S 3 siblings, 2 replies; 16+ messages in thread From: ville.syrjala @ 2014-11-10 20:55 UTC (permalink / raw) To: intel-gfx; +Cc: "Deepak S", deepak.s From: Ville Syrjälä <ville.syrjala@linux.intel.com> According to "Cherryview_GFXclocks_y14w36d1.xlsx" the GPU frequency divider should be 10 in when the CZ clock is 400 MHz. Change the code to agree so that we report the correct frequencies. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0f5c391..b73506f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7292,8 +7292,9 @@ static int vlv_gpu_freq_div(unsigned int czclk_freq) return 12; case 320: case 333: - case 400: return 16; + case 400: + return 20; default: return -1; } -- 2.0.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq 2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala @ 2014-11-11 18:09 ` shuang.he 2014-11-18 9:14 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S 1 sibling, 0 replies; 16+ messages in thread From: shuang.he @ 2014-11-11 18:09 UTC (permalink / raw) To: shuang.he, intel-gfx, ville.syrjala Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=247/348->277/348 PNV: pass/total=326/328->325/328 ILK: pass/total=329/330->330/330 IVB: pass/total=544/546->544/546 SNB: pass/total=558/563->558/563 HSW: pass/total=573/578->573/578 BDW: pass/total=435/435->434/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(5, M31M36M38) -> DMESG_WARN(1, M31)PASS(3, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(5, M36M29)PASS(7, M31M29M38) -> DMESG_WARN(3, M31)PASS(1, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(5, M31M36M29)PASS(7, M31M36M29M38) -> DMESG_WARN(2, M31)PASS(2, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(5, M31M36M29)PASS(7, M31M36M29M38) -> DMESG_WARN(2, M31)PASS(2, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(8, M31M36M29)PASS(4, M29M38) -> DMESG_WARN(2, M31)PASS(2, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(7, M31M36M29)PASS(5, M36M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(3, M36M29)PASS(9, M31M36M29M38) -> DMESG_WARN(1, M31)PASS(3, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(4, M36M29)PASS(8, M31M36M29M38) -> DMESG_WARN(2, M31)PASS(2, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(12, M31M36M29M38) -> PASS(4, M31) PNV: Intel_gpu_tools, igt_gem_linear_blits_normal, NSPT(9, M23M7)PASS(1, M25) -> NSPT(4, M7) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(1, M26)PASS(9, M37) -> PASS(4, M37) IVB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(4, M34M21) -> DMESG_WARN(1, M21)PASS(3, M21) IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(6, M21) -> PASS(4, M21) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-random, PASS(4, M35M22) -> DMESG_WARN(1, M22)PASS(3, M22) SNB: Intel_gpu_tools, igt_kms_cursor_crc_cursor-256x256-sliding, DMESG_WARN(1, M35)PASS(6, M35M22) -> PASS(4, M22) BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(13, M42M30M28) -> DMESG_WARN(1, M42)PASS(3, M42) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala 2014-11-11 18:09 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq shuang.he @ 2014-11-18 9:14 ` Deepak S 2014-11-17 14:35 ` Daniel Vetter 1 sibling, 1 reply; 16+ messages in thread From: Deepak S @ 2014-11-18 9:14 UTC (permalink / raw) To: intel-gfx On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > According to "Cherryview_GFXclocks_y14w36d1.xlsx" the GPU frequency > divider should be 10 in when the CZ clock is 400 MHz. Change the code > to agree so that we report the correct frequencies. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 0f5c391..b73506f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7292,8 +7292,9 @@ static int vlv_gpu_freq_div(unsigned int czclk_freq) > return 12; > case 320: > case 333: > - case 400: > return 16; > + case 400: > + return 20; > default: > return -1; > } right latest spec as div is 20 Reviewed-by: Deepak S <deepak.s@linux.intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 2014-11-18 9:14 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S @ 2014-11-17 14:35 ` Daniel Vetter 0 siblings, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2014-11-17 14:35 UTC (permalink / raw) To: Deepak S; +Cc: intel-gfx On Tue, Nov 18, 2014 at 02:44:57PM +0530, Deepak S wrote: > > On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote: > >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > >According to "Cherryview_GFXclocks_y14w36d1.xlsx" the GPU frequency > >divider should be 10 in when the CZ clock is 400 MHz. Change the code > >to agree so that we report the correct frequencies. > > > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >--- > > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >index 0f5c391..b73506f 100644 > >--- a/drivers/gpu/drm/i915/intel_pm.c > >+++ b/drivers/gpu/drm/i915/intel_pm.c > >@@ -7292,8 +7292,9 @@ static int vlv_gpu_freq_div(unsigned int czclk_freq) > > return 12; > > case 320: > > case 333: > >- case 400: > > return 16; > >+ case 400: > >+ return 20; > > default: > > return -1; > > } > > right latest spec as div is 20 > > Reviewed-by: Deepak S <deepak.s@linux.intel.com> Merged all from this series except patch 2 about the 2*clock confusion. Thanks for patches&review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-11-17 15:39 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala 2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala 2014-11-18 9:03 ` Deepak S 2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala 2014-11-18 9:08 ` Deepak S 2014-11-17 11:35 ` Ville Syrjälä 2014-11-18 12:29 ` Deepak S 2014-11-17 12:41 ` Ville Syrjälä 2014-11-18 14:33 ` Deepak S 2014-11-17 15:39 ` Ville Syrjälä 2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala 2014-11-18 9:09 ` Deepak S 2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala 2014-11-11 18:09 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq shuang.he 2014-11-18 9:14 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S 2014-11-17 14:35 ` Daniel Vetter
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