From: Deepak S <deepak.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/i915: Improve PCBR debug information
Date: Tue, 18 Nov 2014 14:48:27 +0530 [thread overview]
Message-ID: <546B0EE3.8040005@intel.com> (raw)
In-Reply-To: <1415388826-10842-6-git-send-email-ville.syrjala@linux.intel.com>
On Saturday 08 November 2014 01:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Always print the final PCBR register value on both vlv and chv, and
> also tell us whether the BIOS was a good citizen or not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e8a6f92..ef8e055 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5126,12 +5126,15 @@ static void cherryview_setup_pctx(struct drm_device *dev)
>
> pcbr = I915_READ(VLV_PCBR);
> if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
> + DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
> paddr = (dev_priv->mm.stolen_base +
> (gtt->stolen_size - pctx_size));
>
> pctx_paddr = (paddr & (~4095));
> I915_WRITE(VLV_PCBR, pctx_paddr);
> }
> +
> + DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
> }
>
> static void valleyview_setup_pctx(struct drm_device *dev)
> @@ -5157,6 +5160,8 @@ static void valleyview_setup_pctx(struct drm_device *dev)
> goto out;
> }
>
> + DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
> +
> /*
> * From the Gunit register HAS:
> * The Gfx driver is expected to program this register and ensure
> @@ -5175,6 +5180,7 @@ static void valleyview_setup_pctx(struct drm_device *dev)
> I915_WRITE(VLV_PCBR, pctx_paddr);
>
> out:
> + DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
> dev_priv->vlv_pctx = pctx;
> }
>
> @@ -5366,8 +5372,6 @@ static void cherryview_enable_rps(struct drm_device *dev)
> /* For now we assume BIOS is allocating and populating the PCBR */
> pcbr = I915_READ(VLV_PCBR);
>
> - DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
> -
> /* 3: Enable RC6 */
> if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
> (pcbr >> VLV_PCBR_ADDR_SHIFT))
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
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next prev parent reply other threads:[~2014-11-17 9:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-07 19:33 [PATCH 0/5] drm/i915: Some VLV/CHV rc6/rps fixes/cleanups ville.syrjala
2014-11-07 19:33 ` [PATCH 1/5] drm/i915: Silence valleyview_set_rps() ville.syrjala
2014-11-18 8:26 ` Deepak S
2014-11-07 19:33 ` [PATCH 2/5] drm/i915: Read the CCK fuse register from CCK ville.syrjala
2014-11-12 3:10 ` Deepak S
2014-11-11 15:28 ` Daniel Vetter
2014-11-11 15:39 ` S, Deepak
2014-11-07 19:33 ` [PATCH 3/5] drm/i915: Add a name for the Punit GPLLENABLE bit ville.syrjala
2014-11-18 9:20 ` Deepak S
2014-11-07 19:33 ` [PATCH 4/5] drm/i915: Warn if GPLL isn't used on vlv/chv ville.syrjala
2014-11-18 9:19 ` Deepak S
2014-11-07 19:33 ` [PATCH 5/5] drm/i915: Improve PCBR debug information ville.syrjala
2014-11-18 9:18 ` Deepak S [this message]
2014-11-17 14:31 ` Daniel Vetter
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