From: Deepak S <deepak.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: Warn if GPLL isn't used on vlv/chv
Date: Tue, 18 Nov 2014 14:49:58 +0530 [thread overview]
Message-ID: <546B0F3E.3050401@intel.com> (raw)
In-Reply-To: <1415388826-10842-5-git-send-email-ville.syrjala@linux.intel.com>
On Saturday 08 November 2014 01:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our freq<->opcode conversions assume that GPLL is always used.
> Apparently that should be the case always, but let's scream if we
> ever encounter something different.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 71eb377..e8a6f92 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5397,6 +5397,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> + /* RPS code assumes GPLL is used */
> + WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
> +
> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
> @@ -5477,6 +5480,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> + /* RPS code assumes GPLL is used */
> + WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
> +
> DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
Yup better to give warning if our assumption is wrong:)
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
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next prev parent reply other threads:[~2014-11-17 9:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-07 19:33 [PATCH 0/5] drm/i915: Some VLV/CHV rc6/rps fixes/cleanups ville.syrjala
2014-11-07 19:33 ` [PATCH 1/5] drm/i915: Silence valleyview_set_rps() ville.syrjala
2014-11-18 8:26 ` Deepak S
2014-11-07 19:33 ` [PATCH 2/5] drm/i915: Read the CCK fuse register from CCK ville.syrjala
2014-11-12 3:10 ` Deepak S
2014-11-11 15:28 ` Daniel Vetter
2014-11-11 15:39 ` S, Deepak
2014-11-07 19:33 ` [PATCH 3/5] drm/i915: Add a name for the Punit GPLLENABLE bit ville.syrjala
2014-11-18 9:20 ` Deepak S
2014-11-07 19:33 ` [PATCH 4/5] drm/i915: Warn if GPLL isn't used on vlv/chv ville.syrjala
2014-11-18 9:19 ` Deepak S [this message]
2014-11-07 19:33 ` [PATCH 5/5] drm/i915: Improve PCBR debug information ville.syrjala
2014-11-18 9:18 ` Deepak S
2014-11-17 14:31 ` Daniel Vetter
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