From: Deepak S <deepak.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/i915: Add a name for the Punit GPLLENABLE bit
Date: Tue, 18 Nov 2014 14:50:42 +0530 [thread overview]
Message-ID: <546B0F6A.9020307@intel.com> (raw)
In-Reply-To: <1415388826-10842-4-git-send-email-ville.syrjala@linux.intel.com>
On Saturday 08 November 2014 01:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Remove the magic number for the GPLLENABLE bit by adding a name for it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d43fa0e..ec4dc00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -564,6 +564,7 @@ enum punit_power_well {
> #define PUNIT_REG_GPU_LFM 0xd3
> #define PUNIT_REG_GPU_FREQ_REQ 0xd4
> #define PUNIT_REG_GPU_FREQ_STS 0xd8
> +#define GPLLENABLE (1<<4)
> #define GENFREQSTATUS (1<<0)
> #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
> #define PUNIT_REG_CZ_TIMESTAMP 0xce
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index befad36..71eb377 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5397,7 +5397,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
> dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> @@ -5477,7 +5477,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
:)
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
> dev_priv->rps.cur_freq = (val >> 8) & 0xff;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-11-17 9:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-07 19:33 [PATCH 0/5] drm/i915: Some VLV/CHV rc6/rps fixes/cleanups ville.syrjala
2014-11-07 19:33 ` [PATCH 1/5] drm/i915: Silence valleyview_set_rps() ville.syrjala
2014-11-18 8:26 ` Deepak S
2014-11-07 19:33 ` [PATCH 2/5] drm/i915: Read the CCK fuse register from CCK ville.syrjala
2014-11-12 3:10 ` Deepak S
2014-11-11 15:28 ` Daniel Vetter
2014-11-11 15:39 ` S, Deepak
2014-11-07 19:33 ` [PATCH 3/5] drm/i915: Add a name for the Punit GPLLENABLE bit ville.syrjala
2014-11-18 9:20 ` Deepak S [this message]
2014-11-07 19:33 ` [PATCH 4/5] drm/i915: Warn if GPLL isn't used on vlv/chv ville.syrjala
2014-11-18 9:19 ` Deepak S
2014-11-07 19:33 ` [PATCH 5/5] drm/i915: Improve PCBR debug information ville.syrjala
2014-11-18 9:18 ` Deepak S
2014-11-17 14:31 ` Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=546B0F6A.9020307@intel.com \
--to=deepak.s@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox