From: Deepak S <deepak.s@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions
Date: Tue, 18 Nov 2014 17:59:07 +0530 [thread overview]
Message-ID: <546B3B93.9050207@intel.com> (raw)
In-Reply-To: <20141117113552.GG10649@intel.com>
On Monday 17 November 2014 05:05 PM, Ville Syrjälä wrote:
> On Tue, Nov 18, 2014 at 02:38:25PM +0530, Deepak S wrote:
>> On Tuesday 11 November 2014 02:25 AM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Currently we miscalculate the GPU frequency on chv. This causes us to
>>> report the GPU frequency as half of what it really is. Drop the extra
>>> factor of 2 from the calculations to get the correct answer.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 03fbb45..74e4293 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -7329,7 +7329,7 @@ static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
>>> if (div < 0)
>>> return div;
>>>
>>> - return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
>>> + return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div);
>> I think CHV is 2 X cck, shouldn't we report the cck freq and not 2 *cck?
> Hmm. Once again the docs are extremely unclear. Dropping the 2x factor
> gives me the same numbers that the tables in the docs have. But then
> the spreadsheet calls it a "2x clock" in some places, which does suggest
> it might get further divided down by 2.
>
> Oh, now I did find a somewhat clear note in the clock HAS:
> "The dedicated GPLL (Graphics PLL) sends a 2GHz gfx clock to GenLC,
> which gets divided inside the GenLC block to derive a 1GHz Gfx fast clock."
>
> So based on that the original code does make more sense.
>
Do we need to mention in comment about 2 * GFX clock?
>>> }
>>>
>>> static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>>> @@ -7341,7 +7341,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>>> return mul;
>>>
>>> /* CHV needs even values */
>>> - return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
>>> + return DIV_ROUND_CLOSEST(val * mul, czclk_freq) * 2;
>>> }
>>>
>>> int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2014-11-17 12:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-10 20:55 [PATCH 0/4] drm/i915: Additional CHV RPS fixes ville.syrjala
2014-11-10 20:55 ` [PATCH 1/4] drm/i915: Refactor vlv/chv GPU frequency divider setup ville.syrjala
2014-11-18 9:03 ` Deepak S
2014-11-10 20:55 ` [PATCH 2/4] drm/i915: Fix chv GPU freq<->opcode conversions ville.syrjala
2014-11-18 9:08 ` Deepak S
2014-11-17 11:35 ` Ville Syrjälä
2014-11-18 12:29 ` Deepak S [this message]
2014-11-17 12:41 ` Ville Syrjälä
2014-11-18 14:33 ` Deepak S
2014-11-17 15:39 ` Ville Syrjälä
2014-11-10 20:55 ` [PATCH 3/4] drm/i915: Add missing newline to 'DDR speed' debug messages ville.syrjala
2014-11-18 9:09 ` Deepak S
2014-11-10 20:55 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 ville.syrjala
2014-11-11 18:09 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq shuang.he
2014-11-18 9:14 ` [PATCH 4/4] drm/i915: Change CHV SKU400 GPU freq divider to 10 Deepak S
2014-11-17 14:35 ` Daniel Vetter
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