* [PATCH 00/11] BYT DSI Dual Link Support
@ 2014-10-29 8:42 Gaurav K Singh
2014-10-29 8:42 ` [PATCH 01/11] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
` (11 more replies)
0 siblings, 12 replies; 28+ messages in thread
From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Shobhit Kumar
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
v2: Commit message added to all patches. All review comments of Jani, Nikula
have been addressed in the second version of patches.
Regards
Gaurav
Gaurav K Singh (11):
drm/i915: New functions added for enabling & disabling MIPI Port Ctrl
reg
drm/i915: MIPI Sequence to be sent to the DSI Controller based on the
port no from VBT
drm/i915: Cleanup in i915_reg.h for all MIPI regs.
drm/i915: Cleanup patch for MIPI regs
drm/i915: Add support for port enable/disable for dual link
configuration
drm/i915: Pixel Clock changes for DSI dual link
drm/i915: Dual link needs Shutdown and Turn on packet for both ports
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
drm/i915: MIPI Timings related changes for dual link
drm/i915: Update the DSI disable path to support dual link panel
disabling
drm/i915: Update the DSI enable path to support dual link panel
enabling
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 103 +++---
drivers/gpu/drm/i915/intel_bios.h | 3 +-
drivers/gpu/drm/i915/intel_dsi.c | 472 ++++++++++++++++++----------
drivers/gpu/drm/i915/intel_dsi.h | 8 +
drivers/gpu/drm/i915/intel_dsi_cmd.c | 49 +--
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 25 ++
drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +-
8 files changed, 429 insertions(+), 244 deletions(-)
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH 01/11] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 02/11] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT Gaurav K Singh ` (10 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar This patch is in preparation for the DSI dual link port enable and disable related changes. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 43 ++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 0b18407..a211cf1 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -102,6 +102,36 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, return true; } +static void intel_dsi_port_enable(struct intel_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum pipe pipe = intel_crtc->pipe; + u32 temp; + + /* assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; + temp = temp | intel_dsi->port_bits; + I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(pipe)); +} + +static void intel_dsi_port_disable(struct intel_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + enum pipe pipe = intel_crtc->pipe; + u32 temp; + + /* de-assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(pipe)); + I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(pipe)); +} + static void intel_dsi_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; @@ -141,7 +171,6 @@ static void intel_dsi_enable(struct intel_encoder *encoder) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int pipe = intel_crtc->pipe; - u32 temp; DRM_DEBUG_KMS("\n"); @@ -157,11 +186,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder) wait_for_dsi_fifo_empty(intel_dsi); - /* assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; - temp = temp | intel_dsi->port_bits; - I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); + intel_dsi_port_enable(encoder); } } @@ -245,11 +270,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder) if (is_vid_mode(intel_dsi)) { wait_for_dsi_fifo_empty(intel_dsi); - /* de-assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); - + intel_dsi_port_disable(encoder); msleep(2); } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/11] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh 2014-10-29 8:42 ` [PATCH 01/11] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 03/11] drm/i915: Cleanup in i915_reg.h for all MIPI regs Gaurav K Singh ` (9 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar For dual link MIPI Panels, few packets needs to be sent to Port A or Port C or both. Based on the port no from MIPI Sequence Block#53, these sequences needs to be sent accordingly. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/intel_dsi_cmd.c | 9 +++------ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 3 +++ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 657eb5c..587e71f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -115,6 +115,7 @@ struct intel_dsi { u16 clk_lp_to_hs_count; u16 clk_hs_to_lp_count; + u16 port; u16 init_count; u32 pclk; u16 burst_mode_ratio; diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index f4767fd..eb698b1 100644 --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c @@ -130,8 +130,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, struct drm_encoder *encoder = &intel_dsi->base.base; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum pipe pipe = intel_dsi->port; u32 ctrl_reg; u32 ctrl; u32 mask; @@ -172,8 +171,7 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, struct drm_encoder *encoder = &intel_dsi->base.base; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum pipe pipe = intel_dsi->port; u32 data_reg; int i, j, n; u32 mask; @@ -291,8 +289,7 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi, struct drm_encoder *encoder = &intel_dsi->base.base; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum pipe pipe = intel_dsi->port; int i, len = 0; u32 data_reg, val; diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index f6bdd44..051bfff 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -106,6 +106,8 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data) /* LP or HS mode */ intel_dsi->hs = mode; + /*MIPI Port A or MIPI Port C*/ + intel_dsi->port = port; /* get packet type and increment the pointer */ type = *data++; @@ -280,6 +282,7 @@ static bool generic_init(struct intel_dsi_device *dsi) intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; intel_dsi->lane_count = mipi_config->lane_cnt + 1; intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; + intel_dsi->port = 0; if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) bits_per_pixel = 18; -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/11] drm/i915: Cleanup in i915_reg.h for all MIPI regs. 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh 2014-10-29 8:42 ` [PATCH 01/11] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh 2014-10-29 8:42 ` [PATCH 02/11] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 04/11] drm/i915: Cleanup patch for " Gaurav K Singh ` (8 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar _PORT macro to be used instead of _TRANSCODER macro for all MIPI DSI regs. New macro added for mapping the pipe to MIPI Ports. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_reg.h | 98 +++++++++++++++++++-------------------- 2 files changed, 53 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6a73803..f67a49e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -94,6 +94,7 @@ enum plane { #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') enum port { + INVALID_PORT = -1, PORT_A = 0, PORT_B, PORT_C, @@ -105,6 +106,9 @@ enum port { #define I915_NUM_PHYS_VLV 2 +#define PIPE_MAPPED_TO_MIPI_PORT(pipe) ((pipe) == PIPE_A ? PORT_A : \ + (pipe) == PIPE_B ? PORT_B : INVALID_PORT) + enum dpio_channel { DPIO_CH0, DPIO_CH1 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 77fce96..021f72b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6397,9 +6397,9 @@ enum punit_power_well { /* VLV MIPI registers */ #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) -#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) -#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ - _MIPIB_PORT_CTRL) +#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) +#define MIPI_PORT_CTRL(port) _PORT(port, _MIPIA_PORT_CTRL, \ + _MIPIC_PORT_CTRL) #define DPI_ENABLE (1 << 31) /* A + B */ #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) @@ -6441,7 +6441,7 @@ enum punit_power_well { #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) -#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ +#define MIPI_TEARING_CTRL(port) _PORT(port, \ _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) #define TEARING_EFFECT_DELAY_SHIFT 0 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) @@ -6453,7 +6453,7 @@ enum punit_power_well { #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) -#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ +#define MIPI_DEVICE_READY(port) _PORT(port, _MIPIA_DEVICE_READY, \ _MIPIB_DEVICE_READY) #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ #define ULPS_STATE_MASK (3 << 1) @@ -6464,11 +6464,11 @@ enum punit_power_well { #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) -#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ +#define MIPI_INTR_STAT(port) _PORT(port, _MIPIA_INTR_STAT, \ _MIPIB_INTR_STAT) #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) -#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ +#define MIPI_INTR_EN(port) _PORT(port, _MIPIA_INTR_EN, \ _MIPIB_INTR_EN) #define TEARING_EFFECT (1 << 31) #define SPL_PKT_SENT_INTERRUPT (1 << 30) @@ -6505,7 +6505,7 @@ enum punit_power_well { #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) -#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ +#define MIPI_DSI_FUNC_PRG(port) _PORT(port, _MIPIA_DSI_FUNC_PRG, \ _MIPIB_DSI_FUNC_PRG) #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) #define CMD_MODE_NOT_SUPPORTED (0 << 13) @@ -6529,31 +6529,31 @@ enum punit_power_well { #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) -#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ +#define MIPI_HS_TX_TIMEOUT(port) _PORT(port, _MIPIA_HS_TX_TIMEOUT, \ _MIPIB_HS_TX_TIMEOUT) #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) -#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ +#define MIPI_LP_RX_TIMEOUT(port) _PORT(port, _MIPIA_LP_RX_TIMEOUT, \ _MIPIB_LP_RX_TIMEOUT) #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) -#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ +#define MIPI_TURN_AROUND_TIMEOUT(port) _PORT(port, \ _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) #define TURN_AROUND_TIMEOUT_MASK 0x3f #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) -#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ +#define MIPI_DEVICE_RESET_TIMER(port) _PORT(port, \ _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) #define DEVICE_RESET_TIMER_MASK 0xffff #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) -#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ +#define MIPI_DPI_RESOLUTION(port) _PORT(port, _MIPIA_DPI_RESOLUTION, \ _MIPIB_DPI_RESOLUTION) #define VERTICAL_ADDRESS_SHIFT 16 #define VERTICAL_ADDRESS_MASK (0xffff << 16) @@ -6562,7 +6562,7 @@ enum punit_power_well { #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) -#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ +#define MIPI_DBI_FIFO_THROTTLE(port) _PORT(port, \ _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) #define DBI_FIFO_EMPTY_HALF (0 << 0) #define DBI_FIFO_EMPTY_QUARTER (1 << 0) @@ -6571,49 +6571,49 @@ enum punit_power_well { /* regs below are bits 15:0 */ #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) -#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ +#define MIPI_HSYNC_PADDING_COUNT(port) _PORT(port, \ _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) -#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ +#define MIPI_HBP_COUNT(port) _PORT(port, _MIPIA_HBP_COUNT, \ _MIPIB_HBP_COUNT) #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) -#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ +#define MIPI_HFP_COUNT(port) _PORT(port, _MIPIA_HFP_COUNT, \ _MIPIB_HFP_COUNT) #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) -#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ +#define MIPI_HACTIVE_AREA_COUNT(port) _PORT(port, \ _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) -#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ +#define MIPI_VSYNC_PADDING_COUNT(port) _PORT(port, \ _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) -#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ +#define MIPI_VBP_COUNT(port) _PORT(port, _MIPIA_VBP_COUNT, \ _MIPIB_VBP_COUNT) #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) -#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ +#define MIPI_VFP_COUNT(port) _PORT(port, _MIPIA_VFP_COUNT, \ _MIPIB_VFP_COUNT) #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) -#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ +#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _PORT(port, \ _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) /* regs above are bits 15:0 */ #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) -#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ +#define MIPI_DPI_CONTROL(port) _PORT(port, _MIPIA_DPI_CONTROL, \ _MIPIB_DPI_CONTROL) #define DPI_LP_MODE (1 << 6) #define BACKLIGHT_OFF (1 << 5) @@ -6625,28 +6625,28 @@ enum punit_power_well { #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) -#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ +#define MIPI_DPI_DATA(port) _PORT(port, _MIPIA_DPI_DATA, \ _MIPIB_DPI_DATA) #define COMMAND_BYTE_SHIFT 0 #define COMMAND_BYTE_MASK (0x3f << 0) #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) -#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ +#define MIPI_INIT_COUNT(port) _PORT(port, _MIPIA_INIT_COUNT, \ _MIPIB_INIT_COUNT) #define MASTER_INIT_TIMER_SHIFT 0 #define MASTER_INIT_TIMER_MASK (0xffff << 0) #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) -#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ +#define MIPI_MAX_RETURN_PKT_SIZE(port) _PORT(port, \ _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) #define MAX_RETURN_PKT_SIZE_SHIFT 0 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) -#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ +#define MIPI_VIDEO_MODE_FORMAT(port) _PORT(port, \ _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) #define DISABLE_VIDEO_BTA (1 << 3) @@ -6657,7 +6657,7 @@ enum punit_power_well { #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) -#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ +#define MIPI_EOT_DISABLE(port) _PORT(port, _MIPIA_EOT_DISABLE, \ _MIPIB_EOT_DISABLE) #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) @@ -6670,7 +6670,7 @@ enum punit_power_well { #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) -#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ +#define MIPI_LP_BYTECLK(port) _PORT(port, _MIPIA_LP_BYTECLK, \ _MIPIB_LP_BYTECLK) #define LP_BYTECLK_SHIFT 0 #define LP_BYTECLK_MASK (0xffff << 0) @@ -6678,22 +6678,22 @@ enum punit_power_well { /* bits 31:0 */ #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) -#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ +#define MIPI_LP_GEN_DATA(port) _PORT(port, _MIPIA_LP_GEN_DATA, \ _MIPIB_LP_GEN_DATA) /* bits 31:0 */ #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) -#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ +#define MIPI_HS_GEN_DATA(port) _PORT(port, _MIPIA_HS_GEN_DATA, \ _MIPIB_HS_GEN_DATA) #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) #define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) -#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ +#define MIPI_LP_GEN_CTRL(port) _PORT(port, _MIPIA_LP_GEN_CTRL, \ _MIPIB_LP_GEN_CTRL) #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) #define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) -#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ +#define MIPI_HS_GEN_CTRL(port) _PORT(port, _MIPIA_HS_GEN_CTRL, \ _MIPIB_HS_GEN_CTRL) #define LONG_PACKET_WORD_COUNT_SHIFT 8 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) @@ -6707,7 +6707,7 @@ enum punit_power_well { #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) #define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) -#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ +#define MIPI_GEN_FIFO_STAT(port) _PORT(port, _MIPIA_GEN_FIFO_STAT, \ _MIPIB_GEN_FIFO_STAT) #define DPI_FIFO_EMPTY (1 << 28) #define DBI_FIFO_EMPTY (1 << 27) @@ -6726,7 +6726,7 @@ enum punit_power_well { #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) -#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ +#define MIPI_HS_LP_DBI_ENABLE(port) _PORT(port, \ _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) #define DBI_HS_LP_MODE_MASK (1 << 0) #define DBI_LP_MODE (1 << 0) @@ -6734,7 +6734,7 @@ enum punit_power_well { #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) -#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ +#define MIPI_DPHY_PARAM(port) _PORT(port, _MIPIA_DPHY_PARAM, \ _MIPIB_DPHY_PARAM) #define EXIT_ZERO_COUNT_SHIFT 24 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) @@ -6748,14 +6748,14 @@ enum punit_power_well { /* bits 31:0 */ #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) -#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ +#define MIPI_DBI_BW_CTRL(port) _PORT(port, _MIPIA_DBI_BW_CTRL, \ _MIPIB_DBI_BW_CTRL) #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ + 0xb088) #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ + 0xb888) -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _PORT(port, \ _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) #define LP_HS_SSW_CNT_SHIFT 16 #define LP_HS_SSW_CNT_MASK (0xffff << 16) @@ -6764,18 +6764,18 @@ enum punit_power_well { #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) -#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ +#define MIPI_STOP_STATE_STALL(port) _PORT(port, \ _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) #define STOP_STATE_STALL_COUNTER_SHIFT 0 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) -#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ +#define MIPI_INTR_STAT_REG_1(port) _PORT(port, \ _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) -#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ +#define MIPI_INTR_EN_REG_1(port) _PORT(port, _MIPIA_INTR_EN_REG_1, \ _MIPIB_INTR_EN_REG_1) #define RX_CONTENTION_DETECTED (1 << 0) @@ -6796,7 +6796,7 @@ enum punit_power_well { #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) -#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ +#define MIPI_CTRL(port) _PORT(port, _MIPIA_CTRL, \ _MIPIB_CTRL) #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) @@ -6811,7 +6811,7 @@ enum punit_power_well { #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) -#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ +#define MIPI_DATA_ADDRESS(PORT) _PORT(port, _MIPIA_DATA_ADDRESS, \ _MIPIB_DATA_ADDRESS) #define DATA_MEM_ADDRESS_SHIFT 5 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) @@ -6819,14 +6819,14 @@ enum punit_power_well { #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) -#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ +#define MIPI_DATA_LENGTH(port) _PORT(port, _MIPIA_DATA_LENGTH, \ _MIPIB_DATA_LENGTH) #define DATA_LENGTH_SHIFT 0 #define DATA_LENGTH_MASK (0xfffff << 0) #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) -#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ +#define MIPI_COMMAND_ADDRESS(port) _PORT(port, \ _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) #define COMMAND_MEM_ADDRESS_SHIFT 5 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) @@ -6836,20 +6836,20 @@ enum punit_power_well { #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) -#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ +#define MIPI_COMMAND_LENGTH(port) _PORT(port, _MIPIA_COMMAND_LENGTH, \ _MIPIB_COMMAND_LENGTH) #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) -#define MIPI_READ_DATA_RETURN(tc, n) \ - (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ +#define MIPI_READ_DATA_RETURN(port, n) \ + (_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ + 4 * (n)) /* n: 0...7 */ #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) -#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ +#define MIPI_READ_DATA_VALID(port) _PORT(port, \ _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) #define READ_DATA_VALID(n) (1 << (n)) -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/11] drm/i915: Cleanup patch for MIPI regs 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (2 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 03/11] drm/i915: Cleanup in i915_reg.h for all MIPI regs Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 05/11] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh ` (7 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar All macros of MIPI regs now uses port no instead of pipe no.Based on the pipe, port no is determined and used to read or write MIPI regs during enabling & disbling MIPI encoder. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 133 ++++++++++++++++++---------------- drivers/gpu/drm/i915/intel_dsi_cmd.c | 14 ++-- 2 files changed, 77 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index a211cf1..69828c3 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -108,14 +108,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - enum pipe pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 temp; /* assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; + temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK; temp = temp | intel_dsi->port_bits; - I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); + I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); } static void intel_dsi_port_disable(struct intel_encoder *encoder) @@ -123,20 +123,20 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - enum pipe pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 temp; /* de-assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); + temp = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); } static void intel_dsi_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 val; DRM_DEBUG_KMS("\n"); @@ -150,17 +150,17 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(dev_priv); - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); usleep_range(2500, 3000); - val = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); usleep_range(2500, 3000); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); usleep_range(2500, 3000); } @@ -170,12 +170,12 @@ static void intel_dsi_enable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); DRM_DEBUG_KMS("\n"); if (is_cmd_mode(intel_dsi)) - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); else { msleep(20); /* XXX */ dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); @@ -196,7 +196,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - enum pipe pipe = intel_crtc->pipe; + int pipe = intel_crtc->pipe; u32 tmp; DRM_DEBUG_KMS("\n"); @@ -262,7 +262,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); + u32 temp; DRM_DEBUG_KMS("\n"); @@ -275,21 +276,21 @@ static void intel_dsi_disable(struct intel_encoder *encoder) } /* Panel commands can be sent when clock is in LP11 */ - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); + I915_WRITE(MIPI_DEVICE_READY(port), 0x0); - temp = I915_READ(MIPI_CTRL(pipe)); + temp = I915_READ(MIPI_CTRL(port)); temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(pipe), temp | + I915_WRITE(MIPI_CTRL(port), temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); - I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); - temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); + temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); temp &= ~VID_MODE_FORMAT_MASK; - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); + I915_WRITE(MIPI_DEVICE_READY(port), 0x1); /* if disable packets are sent before sending shutdown packet then in * some next enable sequence send turn on packet error is observed */ @@ -303,29 +304,29 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 val; DRM_DEBUG_KMS("\n"); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) + if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) == 0x00000), 30)) DRM_ERROR("DSI LP not going Low\n"); - val = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); + I915_WRITE(MIPI_DEVICE_READY(port), 0x00); usleep_range(2000, 2500); vlv_disable_dsi_pll(encoder); @@ -458,7 +459,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; unsigned int lane_count = intel_dsi->lane_count; @@ -481,18 +482,18 @@ static void set_dsi_timings(struct drm_encoder *encoder, intel_dsi->burst_mode_ratio); hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); - I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); + I915_WRITE(MIPI_HFP_COUNT(port), hfp); /* meaningful for video mode non-burst sync pulse mode only, can be zero * for non-burst sync events and burst modes */ - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); - I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); + I915_WRITE(MIPI_HBP_COUNT(port), hbp); /* vertical values are in terms of lines */ - I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); - I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); + I915_WRITE(MIPI_VFP_COUNT(port), vfp); + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); + I915_WRITE(MIPI_VBP_COUNT(port), vbp); } static void intel_dsi_prepare(struct intel_encoder *intel_encoder) @@ -504,7 +505,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; - int pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; u32 val, tmp; @@ -517,17 +518,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); /* read request priority is per pipe */ - tmp = I915_READ(MIPI_CTRL(pipe)); + tmp = I915_READ(MIPI_CTRL(port)); tmp &= ~READ_REQUEST_PRIORITY_MASK; - I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); + I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); /* XXX: why here, why like this? handling in irq handler?! */ - I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); - I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); + I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); + I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); - I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); + I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); - I915_WRITE(MIPI_DPI_RESOLUTION(pipe), + I915_WRITE(MIPI_DPI_RESOLUTION(port), adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); @@ -543,7 +544,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) /* XXX: cross-check bpp vs. pixel format? */ val |= intel_dsi->pixel_format; } - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); /* timeouts for recovery. one frame IIUC. if counter expires, EOT and * stop state. */ @@ -564,25 +565,26 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) if (is_vid_mode(intel_dsi) && intel_dsi->video_mode_format == VIDEO_MODE_BURST) { - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } else { - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->vtotal * adjusted_mode->htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } - I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); - I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); + I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); + I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); /* dphy stuff */ /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); + I915_WRITE(MIPI_INIT_COUNT(port), + txclkesc(intel_dsi->escape_clk_div, 100)); val = 0; if (intel_dsi->eotp_pkt == 0) @@ -592,17 +594,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) val |= CLOCKSTOP; /* recovery disables */ - I915_WRITE(MIPI_EOT_DISABLE(pipe), val); + I915_WRITE(MIPI_EOT_DISABLE(port), val); /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); + I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); /* in terms of txbyteclkhs. actual high to low switch + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. * * XXX: write MIPI_STOP_STATE_STALL? */ - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), intel_dsi->hs_to_lp_count); /* XXX: low power clock equivalence in terms of byte clock. the number @@ -610,16 +612,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) * and txclkesc. txclkesc time / txbyteclk time * (105 + * MIPI_STOP_STATE_STALL) / 105.??? */ - I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); + I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); /* the bw essential for transmitting 16 long packets containing 252 * bytes meant for dcs write memory command is programmed in this * register in terms of byte clocks. based on dsi transfer rate and the * number of lanes configured the time taken to transmit 16 long packets * in a dsi stream varies. */ - I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); + I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); @@ -627,7 +629,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) /* Some panels might have resolution which is not a multiple of * 64 like 1366 x 768. Enable RANDOM resolution support for such * panels by default */ - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | @@ -783,7 +785,12 @@ void intel_dsi_init(struct drm_device *dev) } intel_encoder->type = INTEL_OUTPUT_DSI; - intel_encoder->crtc_mask = (1 << 0); /* XXX */ + + /*Pipe A with MIPI DSI Port A, Pipe B with MIPI DSI Port C */ + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) + intel_encoder->crtc_mask = (1 << 0); + else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) + intel_encoder->crtc_mask = (1 << 1); intel_encoder->cloneable = 0; drm_connector_init(dev, connector, &intel_dsi_connector_funcs, diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index eb698b1..9cfa832 100644 --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c @@ -392,7 +392,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 mask; /* XXX: pipe, hs */ @@ -402,16 +402,16 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) cmd |= DPI_LP_MODE; /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT); + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe))) + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); - I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd); + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); mask = SPL_PKT_SENT_INTERRUPT; - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100)) + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); return 0; @@ -423,12 +423,12 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 mask; mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) DRM_ERROR("DPI FIFOs are not empty\n"); } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/11] drm/i915: Add support for port enable/disable for dual link configuration 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (3 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 04/11] drm/i915: Cleanup patch for " Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 06/11] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh ` (6 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar For Dual Link MIPI Panels, both Port A and Port C should be enabled during the MIPI encoder enabling sequence. Similarly, during the disabling sequence, both ports needs to be disabled. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dsi.c | 55 ++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 1 + 4 files changed, 47 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 021f72b..b2fc92b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6403,6 +6403,7 @@ enum punit_power_well { #define DPI_ENABLE (1 << 31) /* A + B */ #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) +#define DUAL_LINK_MODE_SHIFT 26 #define DUAL_LINK_MODE_MASK (1 << 26) #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 69828c3..2c30b61 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -108,14 +108,33 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum pipe pipe = intel_crtc->pipe; int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); - u32 temp; - - /* assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK; - temp = temp | intel_dsi->port_bits; - I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(port)); + u32 temp, port_control = 0; + + if (intel_dsi->dual_link) { + port_control = (intel_dsi->dual_link - 1) + << DUAL_LINK_MODE_SHIFT; + port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B : + LANE_CONFIGURATION_DUAL_LINK_A; + /*For Port A */ + temp = I915_READ(MIPI_PORT_CTRL(0)); + temp = temp | port_control; + I915_WRITE(MIPI_PORT_CTRL(0), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(0)); + + /* For Port C */ + temp = I915_READ(MIPI_PORT_CTRL(1)); + I915_WRITE(MIPI_PORT_CTRL(1), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(1)); + } else { + /* assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(port)) & + ~LANE_CONFIGURATION_MASK; + temp = temp | intel_dsi->port_bits; + I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); + } } static void intel_dsi_port_disable(struct intel_encoder *encoder) @@ -123,13 +142,26 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 temp; - /* de-assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(port)); - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(port)); + if (intel_dsi->dual_link) { + /*For Port A */ + temp = I915_READ(MIPI_PORT_CTRL(0)); + I915_WRITE(MIPI_PORT_CTRL(0), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(0)); + + /* For Port C */ + temp = I915_READ(MIPI_PORT_CTRL(1)); + I915_WRITE(MIPI_PORT_CTRL(1), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(1)); + } else { + /* de-assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); + } } static void intel_dsi_device_ready(struct intel_encoder *encoder) @@ -505,6 +537,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; + enum pipe pipe = intel_crtc->pipe; int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; u32 val, tmp; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 587e71f..950ab41 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -101,6 +101,7 @@ struct intel_dsi { u8 clock_stop; u8 escape_clk_div; + u8 dual_link; u32 port_bits; u32 bw_timer; u32 dphy_reg; diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 051bfff..d424ebc 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -283,6 +283,7 @@ static bool generic_init(struct intel_dsi_device *dsi) intel_dsi->lane_count = mipi_config->lane_cnt + 1; intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; intel_dsi->port = 0; + intel_dsi->dual_link = mipi_config->dual_link; if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) bits_per_pixel = 18; -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/11] drm/i915: Pixel Clock changes for DSI dual link 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (4 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 05/11] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 07/11] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh ` (5 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap can be enabled if needed by panel, then in that case, pixel clock will be increased for extra pixels. v2 : Address review comments by Jani - Removed the bit mask used for ->dual_link - Used DSI instead of MIPI for #define variables Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_bios.h | 3 ++- drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++ drivers/gpu/drm/i915/intel_dsi.h | 6 ++++++ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 21 +++++++++++++++++++++ 5 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2fc92b..d50092d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5847,6 +5847,10 @@ enum punit_power_well { #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) #define VLV_PWRDWNUPCTL 0xA294 +#define VLV_CHICKEN_3 0x7040C +#define PIXEL_OVERLAP_CNT_MASK (3 << 30) +#define PIXEL_OVERLAP_CNT_SHIFT 30 + #define GEN6_PMISR 0x44020 #define GEN6_PMIMR 0x44024 /* rps_lock */ #define GEN6_PMIIR 0x44028 diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index 7603765..39dfb65 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -798,7 +798,8 @@ struct mipi_config { #define DUAL_LINK_PIXEL_ALT 2 u16 dual_link:2; u16 lane_cnt:2; - u16 rsvd3:12; + u16 pixel_overlap:3; + u16 rsvd3:9; u16 rsvd4; diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 2c30b61..c285b4a 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -117,6 +117,14 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder) << DUAL_LINK_MODE_SHIFT; port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B : LANE_CONFIGURATION_DUAL_LINK_A; + + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { + temp = I915_READ(VLV_CHICKEN_3); + temp &= ~PIXEL_OVERLAP_CNT_MASK | + intel_dsi->pixel_overlap << + PIXEL_OVERLAP_CNT_SHIFT; + I915_WRITE(VLV_CHICKEN_3, temp); + } /*For Port A */ temp = I915_READ(MIPI_PORT_CTRL(0)); temp = temp | port_control; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 950ab41..89d9c63 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -28,6 +28,11 @@ #include <drm/drm_crtc.h> #include "intel_drv.h" +/* Dual Link support */ +#define DSI_DUAL_LINK_NONE 0 +#define DSI_DUAL_LINK_FRONT_BACK 1 +#define DSI_DUAL_LINK_PIXEL_ALT 2 + struct intel_dsi_device { unsigned int panel_id; const char *name; @@ -102,6 +107,7 @@ struct intel_dsi { u8 escape_clk_div; u8 dual_link; + u8 pixel_overlap; u32 port_bits; u32 bw_timer; u32 dphy_reg; diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index d424ebc..2f2806e 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -284,6 +284,7 @@ static bool generic_init(struct intel_dsi_device *dsi) intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; intel_dsi->port = 0; intel_dsi->dual_link = mipi_config->dual_link; + intel_dsi->pixel_overlap = mipi_config->pixel_overlap; if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) bits_per_pixel = 18; @@ -303,6 +304,20 @@ static bool generic_init(struct intel_dsi_device *dsi) pclk = mode->clock; + /* In dual link mode each port needs half of pixel clock */ + if (intel_dsi->dual_link) { + pclk = pclk / 2; + + /* we can enable pixel_overlap if needed by panel. In this + * case we need to increase the pixelclock for extra pixels + */ + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { + pclk += DIV_ROUND_UP(mode->vtotal * + intel_dsi->pixel_overlap * + 60, 1000); + } + } + /* Burst Mode Ratio * Target ddr frequency from VBT / non burst ddr freq * multiply by 100 to preserve remainder @@ -497,6 +512,12 @@ static bool generic_init(struct intel_dsi_device *dsi) DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? "disabled" : "enabled"); DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); + else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) + DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); + else + DRM_DEBUG_KMS("Dual link: NONE\n"); DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/11] drm/i915: Dual link needs Shutdown and Turn on packet for both ports 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (5 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 06/11] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 08/11] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh ` (4 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet to be sent to both Ports during MIPI encoder enabling sequence. v2: Address review comments by Jani - Used a for loop instead of do-while loop. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi_cmd.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index 9cfa832..aecc27c 100644 --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c @@ -394,6 +394,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 mask; + int count; /* XXX: pipe, hs */ if (hs) @@ -401,19 +402,26 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) else cmd |= DPI_LP_MODE; - /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); - - /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) - DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); - - I915_WRITE(MIPI_DPI_CONTROL(port), cmd); - - mask = SPL_PKT_SENT_INTERRUPT; - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) - DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); - + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + /* clear bit */ + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); + + /* XXX: old code skips write if control unchanged */ + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) + DRM_ERROR("Same special packet %02x twice in a row.\n", + cmd); + + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); + + mask = SPL_PKT_SENT_INTERRUPT; + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == + mask, 100)) + DRM_ERROR("Video mode command 0x%08x send failed.\n", + cmd); + /* For dual link */ + if (intel_dsi->dual_link) + port = PORT_B; + } return 0; } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/11] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (6 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 07/11] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 09/11] drm/i915: MIPI Timings related changes for " Gaurav K Singh ` (3 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled. v2: Address review comments by Jani - Added wait time for PLL to be locked. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi_pll.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index fa7a6ca..93d8e9a 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder) dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; + if (intel_dsi->dual_link) + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; + DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); @@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder) tmp |= DSI_PLL_VCO_EN; vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); - mutex_unlock(&dev_priv->dpio_lock); - - if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) { + if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & + DSI_PLL_LOCK, 20)) { DRM_ERROR("DSI PLL lock failed\n"); return; } + mutex_unlock(&dev_priv->dpio_lock); DRM_DEBUG_KMS("DSI PLL locked\n"); } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/11] drm/i915: MIPI Timings related changes for dual link 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (7 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 08/11] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 10/11] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh ` (2 subsequent siblings) 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels. Accordingly timing related mmio regs needs to be programmed for both MIPI Ports. v2: Address review comments by Jani - Used a for loop instead of do-while loop Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index c285b4a..e00dcd8 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -504,12 +504,23 @@ static void set_dsi_timings(struct drm_encoder *encoder, unsigned int lane_count = intel_dsi->lane_count; u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; + int count; hactive = mode->hdisplay; hfp = mode->hsync_start - mode->hdisplay; hsync = mode->hsync_end - mode->hsync_start; hbp = mode->htotal - mode->hsync_end; + if (intel_dsi->dual_link) { + hactive /= 2; + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + hactive += intel_dsi->pixel_overlap; + hfp /= 2; + hsync /= 2; + hbp /= 2; + count = 2; + } + vfp = mode->vsync_start - mode->vdisplay; vsync = mode->vsync_end - mode->vsync_start; vbp = mode->vtotal - mode->vsync_end; @@ -522,18 +533,23 @@ static void set_dsi_timings(struct drm_encoder *encoder, intel_dsi->burst_mode_ratio); hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); - I915_WRITE(MIPI_HFP_COUNT(port), hfp); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); + I915_WRITE(MIPI_HFP_COUNT(port), hfp); - /* meaningful for video mode non-burst sync pulse mode only, can be zero - * for non-burst sync events and burst modes */ - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); - I915_WRITE(MIPI_HBP_COUNT(port), hbp); + /* meaningful for video mode non-burst sync pulse mode only, + * can be zero for non-burst sync events and burst modes */ + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); + I915_WRITE(MIPI_HBP_COUNT(port), hbp); - /* vertical values are in terms of lines */ - I915_WRITE(MIPI_VFP_COUNT(port), vfp); - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); - I915_WRITE(MIPI_VBP_COUNT(port), vbp); + /* vertical values are in terms of lines */ + I915_WRITE(MIPI_VFP_COUNT(port), vfp); + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); + I915_WRITE(MIPI_VBP_COUNT(port), vbp); + + if (intel_dsi->dual_link) + port = PORT_B; + } } static void intel_dsi_prepare(struct intel_encoder *intel_encoder) -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/11] drm/i915: Update the DSI disable path to support dual link panel disabling 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (8 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 09/11] drm/i915: MIPI Timings related changes for " Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-10-29 8:42 ` [PATCH 11/11] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh 2014-11-13 14:53 ` [PATCH 00/11] BYT DSI Dual Link Support Kumar, Shobhit 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar We need to program both port registers during dual link disable path. v2: Address review comments by Jani - Used a for loop instead of do-while loop. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 68 +++++++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index e00dcd8..512ccbc 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -303,8 +303,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder) struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); - u32 temp; + int count; DRM_DEBUG_KMS("\n"); @@ -315,23 +315,27 @@ static void intel_dsi_disable(struct intel_encoder *encoder) msleep(2); } - /* Panel commands can be sent when clock is in LP11 */ - I915_WRITE(MIPI_DEVICE_READY(port), 0x0); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + /* Panel commands can be sent when clock is in LP11 */ + I915_WRITE(MIPI_DEVICE_READY(port), 0x0); - temp = I915_READ(MIPI_CTRL(port)); - temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(port), temp | - intel_dsi->escape_clk_div << - ESCAPE_CLOCK_DIVIDER_SHIFT); + temp = I915_READ(MIPI_CTRL(port)); + temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; + I915_WRITE(MIPI_CTRL(port), temp | + intel_dsi->escape_clk_div << + ESCAPE_CLOCK_DIVIDER_SHIFT); - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); - temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); - temp &= ~VID_MODE_FORMAT_MASK; - I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); + temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); + temp &= ~VID_MODE_FORMAT_MASK; + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); - I915_WRITE(MIPI_DEVICE_READY(port), 0x1); + I915_WRITE(MIPI_DEVICE_READY(port), 0x1); + if (intel_dsi->dual_link) + port = PORT_B; + } /* if disable packets are sent before sending shutdown packet then in * some next enable sequence send turn on packet error is observed */ if (intel_dsi->dev.dev_ops->disable) @@ -344,30 +348,40 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 val; + int count; DRM_DEBUG_KMS("\n"); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); - usleep_range(2000, 2500); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | + ULPS_STATE_ENTER); + usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); - usleep_range(2000, 2500); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | + ULPS_STATE_EXIT); + usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); - usleep_range(2000, 2500); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | + ULPS_STATE_ENTER); + usleep_range(2000, 2500); - if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) - == 0x00000), 30)) - DRM_ERROR("DSI LP not going Low\n"); + if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) + == 0x00000), 30)) + DRM_ERROR("DSI LP not going Low\n"); - val = I915_READ(MIPI_PORT_CTRL(port)); - I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); - usleep_range(1000, 1500); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); + usleep_range(1000, 1500); + + I915_WRITE(MIPI_DEVICE_READY(port), 0x00); + usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), 0x00); - usleep_range(2000, 2500); + if (intel_dsi->dual_link) + port = PORT_B; + } vlv_disable_dsi_pll(encoder); } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/11] drm/i915: Update the DSI enable path to support dual link panel enabling 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (9 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 10/11] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh @ 2014-10-29 8:42 ` Gaurav K Singh 2014-11-13 14:53 ` [PATCH 00/11] BYT DSI Dual Link Support Kumar, Shobhit 11 siblings, 0 replies; 28+ messages in thread From: Gaurav K Singh @ 2014-10-29 8:42 UTC (permalink / raw) To: intel-gfx; +Cc: Shobhit Kumar We need to program both port registers during dual link enable path. v2: Address review comments by Jani - Used a for loop instead of do-while loop. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 255 ++++++++++++++++++++++---------------- 1 file changed, 145 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 512ccbc..727385b 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -176,8 +176,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); u32 val; + int count; DRM_DEBUG_KMS("\n"); @@ -190,18 +192,24 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(dev_priv); - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); - usleep_range(2500, 3000); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); + usleep_range(2500, 3000); - val = I915_READ(MIPI_PORT_CTRL(port)); - I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); - usleep_range(1000, 1500); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); + usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); - usleep_range(2500, 3000); + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); + usleep_range(2500, 3000); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); - usleep_range(2500, 3000); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); + usleep_range(2500, 3000); + + if (intel_dsi->dual_link) + port = PORT_B; + } } static void intel_dsi_enable(struct intel_encoder *encoder) @@ -579,32 +587,48 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; u32 val, tmp; + int count; + u16 mode_hactive; DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); - /* escape clock divider, 20MHz, shared for A and C. device ready must be - * off when doing this! txclkesc? */ - tmp = I915_READ(MIPI_CTRL(0)); - tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); - - /* read request priority is per pipe */ - tmp = I915_READ(MIPI_CTRL(port)); - tmp &= ~READ_REQUEST_PRIORITY_MASK; - I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); - - /* XXX: why here, why like this? handling in irq handler?! */ - I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); - I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); - - I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); + mode_hactive = adjusted_mode->hdisplay; + if (intel_dsi->dual_link) { + mode_hactive /= 2; + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + mode_hactive += intel_dsi->pixel_overlap; + } - I915_WRITE(MIPI_DPI_RESOLUTION(port), - adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | - adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + /* escape clock divider, 20MHz, shared for A and C. + * device ready must be off when doing this! txclkesc? */ + tmp = I915_READ(MIPI_CTRL(0)); + tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; + I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); + + /* read request priority is per pipe */ + tmp = I915_READ(MIPI_CTRL(port)); + tmp &= ~READ_REQUEST_PRIORITY_MASK; + I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); + + /* XXX: why here, why like this? handling in irq handler?! */ + I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); + I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); + + I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); + + I915_WRITE(MIPI_DPI_RESOLUTION(port), + adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | + mode_hactive << HORIZONTAL_ADDRESS_SHIFT); + if (intel_dsi->dual_link) + port = PORT_B; + } set_dsi_timings(encoder, adjusted_mode); + if (intel_dsi->dual_link) + port = PORT_A; + val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; if (is_cmd_mode(intel_dsi)) { val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; @@ -615,96 +639,107 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) /* XXX: cross-check bpp vs. pixel format? */ val |= intel_dsi->pixel_format; } - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); - - /* timeouts for recovery. one frame IIUC. if counter expires, EOT and - * stop state. */ + tmp = 0; + if (intel_dsi->eotp_pkt == 0) + tmp |= EOT_DISABLE; - /* - * In burst mode, value greater than one DPI line Time in byte clock - * (txbyteclkhs) To timeout this timer 1+ of the above said value is - * recommended. - * - * In non-burst mode, Value greater than one DPI frame time in byte - * clock(txbyteclkhs) To timeout this timer 1+ of the above said value - * is recommended. - * - * In DBI only mode, value greater than one DBI frame time in byte - * clock(txbyteclkhs) To timeout this timer 1+ of the above said value - * is recommended. - */ + if (intel_dsi->clock_stop) + tmp |= CLOCKSTOP; - if (is_vid_mode(intel_dsi) && - intel_dsi->video_mode_format == VIDEO_MODE_BURST) { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->htotal, bpp, - intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); - } else { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->vtotal * - adjusted_mode->htotal, - bpp, intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); - } - I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); - I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); + for (count = 0; count < (intel_dsi->dual_link ? 2 : 1); count++) { + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); + + /* timeouts for recovery. one frame IIUC. if counter expires, + * EOT and stop state. */ + + /* + * In burst mode, value greater than one DPI line Time in byte + * clock (txbyteclkhs) To timeout this timer 1+ of the above + * said value is recommended. + * + * In non-burst mode, Value greater than one DPI frame time in + * byte clock(txbyteclkhs) To timeout this timer 1+ of the + * above said value is recommended. + * + * In DBI only mode, value greater than one DBI frame time in + * byte clock(txbyteclkhs) To timeout this timer 1+ of the + * above said value is recommended. + */ + + if (is_vid_mode(intel_dsi) && + intel_dsi->video_mode_format == VIDEO_MODE_BURST) { + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->htotal, bpp, + intel_dsi->lane_count, + intel_dsi->burst_mode_ratio) + 1); + } else { + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->vtotal * + adjusted_mode->htotal, + bpp, intel_dsi->lane_count, + intel_dsi->burst_mode_ratio) + 1); + } + I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), + intel_dsi->turn_arnd_val); + I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), + intel_dsi->rst_timer_val); - /* dphy stuff */ + /* dphy stuff */ - /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), + /* in terms of low power clock */ + I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); - val = 0; - if (intel_dsi->eotp_pkt == 0) - val |= EOT_DISABLE; - - if (intel_dsi->clock_stop) - val |= CLOCKSTOP; - - /* recovery disables */ - I915_WRITE(MIPI_EOT_DISABLE(port), val); - - /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); + /* recovery disables */ + I915_WRITE(MIPI_EOT_DISABLE(port), tmp); + + /* in terms of low power clock */ + I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); + + /* in terms of txbyteclkhs. actual high to low switch + + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. + * + * XXX: write MIPI_STOP_STATE_STALL? + */ + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), + intel_dsi->hs_to_lp_count); + + /* XXX: low power clock equivalence in terms of byte clock. + * the number of byte clocks occupied in one low power clock. + * based on txbyteclkhs and txclkesc. + * txclkesc time / txbyteclk time * (105 + + * MIPI_STOP_STATE_STALL) / 105.??? + */ + I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); + + /* the bw essential for transmitting 16 long packets containing + * 252 bytes meant for dcs write memory command is programmed + * in this register in terms of byte clocks. based on dsi + * transfer rate and the number of lanes configured the time + * taken to transmit 16 long packets in a dsi stream varies. + */ + I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); + + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), + intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | + intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); + + if (is_vid_mode(intel_dsi)) + /* Some panels might have resolution which is not a + * multiple of 64 like 1366 x 768. Enable RANDOM + * resolution support for such panels by default + */ + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), + intel_dsi->video_frmt_cfg_bits | + intel_dsi->video_mode_format | + IP_TG_CONFIG | + RANDOM_DPI_DISPLAY_RESOLUTION); - /* in terms of txbyteclkhs. actual high to low switch + - * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. - * - * XXX: write MIPI_STOP_STATE_STALL? - */ - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), - intel_dsi->hs_to_lp_count); + if (intel_dsi->dual_link) + port = PORT_B; - /* XXX: low power clock equivalence in terms of byte clock. the number - * of byte clocks occupied in one low power clock. based on txbyteclkhs - * and txclkesc. txclkesc time / txbyteclk time * (105 + - * MIPI_STOP_STATE_STALL) / 105.??? - */ - I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); - - /* the bw essential for transmitting 16 long packets containing 252 - * bytes meant for dcs write memory command is programmed in this - * register in terms of byte clocks. based on dsi transfer rate and the - * number of lanes configured the time taken to transmit 16 long packets - * in a dsi stream varies. */ - I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); - - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), - intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | - intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); - - if (is_vid_mode(intel_dsi)) - /* Some panels might have resolution which is not a multiple of - * 64 like 1366 x 768. Enable RANDOM resolution support for such - * panels by default */ - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), - intel_dsi->video_frmt_cfg_bits | - intel_dsi->video_mode_format | - IP_TG_CONFIG | - RANDOM_DPI_DISPLAY_RESOLUTION); + } } static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 00/11] BYT DSI Dual Link Support 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh ` (10 preceding siblings ...) 2014-10-29 8:42 ` [PATCH 11/11] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh @ 2014-11-13 14:53 ` Kumar, Shobhit 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula 11 siblings, 1 reply; 28+ messages in thread From: Kumar, Shobhit @ 2014-11-13 14:53 UTC (permalink / raw) To: intel-gfx On 10/29/2014 2:12 PM, Gaurav K Singh wrote: > Hi, > > These set of patches build on top of the existing DSI Video mode support to > enable dual link MIPI panels with high resolutions. These patches have been > tested on a 25x16 panel and works well. > > v2: Commit message added to all patches. All review comments of Jani, Nikula > have been addressed in the second version of patches. > Jani, Damien, can you guys have a look at these updated Dual link patches. Regards Shobhit _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 0/3] BYT DSI Dual Link Support 2014-11-13 14:53 ` [PATCH 00/11] BYT DSI Dual Link Support Kumar, Shobhit @ 2014-11-14 14:54 ` Jani Nikula 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula ` (3 more replies) 0 siblings, 4 replies; 28+ messages in thread From: Jani Nikula @ 2014-11-14 14:54 UTC (permalink / raw) To: intel-gfx, shobhit.kumar, gaurav.k.singh; +Cc: jani.nikula Hi Shobhit and Gaurav - I've been pondering this whole MIPI DSI pipes vs. ports thing and discussing with Ville and others. Rather than try and fail in explaining the ideas, here are some concrete patches to describe what I'd like to be done first. The most important thing is that we don't confuse the pipes and ports. Getting confused was easy with the pipe B mapping to port C, and the register defines being very confused/confusing about it. These patches attempt to fix that. Before adding dual link support, there's a simple function mapping the pipe to port. Next up is expanding that to handle multiple ports driven from one pipe. That's handled by adding intel_dsi->ports bitmap that has the bit set for each port that is to be driven. I've added the bitmap and some helpers to iterate over the configured ports, but there's no actual support for doing the configuration. I'm hoping you could take over from here. There's a sample patch about the usage. I'm sorry it's taken me so long to reply. With the new stuff coming in, I really think it's important to get the foundation right first. Especially because I'm to blame for getting some of the port/pipe stuff confused in the first place... BR, Jani. Jani Nikula (3): drm/i915/dsi: clean up MIPI DSI pipe vs. port usage drm/i915/dsi: add ports to intel_dsi to describe the ports being driven drm/i915/dsi: an example how to handle dual link for each port drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- drivers/gpu/drm/i915/intel_dsi.c | 151 ++++++++--------- drivers/gpu/drm/i915/intel_dsi.h | 19 +++ drivers/gpu/drm/i915/intel_dsi_cmd.c | 76 ++++----- 4 files changed, 290 insertions(+), 259 deletions(-) -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula @ 2014-11-14 14:54 ` Jani Nikula 2014-11-26 17:20 ` Singh, Gaurav K 2014-11-27 7:28 ` Singh, Gaurav K 2014-11-14 14:54 ` [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven Jani Nikula ` (2 subsequent siblings) 3 siblings, 2 replies; 28+ messages in thread From: Jani Nikula @ 2014-11-14 14:54 UTC (permalink / raw) To: intel-gfx, shobhit.kumar, gaurav.k.singh; +Cc: jani.nikula MIPI DSI works on ports A and C, which map to pipes A and B, respectively. Things are going to get more complicated with the introduction of dual link DSI support, so clean up the register defines and code to match reality. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- drivers/gpu/drm/i915/intel_dsi.c | 148 ++++++++--------- drivers/gpu/drm/i915/intel_dsi.h | 16 ++ drivers/gpu/drm/i915/intel_dsi_cmd.c | 64 ++++---- 4 files changed, 277 insertions(+), 254 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a143127eb451..250043f3f22e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -31,6 +31,8 @@ #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ (pipe) == PIPE_B ? (b) : (c)) +#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ + (port) == PORT_B ? (b) : (c)) #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) #define _MASKED_BIT_DISABLE(a) ((a) << 16) @@ -1492,7 +1494,7 @@ enum punit_power_well { #define I915_ISP_INTERRUPT (1<<22) #define I915_LPE_PIPE_B_INTERRUPT (1<<21) #define I915_LPE_PIPE_A_INTERRUPT (1<<20) -#define I915_MIPIB_INTERRUPT (1<<19) +#define I915_MIPIC_INTERRUPT (1<<19) #define I915_MIPIA_INTERRUPT (1<<18) #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) #define I915_DISPLAY_PORT_INTERRUPT (1<<17) @@ -6612,29 +6614,30 @@ enum punit_power_well { #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) -/* VLV MIPI registers */ +/* MIPI DSI registers */ + +#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) -#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) -#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ - _MIPIB_PORT_CTRL) -#define DPI_ENABLE (1 << 31) /* A + B */ +#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) +#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) +#define DPI_ENABLE (1 << 31) /* A + C */ #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) #define DUAL_LINK_MODE_MASK (1 << 26) #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) -#define DITHERING_ENABLE (1 << 25) /* A + B */ +#define DITHERING_ENABLE (1 << 25) /* A + C */ #define FLOPPED_HSTX (1 << 23) #define DE_INVERT (1 << 19) /* XXX */ #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) #define AFE_LATCHOUT (1 << 17) #define LP_OUTPUT_HOLD (1 << 16) -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) -#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 -#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) +#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 +#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) #define CSB_SHIFT 9 #define CSB_MASK (3 << 9) #define CSB_20MHZ (0 << 9) @@ -6643,10 +6646,10 @@ enum punit_power_well { #define BANDGAP_MASK (1 << 8) #define BANDGAP_PNW_CIRCUIT (0 << 8) #define BANDGAP_LNC_CIRCUIT (1 << 8) -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) -#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ -#define TEARING_EFFECT_SHIFT 2 /* A + B */ +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) +#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ +#define TEARING_EFFECT_SHIFT 2 /* A + C */ #define TEARING_EFFECT_MASK (3 << 2) #define TEARING_EFFECT_OFF (0 << 2) #define TEARING_EFFECT_DSI (1 << 2) @@ -6658,9 +6661,9 @@ enum punit_power_well { #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) -#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) -#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ - _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) +#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) +#define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ + _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) #define TEARING_EFFECT_DELAY_SHIFT 0 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) @@ -6670,9 +6673,9 @@ enum punit_power_well { /* MIPI DSI Controller and D-PHY registers */ #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) -#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) -#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ - _MIPIB_DEVICE_READY) +#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) +#define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ + _MIPIC_DEVICE_READY) #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ #define ULPS_STATE_MASK (3 << 1) #define ULPS_STATE_ENTER (2 << 1) @@ -6681,13 +6684,13 @@ enum punit_power_well { #define DEVICE_READY (1 << 0) #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) -#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) -#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ - _MIPIB_INTR_STAT) +#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) +#define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ + _MIPIC_INTR_STAT) #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) -#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) -#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ - _MIPIB_INTR_EN) +#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) +#define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ + _MIPIC_INTR_EN) #define TEARING_EFFECT (1 << 31) #define SPL_PKT_SENT_INTERRUPT (1 << 30) #define GEN_READ_DATA_AVAIL (1 << 29) @@ -6722,9 +6725,9 @@ enum punit_power_well { #define RXSOT_ERROR (1 << 0) #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) -#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) -#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ - _MIPIB_DSI_FUNC_PRG) +#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) +#define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ + _MIPIC_DSI_FUNC_PRG) #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) #define CMD_MODE_NOT_SUPPORTED (0 << 13) #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) @@ -6746,93 +6749,93 @@ enum punit_power_well { #define DATA_LANES_PRG_REG_MASK (7 << 0) #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) -#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) -#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ - _MIPIB_HS_TX_TIMEOUT) +#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) +#define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ + _MIPIC_HS_TX_TIMEOUT) #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) -#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) -#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ - _MIPIB_LP_RX_TIMEOUT) +#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) +#define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ + _MIPIC_LP_RX_TIMEOUT) #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) -#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) -#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ - _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) +#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) +#define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ + _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) #define TURN_AROUND_TIMEOUT_MASK 0x3f #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) -#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) -#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ - _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) +#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) +#define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ + _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) #define DEVICE_RESET_TIMER_MASK 0xffff #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) -#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) -#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ - _MIPIB_DPI_RESOLUTION) +#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) +#define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ + _MIPIC_DPI_RESOLUTION) #define VERTICAL_ADDRESS_SHIFT 16 #define VERTICAL_ADDRESS_MASK (0xffff << 16) #define HORIZONTAL_ADDRESS_SHIFT 0 #define HORIZONTAL_ADDRESS_MASK 0xffff #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) -#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) -#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ - _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) +#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) +#define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ + _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) #define DBI_FIFO_EMPTY_HALF (0 << 0) #define DBI_FIFO_EMPTY_QUARTER (1 << 0) #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) /* regs below are bits 15:0 */ #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) -#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) -#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ - _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) +#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) +#define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ + _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) -#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) -#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ - _MIPIB_HBP_COUNT) +#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) +#define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ + _MIPIC_HBP_COUNT) #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) -#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) -#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ - _MIPIB_HFP_COUNT) +#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) +#define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ + _MIPIC_HFP_COUNT) #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) -#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) -#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ - _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) +#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) +#define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ + _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) -#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) -#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ - _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) +#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) +#define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ + _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) -#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) -#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ - _MIPIB_VBP_COUNT) +#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) +#define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ + _MIPIC_VBP_COUNT) #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) -#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) -#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ - _MIPIB_VFP_COUNT) +#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) +#define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ + _MIPIC_VFP_COUNT) #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) -#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) -#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ - _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) +#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) +#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ + _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) /* regs above are bits 15:0 */ #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) -#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) -#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ - _MIPIB_DPI_CONTROL) +#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) +#define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ + _MIPIC_DPI_CONTROL) #define DPI_LP_MODE (1 << 6) #define BACKLIGHT_OFF (1 << 5) #define BACKLIGHT_ON (1 << 4) @@ -6842,30 +6845,30 @@ enum punit_power_well { #define SHUTDOWN (1 << 0) #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) -#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) -#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ - _MIPIB_DPI_DATA) +#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) +#define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ + _MIPIC_DPI_DATA) #define COMMAND_BYTE_SHIFT 0 #define COMMAND_BYTE_MASK (0x3f << 0) #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) -#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) -#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ - _MIPIB_INIT_COUNT) +#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) +#define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ + _MIPIC_INIT_COUNT) #define MASTER_INIT_TIMER_SHIFT 0 #define MASTER_INIT_TIMER_MASK (0xffff << 0) #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) -#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) -#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) +#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) +#define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ + _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) #define MAX_RETURN_PKT_SIZE_SHIFT 0 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) -#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) -#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ - _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) +#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) +#define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ + _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) #define DISABLE_VIDEO_BTA (1 << 3) #define IP_TG_CONFIG (1 << 2) @@ -6874,9 +6877,9 @@ enum punit_power_well { #define VIDEO_MODE_BURST (3 << 0) #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) -#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) -#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ - _MIPIB_EOT_DISABLE) +#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) +#define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ + _MIPIC_EOT_DISABLE) #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) @@ -6887,32 +6890,32 @@ enum punit_power_well { #define EOT_DISABLE (1 << 0) #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) -#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) -#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ - _MIPIB_LP_BYTECLK) +#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) +#define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ + _MIPIC_LP_BYTECLK) #define LP_BYTECLK_SHIFT 0 #define LP_BYTECLK_MASK (0xffff << 0) /* bits 31:0 */ #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) -#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) -#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ - _MIPIB_LP_GEN_DATA) +#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) +#define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ + _MIPIC_LP_GEN_DATA) /* bits 31:0 */ #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) -#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) -#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ - _MIPIB_HS_GEN_DATA) +#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) +#define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ + _MIPIC_HS_GEN_DATA) #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) -#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) -#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ - _MIPIB_LP_GEN_CTRL) +#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) +#define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ + _MIPIC_LP_GEN_CTRL) #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) -#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) -#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ - _MIPIB_HS_GEN_CTRL) +#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) +#define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ + _MIPIC_HS_GEN_CTRL) #define LONG_PACKET_WORD_COUNT_SHIFT 8 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) #define SHORT_PACKET_PARAM_SHIFT 8 @@ -6924,9 +6927,9 @@ enum punit_power_well { /* data type values, see include/video/mipi_display.h */ #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) -#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) -#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ - _MIPIB_GEN_FIFO_STAT) +#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) +#define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ + _MIPIC_GEN_FIFO_STAT) #define DPI_FIFO_EMPTY (1 << 28) #define DBI_FIFO_EMPTY (1 << 27) #define LP_CTRL_FIFO_EMPTY (1 << 26) @@ -6943,17 +6946,17 @@ enum punit_power_well { #define HS_DATA_FIFO_FULL (1 << 0) #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) -#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) -#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ - _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) +#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) +#define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ + _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) #define DBI_HS_LP_MODE_MASK (1 << 0) #define DBI_LP_MODE (1 << 0) #define DBI_HS_MODE (0 << 0) #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) -#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) -#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ - _MIPIB_DPHY_PARAM) +#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) +#define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ + _MIPIC_DPHY_PARAM) #define EXIT_ZERO_COUNT_SHIFT 24 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) #define TRAIL_COUNT_SHIFT 16 @@ -6965,36 +6968,36 @@ enum punit_power_well { /* bits 31:0 */ #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) -#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) -#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ - _MIPIB_DBI_BW_CTRL) +#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) +#define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ + _MIPIC_DBI_BW_CTRL) #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ + 0xb088) -#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ + 0xb888) -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ - _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ + _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) #define LP_HS_SSW_CNT_SHIFT 16 #define LP_HS_SSW_CNT_MASK (0xffff << 16) #define HS_LP_PWR_SW_CNT_SHIFT 0 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) -#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) -#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ - _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) +#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) +#define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ + _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) #define STOP_STATE_STALL_COUNTER_SHIFT 0 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) -#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) -#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ - _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) +#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) +#define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ + _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) -#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) -#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ - _MIPIB_INTR_EN_REG_1) +#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) +#define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ + _MIPIC_INTR_EN_REG_1) #define RX_CONTENTION_DETECTED (1 << 0) /* XXX: only pipe A ?!? */ @@ -7013,9 +7016,9 @@ enum punit_power_well { /* MIPI adapter registers */ #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) -#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) -#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ - _MIPIB_CTRL) +#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) +#define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ + _MIPIC_CTRL) #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) @@ -7028,24 +7031,24 @@ enum punit_power_well { #define RGB_FLIP_TO_BGR (1 << 2) #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) -#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) -#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ - _MIPIB_DATA_ADDRESS) +#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) +#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ + _MIPIC_DATA_ADDRESS) #define DATA_MEM_ADDRESS_SHIFT 5 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) #define DATA_VALID (1 << 0) #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) -#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) -#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ - _MIPIB_DATA_LENGTH) +#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) +#define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ + _MIPIC_DATA_LENGTH) #define DATA_LENGTH_SHIFT 0 #define DATA_LENGTH_MASK (0xfffff << 0) #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) -#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) -#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ - _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) +#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) +#define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ + _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) #define COMMAND_MEM_ADDRESS_SHIFT 5 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) #define AUTO_PWG_ENABLE (1 << 2) @@ -7053,22 +7056,22 @@ enum punit_power_well { #define COMMAND_VALID (1 << 0) #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) -#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) -#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ - _MIPIB_COMMAND_LENGTH) +#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) +#define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ + _MIPIC_COMMAND_LENGTH) #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) -#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) -#define MIPI_READ_DATA_RETURN(tc, n) \ - (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ +#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) +#define MIPI_READ_DATA_RETURN(port, n) \ + (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ + 4 * (n)) /* n: 0...7 */ #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) -#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) -#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ - _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) +#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) +#define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ + _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) #define READ_DATA_VALID(n) (1 << (n)) /* For UMS only (deprecated): */ diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 0b184079de14..35842a6687d8 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -106,7 +106,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 val; DRM_DEBUG_KMS("\n"); @@ -120,17 +120,17 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(dev_priv); - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); usleep_range(2500, 3000); - val = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); usleep_range(2500, 3000); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); usleep_range(2500, 3000); } @@ -140,13 +140,13 @@ static void intel_dsi_enable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 temp; DRM_DEBUG_KMS("\n"); if (is_cmd_mode(intel_dsi)) - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); else { msleep(20); /* XXX */ dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); @@ -158,10 +158,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder) wait_for_dsi_fifo_empty(intel_dsi); /* assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; + temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK; temp = temp | intel_dsi->port_bits; - I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); + I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); } } @@ -237,7 +237,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 temp; DRM_DEBUG_KMS("\n"); @@ -246,29 +246,29 @@ static void intel_dsi_disable(struct intel_encoder *encoder) wait_for_dsi_fifo_empty(intel_dsi); /* de-assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(pipe)); + temp = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(port)); msleep(2); } /* Panel commands can be sent when clock is in LP11 */ - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); + I915_WRITE(MIPI_DEVICE_READY(port), 0x0); - temp = I915_READ(MIPI_CTRL(pipe)); + temp = I915_READ(MIPI_CTRL(port)); temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(pipe), temp | + I915_WRITE(MIPI_CTRL(port), temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); - I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); - temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); + temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); temp &= ~VID_MODE_FORMAT_MASK; - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); + I915_WRITE(MIPI_DEVICE_READY(port), 0x1); /* if disable packets are sent before sending shutdown packet then in * some next enable sequence send turn on packet error is observed */ @@ -282,29 +282,29 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 val; DRM_DEBUG_KMS("\n"); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) + if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) == 0x00000), 30)) DRM_ERROR("DSI LP not going Low\n"); - val = I915_READ(MIPI_PORT_CTRL(pipe)); - I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); + val = I915_READ(MIPI_PORT_CTRL(port)); + I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); + I915_WRITE(MIPI_DEVICE_READY(port), 0x00); usleep_range(2000, 2500); vlv_disable_dsi_pll(encoder); @@ -338,8 +338,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; enum intel_display_power_domain power_domain; - u32 port, func; - enum pipe p; + u32 port_ctl, func; + enum port port; DRM_DEBUG_KMS("\n"); @@ -348,13 +348,13 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, return false; /* XXX: this only works for one DSI output */ - for (p = PIPE_A; p <= PIPE_B; p++) { - port = I915_READ(MIPI_PORT_CTRL(p)); - func = I915_READ(MIPI_DSI_FUNC_PRG(p)); + for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) { + port_ctl = I915_READ(MIPI_PORT_CTRL(port)); + func = I915_READ(MIPI_DSI_FUNC_PRG(port)); - if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { - if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { - *pipe = p; + if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { + if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { + *pipe = port == PORT_A ? PIPE_A : PIPE_C; return true; } } @@ -437,7 +437,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; unsigned int lane_count = intel_dsi->lane_count; @@ -460,18 +460,18 @@ static void set_dsi_timings(struct drm_encoder *encoder, intel_dsi->burst_mode_ratio); hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); - I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); + I915_WRITE(MIPI_HFP_COUNT(port), hfp); /* meaningful for video mode non-burst sync pulse mode only, can be zero * for non-burst sync events and burst modes */ - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); - I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); + I915_WRITE(MIPI_HBP_COUNT(port), hbp); /* vertical values are in terms of lines */ - I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); - I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); + I915_WRITE(MIPI_VFP_COUNT(port), vfp); + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); + I915_WRITE(MIPI_VBP_COUNT(port), vbp); } static void intel_dsi_prepare(struct intel_encoder *intel_encoder) @@ -483,30 +483,30 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct drm_display_mode *adjusted_mode = &intel_crtc->config.adjusted_mode; - int pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); unsigned int bpp = intel_crtc->config.pipe_bpp; u32 val, tmp; - DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); + DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); /* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ - tmp = I915_READ(MIPI_CTRL(0)); + tmp = I915_READ(MIPI_CTRL(PORT_A)); tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); + I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); /* read request priority is per pipe */ - tmp = I915_READ(MIPI_CTRL(pipe)); + tmp = I915_READ(MIPI_CTRL(port)); tmp &= ~READ_REQUEST_PRIORITY_MASK; - I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); + I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); /* XXX: why here, why like this? handling in irq handler?! */ - I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); - I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); + I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); + I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); - I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); + I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); - I915_WRITE(MIPI_DPI_RESOLUTION(pipe), + I915_WRITE(MIPI_DPI_RESOLUTION(port), adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); @@ -522,7 +522,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) /* XXX: cross-check bpp vs. pixel format? */ val |= intel_dsi->pixel_format; } - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); /* timeouts for recovery. one frame IIUC. if counter expires, EOT and * stop state. */ @@ -543,25 +543,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) if (is_vid_mode(intel_dsi) && intel_dsi->video_mode_format == VIDEO_MODE_BURST) { - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } else { - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->vtotal * adjusted_mode->htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } - I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); - I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); + I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); + I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); /* dphy stuff */ /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); + I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); val = 0; if (intel_dsi->eotp_pkt == 0) @@ -571,17 +571,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) val |= CLOCKSTOP; /* recovery disables */ - I915_WRITE(MIPI_EOT_DISABLE(pipe), val); + I915_WRITE(MIPI_EOT_DISABLE(port), val); /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); + I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); /* in terms of txbyteclkhs. actual high to low switch + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. * * XXX: write MIPI_STOP_STATE_STALL? */ - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), intel_dsi->hs_to_lp_count); /* XXX: low power clock equivalence in terms of byte clock. the number @@ -589,16 +589,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) * and txclkesc. txclkesc time / txbyteclk time * (105 + * MIPI_STOP_STATE_STALL) / 105.??? */ - I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); + I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); /* the bw essential for transmitting 16 long packets containing 252 * bytes meant for dcs write memory command is programmed in this * register in terms of byte clocks. based on dsi transfer rate and the * number of lanes configured the time taken to transmit 16 long packets * in a dsi stream varies. */ - I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); + I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); @@ -606,7 +606,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) /* Some panels might have resolution which is not a multiple of * 64 like 1366 x 768. Enable RANDOM resolution support for such * panels by default */ - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | @@ -748,6 +748,12 @@ void intel_dsi_init(struct drm_device *dev) intel_connector->get_hw_state = intel_connector_get_hw_state; intel_connector->unregister = intel_connector_unregister; + /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) + intel_encoder->crtc_mask = (1 << PIPE_A); + else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) + intel_encoder->crtc_mask = (1 << PIPE_B); + for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { dsi = &intel_dsi_devices[i]; intel_dsi->dev = *dsi; @@ -762,8 +768,6 @@ void intel_dsi_init(struct drm_device *dev) } intel_encoder->type = INTEL_OUTPUT_DSI; - intel_encoder->crtc_mask = (1 << 0); /* XXX */ - intel_encoder->cloneable = 0; drm_connector_init(dev, connector, &intel_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 657eb5c1b9d8..97a6f621774f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -127,6 +127,22 @@ struct intel_dsi { u16 panel_pwr_cycle_delay; }; +/* XXX: Transitional before dual port configuration */ +static inline enum port intel_dsi_pipe_to_port(enum pipe pipe) +{ + if (pipe == PIPE_A) + return PORT_A; + else if (pipe == PIPE_B) + return PORT_C; + + WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe)); + return PORT_C; +} + +#define for_each_dsi_port(__port, __ports_mask) \ + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ + if ((__ports_mask) & (1 << (__port))) + static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) { return container_of(encoder, struct intel_dsi, base.base); diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index f4767fd2ebeb..004fa918ca03 100644 --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c @@ -54,15 +54,15 @@ static void print_stat(struct intel_dsi *intel_dsi) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 val; - val = I915_READ(MIPI_INTR_STAT(pipe)); + val = I915_READ(MIPI_INTR_STAT(port)); #define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : "" - DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x" + DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x" "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" - "\n", pipe, val, + "\n", port_name(port), val, STAT_BIT(val, TEARING_EFFECT), STAT_BIT(val, SPL_PKT_SENT_INTERRUPT), STAT_BIT(val, GEN_READ_DATA_AVAIL), @@ -110,16 +110,16 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 temp; u32 mask = DBI_FIFO_EMPTY; - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50)) + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 50)) DRM_ERROR("Timeout waiting for DBI FIFO empty\n"); - temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe)); + temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(port)); temp &= DBI_HS_LP_MODE_MASK; - I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE); + I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), enable ? DBI_HS_MODE : DBI_LP_MODE); intel_dsi->hs = enable; } @@ -131,7 +131,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 ctrl_reg; u32 ctrl; u32 mask; @@ -140,14 +140,14 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, channel, data_type, data); if (intel_dsi->hs) { - ctrl_reg = MIPI_HS_GEN_CTRL(pipe); + ctrl_reg = MIPI_HS_GEN_CTRL(port); mask = HS_CTRL_FIFO_FULL; } else { - ctrl_reg = MIPI_LP_GEN_CTRL(pipe); + ctrl_reg = MIPI_LP_GEN_CTRL(port); mask = LP_CTRL_FIFO_FULL; } - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) { + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) { DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); print_stat(intel_dsi); } @@ -173,7 +173,7 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 data_reg; int i, j, n; u32 mask; @@ -182,14 +182,14 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, channel, data_type, len); if (intel_dsi->hs) { - data_reg = MIPI_HS_GEN_DATA(pipe); + data_reg = MIPI_HS_GEN_DATA(port); mask = HS_DATA_FIFO_FULL; } else { - data_reg = MIPI_LP_GEN_DATA(pipe); + data_reg = MIPI_LP_GEN_DATA(port); mask = LP_DATA_FIFO_FULL; } - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); for (i = 0; i < len; i += n) { @@ -292,14 +292,14 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); int i, len = 0; u32 data_reg, val; if (intel_dsi->hs) { - data_reg = MIPI_HS_GEN_DATA(pipe); + data_reg = MIPI_HS_GEN_DATA(port); } else { - data_reg = MIPI_LP_GEN_DATA(pipe); + data_reg = MIPI_LP_GEN_DATA(port); } while (len < buflen) { @@ -318,7 +318,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 mask; int ret; @@ -327,14 +327,14 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, * longer than MIPI_MAX_RETURN_PKT_SIZE */ - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd); if (ret) return ret; mask = GEN_READ_DATA_AVAIL; - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) DRM_ERROR("Timeout waiting for read data.\n"); ret = dsi_read_data_return(intel_dsi, buf, buflen); @@ -354,7 +354,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 mask; int ret; @@ -363,7 +363,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, * longer than MIPI_MAX_RETURN_PKT_SIZE */ - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata, reqlen); @@ -371,7 +371,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, return ret; mask = GEN_READ_DATA_AVAIL; - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) DRM_ERROR("Timeout waiting for read data.\n"); ret = dsi_read_data_return(intel_dsi, buf, buflen); @@ -395,7 +395,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 mask; /* XXX: pipe, hs */ @@ -405,16 +405,16 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) cmd |= DPI_LP_MODE; /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT); + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe))) + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); - I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd); + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); mask = SPL_PKT_SENT_INTERRUPT; - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100)) + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); return 0; @@ -426,12 +426,12 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum pipe pipe = intel_crtc->pipe; + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); u32 mask; mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) DRM_ERROR("DPI FIFOs are not empty\n"); } -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula @ 2014-11-26 17:20 ` Singh, Gaurav K 2014-11-26 18:08 ` Daniel Vetter 2014-11-27 7:28 ` Singh, Gaurav K 1 sibling, 1 reply; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-26 17:20 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar On 11/14/2014 8:24 PM, Jani Nikula wrote: > MIPI DSI works on ports A and C, which map to pipes A and B, > respectively. Things are going to get more complicated with the > introduction of dual link DSI support, so clean up the register defines > and code to match reality. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dsi.c | 148 ++++++++--------- > drivers/gpu/drm/i915/intel_dsi.h | 16 ++ > drivers/gpu/drm/i915/intel_dsi_cmd.c | 64 ++++---- > 4 files changed, 277 insertions(+), 254 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a143127eb451..250043f3f22e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -31,6 +31,8 @@ > #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) > #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ > (pipe) == PIPE_B ? (b) : (c)) > +#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ > + (port) == PORT_B ? (b) : (c)) > > #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) > #define _MASKED_BIT_DISABLE(a) ((a) << 16) > @@ -1492,7 +1494,7 @@ enum punit_power_well { > #define I915_ISP_INTERRUPT (1<<22) > #define I915_LPE_PIPE_B_INTERRUPT (1<<21) > #define I915_LPE_PIPE_A_INTERRUPT (1<<20) > -#define I915_MIPIB_INTERRUPT (1<<19) > +#define I915_MIPIC_INTERRUPT (1<<19) > #define I915_MIPIA_INTERRUPT (1<<18) > #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) > #define I915_DISPLAY_PORT_INTERRUPT (1<<17) > @@ -6612,29 +6614,30 @@ enum punit_power_well { > #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) > #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) > > -/* VLV MIPI registers */ > +/* MIPI DSI registers */ > + > +#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ > > #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) > -#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > -#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ > - _MIPIB_PORT_CTRL) > -#define DPI_ENABLE (1 << 31) /* A + B */ > +#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > +#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > +#define DPI_ENABLE (1 << 31) /* A + C */ > #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 > #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) > #define DUAL_LINK_MODE_MASK (1 << 26) > #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) > #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) > -#define DITHERING_ENABLE (1 << 25) /* A + B */ > +#define DITHERING_ENABLE (1 << 25) /* A + C */ > #define FLOPPED_HSTX (1 << 23) > #define DE_INVERT (1 << 19) /* XXX */ > #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 > #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) > #define AFE_LATCHOUT (1 << 17) > #define LP_OUTPUT_HOLD (1 << 16) > -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 > -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) > -#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 > -#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) > +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 > +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) > +#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 > +#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) > #define CSB_SHIFT 9 > #define CSB_MASK (3 << 9) > #define CSB_20MHZ (0 << 9) > @@ -6643,10 +6646,10 @@ enum punit_power_well { > #define BANDGAP_MASK (1 << 8) > #define BANDGAP_PNW_CIRCUIT (0 << 8) > #define BANDGAP_LNC_CIRCUIT (1 << 8) > -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 > -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) > -#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ > -#define TEARING_EFFECT_SHIFT 2 /* A + B */ > +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 > +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) > +#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ > +#define TEARING_EFFECT_SHIFT 2 /* A + C */ > #define TEARING_EFFECT_MASK (3 << 2) > #define TEARING_EFFECT_OFF (0 << 2) > #define TEARING_EFFECT_DSI (1 << 2) > @@ -6658,9 +6661,9 @@ enum punit_power_well { > #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) > > #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) > -#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > -#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ > - _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) > +#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > +#define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ > + _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > #define TEARING_EFFECT_DELAY_SHIFT 0 > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > @@ -6670,9 +6673,9 @@ enum punit_power_well { > /* MIPI DSI Controller and D-PHY registers */ > > #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) > -#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) > -#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ > - _MIPIB_DEVICE_READY) > +#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) > +#define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ > + _MIPIC_DEVICE_READY) > #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ > #define ULPS_STATE_MASK (3 << 1) > #define ULPS_STATE_ENTER (2 << 1) > @@ -6681,13 +6684,13 @@ enum punit_power_well { > #define DEVICE_READY (1 << 0) > > #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) > -#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) > -#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ > - _MIPIB_INTR_STAT) > +#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) > +#define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ > + _MIPIC_INTR_STAT) > #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) > -#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) > -#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ > - _MIPIB_INTR_EN) > +#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) > +#define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ > + _MIPIC_INTR_EN) > #define TEARING_EFFECT (1 << 31) > #define SPL_PKT_SENT_INTERRUPT (1 << 30) > #define GEN_READ_DATA_AVAIL (1 << 29) > @@ -6722,9 +6725,9 @@ enum punit_power_well { > #define RXSOT_ERROR (1 << 0) > > #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) > -#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) > -#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ > - _MIPIB_DSI_FUNC_PRG) > +#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) > +#define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ > + _MIPIC_DSI_FUNC_PRG) > #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) > #define CMD_MODE_NOT_SUPPORTED (0 << 13) > #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) > @@ -6746,93 +6749,93 @@ enum punit_power_well { > #define DATA_LANES_PRG_REG_MASK (7 << 0) > > #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) > -#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) > -#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ > - _MIPIB_HS_TX_TIMEOUT) > +#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) > +#define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ > + _MIPIC_HS_TX_TIMEOUT) > #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff > > #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) > -#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) > -#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ > - _MIPIB_LP_RX_TIMEOUT) > +#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) > +#define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ > + _MIPIC_LP_RX_TIMEOUT) > #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff > > #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) > -#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) > -#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ > - _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) > +#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) > +#define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ > + _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > #define TURN_AROUND_TIMEOUT_MASK 0x3f > > #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) > -#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) > -#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ > - _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) > +#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) > +#define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ > + _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > #define DEVICE_RESET_TIMER_MASK 0xffff > > #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) > -#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) > -#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ > - _MIPIB_DPI_RESOLUTION) > +#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) > +#define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ > + _MIPIC_DPI_RESOLUTION) > #define VERTICAL_ADDRESS_SHIFT 16 > #define VERTICAL_ADDRESS_MASK (0xffff << 16) > #define HORIZONTAL_ADDRESS_SHIFT 0 > #define HORIZONTAL_ADDRESS_MASK 0xffff > > #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) > -#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) > -#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ > - _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) > +#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) > +#define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ > + _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > #define DBI_FIFO_EMPTY_HALF (0 << 0) > #define DBI_FIFO_EMPTY_QUARTER (1 << 0) > #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) > > /* regs below are bits 15:0 */ > #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) > -#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) > -#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) > +#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) > +#define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > > #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) > -#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) > -#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ > - _MIPIB_HBP_COUNT) > +#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) > +#define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ > + _MIPIC_HBP_COUNT) > > #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) > -#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) > -#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ > - _MIPIB_HFP_COUNT) > +#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) > +#define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ > + _MIPIC_HFP_COUNT) > > #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) > -#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) > -#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) > +#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) > +#define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > > #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) > -#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) > -#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) > +#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) > +#define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > > #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) > -#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) > -#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ > - _MIPIB_VBP_COUNT) > +#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) > +#define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ > + _MIPIC_VBP_COUNT) > > #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) > -#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) > -#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ > - _MIPIB_VFP_COUNT) > +#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) > +#define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ > + _MIPIC_VFP_COUNT) > > #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) > -#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) > -#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) > +#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) > +#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > > /* regs above are bits 15:0 */ > > #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) > -#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) > -#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ > - _MIPIB_DPI_CONTROL) > +#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) > +#define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ > + _MIPIC_DPI_CONTROL) > #define DPI_LP_MODE (1 << 6) > #define BACKLIGHT_OFF (1 << 5) > #define BACKLIGHT_ON (1 << 4) > @@ -6842,30 +6845,30 @@ enum punit_power_well { > #define SHUTDOWN (1 << 0) > > #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) > -#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) > -#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ > - _MIPIB_DPI_DATA) > +#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) > +#define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ > + _MIPIC_DPI_DATA) > #define COMMAND_BYTE_SHIFT 0 > #define COMMAND_BYTE_MASK (0x3f << 0) > > #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) > -#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) > -#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ > - _MIPIB_INIT_COUNT) > +#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) > +#define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ > + _MIPIC_INIT_COUNT) > #define MASTER_INIT_TIMER_SHIFT 0 > #define MASTER_INIT_TIMER_MASK (0xffff << 0) > > #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) > -#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) > -#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ > - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) > +#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) > +#define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ > + _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > #define MAX_RETURN_PKT_SIZE_SHIFT 0 > #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) > > #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) > -#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) > -#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ > - _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) > +#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) > +#define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ > + _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) > #define DISABLE_VIDEO_BTA (1 << 3) > #define IP_TG_CONFIG (1 << 2) > @@ -6874,9 +6877,9 @@ enum punit_power_well { > #define VIDEO_MODE_BURST (3 << 0) > > #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) > -#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) > -#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ > - _MIPIB_EOT_DISABLE) > +#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) > +#define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ > + _MIPIC_EOT_DISABLE) > #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) > #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) > #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) > @@ -6887,32 +6890,32 @@ enum punit_power_well { > #define EOT_DISABLE (1 << 0) > > #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) > -#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) > -#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ > - _MIPIB_LP_BYTECLK) > +#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) > +#define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ > + _MIPIC_LP_BYTECLK) > #define LP_BYTECLK_SHIFT 0 > #define LP_BYTECLK_MASK (0xffff << 0) > > /* bits 31:0 */ > #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) > -#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) > -#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ > - _MIPIB_LP_GEN_DATA) > +#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) > +#define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ > + _MIPIC_LP_GEN_DATA) > > /* bits 31:0 */ > #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) > -#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) > -#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ > - _MIPIB_HS_GEN_DATA) > +#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) > +#define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ > + _MIPIC_HS_GEN_DATA) > > #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) > -#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) > -#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ > - _MIPIB_LP_GEN_CTRL) > +#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) > +#define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ > + _MIPIC_LP_GEN_CTRL) > #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) > -#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) > -#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ > - _MIPIB_HS_GEN_CTRL) > +#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) > +#define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ > + _MIPIC_HS_GEN_CTRL) > #define LONG_PACKET_WORD_COUNT_SHIFT 8 > #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) > #define SHORT_PACKET_PARAM_SHIFT 8 > @@ -6924,9 +6927,9 @@ enum punit_power_well { > /* data type values, see include/video/mipi_display.h */ > > #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) > -#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) > -#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ > - _MIPIB_GEN_FIFO_STAT) > +#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) > +#define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ > + _MIPIC_GEN_FIFO_STAT) > #define DPI_FIFO_EMPTY (1 << 28) > #define DBI_FIFO_EMPTY (1 << 27) > #define LP_CTRL_FIFO_EMPTY (1 << 26) > @@ -6943,17 +6946,17 @@ enum punit_power_well { > #define HS_DATA_FIFO_FULL (1 << 0) > > #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) > -#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) > -#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ > - _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) > +#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) > +#define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ > + _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > #define DBI_HS_LP_MODE_MASK (1 << 0) > #define DBI_LP_MODE (1 << 0) > #define DBI_HS_MODE (0 << 0) > > #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) > -#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) > -#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ > - _MIPIB_DPHY_PARAM) > +#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) > +#define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ > + _MIPIC_DPHY_PARAM) > #define EXIT_ZERO_COUNT_SHIFT 24 > #define EXIT_ZERO_COUNT_MASK (0x3f << 24) > #define TRAIL_COUNT_SHIFT 16 > @@ -6965,36 +6968,36 @@ enum punit_power_well { > > /* bits 31:0 */ > #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) > -#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) > -#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ > - _MIPIB_DBI_BW_CTRL) > +#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) > +#define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ > + _MIPIC_DBI_BW_CTRL) > > #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > + 0xb088) > -#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > + 0xb888) > -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ > - _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) > +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ > + _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > #define LP_HS_SSW_CNT_SHIFT 16 > #define LP_HS_SSW_CNT_MASK (0xffff << 16) > #define HS_LP_PWR_SW_CNT_SHIFT 0 > #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) > > #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) > -#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) > -#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ > - _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) > +#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) > +#define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ > + _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > #define STOP_STATE_STALL_COUNTER_SHIFT 0 > #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) > > #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) > -#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) > -#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ > - _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) > +#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) > +#define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ > + _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) > -#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) > -#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ > - _MIPIB_INTR_EN_REG_1) > +#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) > +#define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ > + _MIPIC_INTR_EN_REG_1) > #define RX_CONTENTION_DETECTED (1 << 0) > > /* XXX: only pipe A ?!? */ > @@ -7013,9 +7016,9 @@ enum punit_power_well { > /* MIPI adapter registers */ > > #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) > -#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) > -#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ > - _MIPIB_CTRL) > +#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) > +#define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ > + _MIPIC_CTRL) > #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ > #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) > #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) > @@ -7028,24 +7031,24 @@ enum punit_power_well { > #define RGB_FLIP_TO_BGR (1 << 2) > > #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) > -#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) > -#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ > - _MIPIB_DATA_ADDRESS) > +#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) > +#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ > + _MIPIC_DATA_ADDRESS) > #define DATA_MEM_ADDRESS_SHIFT 5 > #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define DATA_VALID (1 << 0) > > #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) > -#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) > -#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ > - _MIPIB_DATA_LENGTH) > +#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) > +#define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ > + _MIPIC_DATA_LENGTH) > #define DATA_LENGTH_SHIFT 0 > #define DATA_LENGTH_MASK (0xfffff << 0) > > #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) > -#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) > -#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ > - _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) > +#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) > +#define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ > + _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > #define COMMAND_MEM_ADDRESS_SHIFT 5 > #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define AUTO_PWG_ENABLE (1 << 2) > @@ -7053,22 +7056,22 @@ enum punit_power_well { > #define COMMAND_VALID (1 << 0) > > #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) > -#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) > -#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ > - _MIPIB_COMMAND_LENGTH) > +#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) > +#define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ > + _MIPIC_COMMAND_LENGTH) > #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ > #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) > > #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) > -#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) > -#define MIPI_READ_DATA_RETURN(tc, n) \ > - (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ > +#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) > +#define MIPI_READ_DATA_RETURN(port, n) \ > + (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ > + 4 * (n)) /* n: 0...7 */ > > #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) > -#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) > -#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ > - _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) > +#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) > +#define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ > + _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > #define READ_DATA_VALID(n) (1 << (n)) > > /* For UMS only (deprecated): */ > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 0b184079de14..35842a6687d8 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -106,7 +106,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > DRM_DEBUG_KMS("\n"); > @@ -120,17 +120,17 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > /* bandgap reset is needed after everytime we do power gate */ > band_gap_reset(dev_priv); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); > usleep_range(2500, 3000); > > - val = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); > + val = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); > + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); > usleep_range(2500, 3000); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); > usleep_range(2500, 3000); > } > > @@ -140,13 +140,13 @@ static void intel_dsi_enable(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > > DRM_DEBUG_KMS("\n"); > > if (is_cmd_mode(intel_dsi)) > - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); > + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); > else { > msleep(20); /* XXX */ > dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); > @@ -158,10 +158,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder) > wait_for_dsi_fifo_empty(intel_dsi); > > /* assert ip_tg_enable signal */ > - temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; > + temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK; > temp = temp | intel_dsi->port_bits; > - I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); > - POSTING_READ(MIPI_PORT_CTRL(pipe)); > + I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); > + POSTING_READ(MIPI_PORT_CTRL(port)); > } > } > > @@ -237,7 +237,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > > DRM_DEBUG_KMS("\n"); > @@ -246,29 +246,29 @@ static void intel_dsi_disable(struct intel_encoder *encoder) > wait_for_dsi_fifo_empty(intel_dsi); > > /* de-assert ip_tg_enable signal */ > - temp = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); > - POSTING_READ(MIPI_PORT_CTRL(pipe)); > + temp = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); > + POSTING_READ(MIPI_PORT_CTRL(port)); > > msleep(2); > } > > /* Panel commands can be sent when clock is in LP11 */ > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x0); > > - temp = I915_READ(MIPI_CTRL(pipe)); > + temp = I915_READ(MIPI_CTRL(port)); > temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - I915_WRITE(MIPI_CTRL(pipe), temp | > + I915_WRITE(MIPI_CTRL(port), temp | > intel_dsi->escape_clk_div << > ESCAPE_CLOCK_DIVIDER_SHIFT); > > - I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); > + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); > > - temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); > + temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); > temp &= ~VID_MODE_FORMAT_MASK; > - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); > + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x1); > > /* if disable packets are sent before sending shutdown packet then in > * some next enable sequence send turn on packet error is observed */ > @@ -282,29 +282,29 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > DRM_DEBUG_KMS("\n"); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); > usleep_range(2000, 2500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > - if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) > + if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) > == 0x00000), 30)) > DRM_ERROR("DSI LP not going Low\n"); > > - val = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); > + val = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x00); > usleep_range(2000, 2500); > > vlv_disable_dsi_pll(encoder); > @@ -338,8 +338,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > enum intel_display_power_domain power_domain; > - u32 port, func; > - enum pipe p; > + u32 port_ctl, func; > + enum port port; > > DRM_DEBUG_KMS("\n"); > > @@ -348,13 +348,13 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > return false; > > /* XXX: this only works for one DSI output */ > - for (p = PIPE_A; p <= PIPE_B; p++) { > - port = I915_READ(MIPI_PORT_CTRL(p)); > - func = I915_READ(MIPI_DSI_FUNC_PRG(p)); > + for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) { > + port_ctl = I915_READ(MIPI_PORT_CTRL(port)); > + func = I915_READ(MIPI_DSI_FUNC_PRG(port)); > > - if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { > - if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { > - *pipe = p; > + if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { > + if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { > + *pipe = port == PORT_A ? PIPE_A : PIPE_C; > return true; > } > } > @@ -437,7 +437,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > unsigned int bpp = intel_crtc->config.pipe_bpp; > unsigned int lane_count = intel_dsi->lane_count; > > @@ -460,18 +460,18 @@ static void set_dsi_timings(struct drm_encoder *encoder, > intel_dsi->burst_mode_ratio); > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); > > - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); > - I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); > + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); > + I915_WRITE(MIPI_HFP_COUNT(port), hfp); > > /* meaningful for video mode non-burst sync pulse mode only, can be zero > * for non-burst sync events and burst modes */ > - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); > - I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); > + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); > + I915_WRITE(MIPI_HBP_COUNT(port), hbp); > > /* vertical values are in terms of lines */ > - I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); > - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); > - I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); > + I915_WRITE(MIPI_VFP_COUNT(port), vfp); > + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); > + I915_WRITE(MIPI_VBP_COUNT(port), vbp); > } > > static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > @@ -483,30 +483,30 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > struct drm_display_mode *adjusted_mode = > &intel_crtc->config.adjusted_mode; > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > unsigned int bpp = intel_crtc->config.pipe_bpp; > u32 val, tmp; > > - DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); > + DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); > > /* escape clock divider, 20MHz, shared for A and C. device ready must be > * off when doing this! txclkesc? */ > - tmp = I915_READ(MIPI_CTRL(0)); > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); > + I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); > > /* read request priority is per pipe */ > - tmp = I915_READ(MIPI_CTRL(pipe)); > + tmp = I915_READ(MIPI_CTRL(port)); > tmp &= ~READ_REQUEST_PRIORITY_MASK; > - I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); > + I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); > > /* XXX: why here, why like this? handling in irq handler?! */ > - I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); > - I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); > + I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); > + I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); > > - I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); > + I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); > > - I915_WRITE(MIPI_DPI_RESOLUTION(pipe), > + I915_WRITE(MIPI_DPI_RESOLUTION(port), > adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | > adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); > > @@ -522,7 +522,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > /* XXX: cross-check bpp vs. pixel format? */ > val |= intel_dsi->pixel_format; > } > - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); > + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); > > /* timeouts for recovery. one frame IIUC. if counter expires, EOT and > * stop state. */ > @@ -543,25 +543,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > > if (is_vid_mode(intel_dsi) && > intel_dsi->video_mode_format == VIDEO_MODE_BURST) { > - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), > + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), > txbyteclkhs(adjusted_mode->htotal, bpp, > intel_dsi->lane_count, > intel_dsi->burst_mode_ratio) + 1); > } else { > - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), > + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), > txbyteclkhs(adjusted_mode->vtotal * > adjusted_mode->htotal, > bpp, intel_dsi->lane_count, > intel_dsi->burst_mode_ratio) + 1); > } > - I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); > - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); > - I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); > + I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); > + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); > + I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); > > /* dphy stuff */ > > /* in terms of low power clock */ > - I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); > + I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); > > val = 0; > if (intel_dsi->eotp_pkt == 0) > @@ -571,17 +571,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > val |= CLOCKSTOP; > > /* recovery disables */ > - I915_WRITE(MIPI_EOT_DISABLE(pipe), val); > + I915_WRITE(MIPI_EOT_DISABLE(port), val); > > /* in terms of low power clock */ > - I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); > + I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); > > /* in terms of txbyteclkhs. actual high to low switch + > * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. > * > * XXX: write MIPI_STOP_STATE_STALL? > */ > - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), > + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), > intel_dsi->hs_to_lp_count); > > /* XXX: low power clock equivalence in terms of byte clock. the number > @@ -589,16 +589,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > * and txclkesc. txclkesc time / txbyteclk time * (105 + > * MIPI_STOP_STATE_STALL) / 105.??? > */ > - I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); > + I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); > > /* the bw essential for transmitting 16 long packets containing 252 > * bytes meant for dcs write memory command is programmed in this > * register in terms of byte clocks. based on dsi transfer rate and the > * number of lanes configured the time taken to transmit 16 long packets > * in a dsi stream varies. */ > - I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); > + I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); > > - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), > + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), > intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | > intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); > > @@ -606,7 +606,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > /* Some panels might have resolution which is not a multiple of > * 64 like 1366 x 768. Enable RANDOM resolution support for such > * panels by default */ > - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), > + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), > intel_dsi->video_frmt_cfg_bits | > intel_dsi->video_mode_format | > IP_TG_CONFIG | > @@ -748,6 +748,12 @@ void intel_dsi_init(struct drm_device *dev) > intel_connector->get_hw_state = intel_connector_get_hw_state; > intel_connector->unregister = intel_connector_unregister; > > + /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ > + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) > + intel_encoder->crtc_mask = (1 << PIPE_A); > + else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) > + intel_encoder->crtc_mask = (1 << PIPE_B); > + > for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { > dsi = &intel_dsi_devices[i]; > intel_dsi->dev = *dsi; > @@ -762,8 +768,6 @@ void intel_dsi_init(struct drm_device *dev) > } > > intel_encoder->type = INTEL_OUTPUT_DSI; > - intel_encoder->crtc_mask = (1 << 0); /* XXX */ > - > intel_encoder->cloneable = 0; > drm_connector_init(dev, connector, &intel_dsi_connector_funcs, > DRM_MODE_CONNECTOR_DSI); > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h > index 657eb5c1b9d8..97a6f621774f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -127,6 +127,22 @@ struct intel_dsi { > u16 panel_pwr_cycle_delay; > }; > > +/* XXX: Transitional before dual port configuration */ > +static inline enum port intel_dsi_pipe_to_port(enum pipe pipe) > +{ > + if (pipe == PIPE_A) > + return PORT_A; > + else if (pipe == PIPE_B) > + return PORT_C; > + > + WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe)); > + return PORT_C; > +} > + > +#define for_each_dsi_port(__port, __ports_mask) \ > + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > + if ((__ports_mask) & (1 << (__port))) > + > static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) > { > return container_of(encoder, struct intel_dsi, base.base); > diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c > index f4767fd2ebeb..004fa918ca03 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c > +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c > @@ -54,15 +54,15 @@ static void print_stat(struct intel_dsi *intel_dsi) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > - val = I915_READ(MIPI_INTR_STAT(pipe)); > + val = I915_READ(MIPI_INTR_STAT(port)); > > #define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : "" > - DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x" > + DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x" > "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" > - "\n", pipe, val, > + "\n", port_name(port), val, > STAT_BIT(val, TEARING_EFFECT), > STAT_BIT(val, SPL_PKT_SENT_INTERRUPT), > STAT_BIT(val, GEN_READ_DATA_AVAIL), > @@ -110,16 +110,16 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > u32 mask = DBI_FIFO_EMPTY; > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for DBI FIFO empty\n"); > > - temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe)); > + temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(port)); > temp &= DBI_HS_LP_MODE_MASK; > - I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE); > + I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), enable ? DBI_HS_MODE : DBI_LP_MODE); > > intel_dsi->hs = enable; > } > @@ -131,7 +131,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 ctrl_reg; > u32 ctrl; > u32 mask; > @@ -140,14 +140,14 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, > channel, data_type, data); > > if (intel_dsi->hs) { > - ctrl_reg = MIPI_HS_GEN_CTRL(pipe); > + ctrl_reg = MIPI_HS_GEN_CTRL(port); > mask = HS_CTRL_FIFO_FULL; > } else { > - ctrl_reg = MIPI_LP_GEN_CTRL(pipe); > + ctrl_reg = MIPI_LP_GEN_CTRL(port); > mask = LP_CTRL_FIFO_FULL; > } > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) { > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) { > DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); > print_stat(intel_dsi); > } > @@ -173,7 +173,7 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 data_reg; > int i, j, n; > u32 mask; > @@ -182,14 +182,14 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, > channel, data_type, len); > > if (intel_dsi->hs) { > - data_reg = MIPI_HS_GEN_DATA(pipe); > + data_reg = MIPI_HS_GEN_DATA(port); > mask = HS_DATA_FIFO_FULL; > } else { > - data_reg = MIPI_LP_GEN_DATA(pipe); > + data_reg = MIPI_LP_GEN_DATA(port); > mask = LP_DATA_FIFO_FULL; > } > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) > DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); > > for (i = 0; i < len; i += n) { > @@ -292,14 +292,14 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > int i, len = 0; > u32 data_reg, val; > > if (intel_dsi->hs) { > - data_reg = MIPI_HS_GEN_DATA(pipe); > + data_reg = MIPI_HS_GEN_DATA(port); > } else { > - data_reg = MIPI_LP_GEN_DATA(pipe); > + data_reg = MIPI_LP_GEN_DATA(port); > } > > while (len < buflen) { > @@ -318,7 +318,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > int ret; > > @@ -327,14 +327,14 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, > * longer than MIPI_MAX_RETURN_PKT_SIZE > */ > > - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); > + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); > > ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd); > if (ret) > return ret; > > mask = GEN_READ_DATA_AVAIL; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for read data.\n"); > > ret = dsi_read_data_return(intel_dsi, buf, buflen); > @@ -354,7 +354,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > int ret; > > @@ -363,7 +363,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > * longer than MIPI_MAX_RETURN_PKT_SIZE > */ > > - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); > + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); > > ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata, > reqlen); > @@ -371,7 +371,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > return ret; > > mask = GEN_READ_DATA_AVAIL; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for read data.\n"); > > ret = dsi_read_data_return(intel_dsi, buf, buflen); > @@ -395,7 +395,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > > /* XXX: pipe, hs */ > @@ -405,16 +405,16 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) > cmd |= DPI_LP_MODE; > > /* clear bit */ > - I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT); > + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); > > /* XXX: old code skips write if control unchanged */ > - if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe))) > + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) > DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); > > - I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd); > + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); > > mask = SPL_PKT_SENT_INTERRUPT; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) > DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); > > return 0; > @@ -426,12 +426,12 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > > mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) > DRM_ERROR("DPI FIFOs are not empty\n"); > } This patch has some style issues. Please address them. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 2014-11-26 17:20 ` Singh, Gaurav K @ 2014-11-26 18:08 ` Daniel Vetter 2014-11-26 18:43 ` Singh, Gaurav K 0 siblings, 1 reply; 28+ messages in thread From: Daniel Vetter @ 2014-11-26 18:08 UTC (permalink / raw) To: Singh, Gaurav K; +Cc: Jani Nikula, intel-gfx On Wed, Nov 26, 2014 at 10:50:46PM +0530, Singh, Gaurav K wrote: > This patch has some style issues. Please address them. Please be more specific, that's rather non-actionable review. Also general rule of thumb is that if it doesn't look offensive and the patch is otherwise good it still deserves an r-b. I can easily fix up small things while applying (and do that all the time). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 2014-11-26 18:08 ` Daniel Vetter @ 2014-11-26 18:43 ` Singh, Gaurav K 0 siblings, 0 replies; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-26 18:43 UTC (permalink / raw) To: Daniel Vetter; +Cc: Jani Nikula, intel-gfx On 11/26/2014 11:38 PM, Daniel Vetter wrote: > On Wed, Nov 26, 2014 at 10:50:46PM +0530, Singh, Gaurav K wrote: >> This patch has some style issues. Please address them. > Please be more specific, that's rather non-actionable review. > > Also general rule of thumb is that if it doesn't look offensive and the > patch is otherwise good it still deserves an r-b. I can easily fix up > small things while applying (and do that all the time). > -Daniel checkpatch.pl is throwing few warnings and one error which are mainly because of lines more than 80 characters. The patch is otherwise looking good. I will add Reviewed-by field in the patch. with regards, Gaurav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula 2014-11-26 17:20 ` Singh, Gaurav K @ 2014-11-27 7:28 ` Singh, Gaurav K 1 sibling, 0 replies; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-27 7:28 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar On 11/14/2014 8:24 PM, Jani Nikula wrote: > MIPI DSI works on ports A and C, which map to pipes A and B, > respectively. Things are going to get more complicated with the > introduction of dual link DSI support, so clean up the register defines > and code to match reality. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dsi.c | 148 ++++++++--------- > drivers/gpu/drm/i915/intel_dsi.h | 16 ++ > drivers/gpu/drm/i915/intel_dsi_cmd.c | 64 ++++---- > 4 files changed, 277 insertions(+), 254 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a143127eb451..250043f3f22e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -31,6 +31,8 @@ > #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) > #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ > (pipe) == PIPE_B ? (b) : (c)) > +#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ > + (port) == PORT_B ? (b) : (c)) > > #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) > #define _MASKED_BIT_DISABLE(a) ((a) << 16) > @@ -1492,7 +1494,7 @@ enum punit_power_well { > #define I915_ISP_INTERRUPT (1<<22) > #define I915_LPE_PIPE_B_INTERRUPT (1<<21) > #define I915_LPE_PIPE_A_INTERRUPT (1<<20) > -#define I915_MIPIB_INTERRUPT (1<<19) > +#define I915_MIPIC_INTERRUPT (1<<19) > #define I915_MIPIA_INTERRUPT (1<<18) > #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) > #define I915_DISPLAY_PORT_INTERRUPT (1<<17) > @@ -6612,29 +6614,30 @@ enum punit_power_well { > #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) > #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) > > -/* VLV MIPI registers */ > +/* MIPI DSI registers */ > + > +#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ > > #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) > -#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > -#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ > - _MIPIB_PORT_CTRL) > -#define DPI_ENABLE (1 << 31) /* A + B */ > +#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) > +#define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) > +#define DPI_ENABLE (1 << 31) /* A + C */ > #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 > #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) > #define DUAL_LINK_MODE_MASK (1 << 26) > #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) > #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) > -#define DITHERING_ENABLE (1 << 25) /* A + B */ > +#define DITHERING_ENABLE (1 << 25) /* A + C */ > #define FLOPPED_HSTX (1 << 23) > #define DE_INVERT (1 << 19) /* XXX */ > #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 > #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) > #define AFE_LATCHOUT (1 << 17) > #define LP_OUTPUT_HOLD (1 << 16) > -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 > -#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) > -#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 > -#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) > +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 > +#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) > +#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 > +#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) > #define CSB_SHIFT 9 > #define CSB_MASK (3 << 9) > #define CSB_20MHZ (0 << 9) > @@ -6643,10 +6646,10 @@ enum punit_power_well { > #define BANDGAP_MASK (1 << 8) > #define BANDGAP_PNW_CIRCUIT (0 << 8) > #define BANDGAP_LNC_CIRCUIT (1 << 8) > -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 > -#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) > -#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ > -#define TEARING_EFFECT_SHIFT 2 /* A + B */ > +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 > +#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) > +#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ > +#define TEARING_EFFECT_SHIFT 2 /* A + C */ > #define TEARING_EFFECT_MASK (3 << 2) > #define TEARING_EFFECT_OFF (0 << 2) > #define TEARING_EFFECT_DSI (1 << 2) > @@ -6658,9 +6661,9 @@ enum punit_power_well { > #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) > > #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) > -#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > -#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ > - _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) > +#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) > +#define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ > + _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) > #define TEARING_EFFECT_DELAY_SHIFT 0 > #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) > > @@ -6670,9 +6673,9 @@ enum punit_power_well { > /* MIPI DSI Controller and D-PHY registers */ > > #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) > -#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) > -#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ > - _MIPIB_DEVICE_READY) > +#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) > +#define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ > + _MIPIC_DEVICE_READY) > #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ > #define ULPS_STATE_MASK (3 << 1) > #define ULPS_STATE_ENTER (2 << 1) > @@ -6681,13 +6684,13 @@ enum punit_power_well { > #define DEVICE_READY (1 << 0) > > #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) > -#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) > -#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ > - _MIPIB_INTR_STAT) > +#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) > +#define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ > + _MIPIC_INTR_STAT) > #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) > -#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) > -#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ > - _MIPIB_INTR_EN) > +#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) > +#define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ > + _MIPIC_INTR_EN) > #define TEARING_EFFECT (1 << 31) > #define SPL_PKT_SENT_INTERRUPT (1 << 30) > #define GEN_READ_DATA_AVAIL (1 << 29) > @@ -6722,9 +6725,9 @@ enum punit_power_well { > #define RXSOT_ERROR (1 << 0) > > #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) > -#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) > -#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ > - _MIPIB_DSI_FUNC_PRG) > +#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) > +#define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ > + _MIPIC_DSI_FUNC_PRG) > #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) > #define CMD_MODE_NOT_SUPPORTED (0 << 13) > #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) > @@ -6746,93 +6749,93 @@ enum punit_power_well { > #define DATA_LANES_PRG_REG_MASK (7 << 0) > > #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) > -#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) > -#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ > - _MIPIB_HS_TX_TIMEOUT) > +#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) > +#define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ > + _MIPIC_HS_TX_TIMEOUT) > #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff > > #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) > -#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) > -#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ > - _MIPIB_LP_RX_TIMEOUT) > +#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) > +#define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ > + _MIPIC_LP_RX_TIMEOUT) > #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff > > #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) > -#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) > -#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ > - _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) > +#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) > +#define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ > + _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) > #define TURN_AROUND_TIMEOUT_MASK 0x3f > > #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) > -#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) > -#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ > - _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) > +#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) > +#define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ > + _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) > #define DEVICE_RESET_TIMER_MASK 0xffff > > #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) > -#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) > -#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ > - _MIPIB_DPI_RESOLUTION) > +#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) > +#define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ > + _MIPIC_DPI_RESOLUTION) > #define VERTICAL_ADDRESS_SHIFT 16 > #define VERTICAL_ADDRESS_MASK (0xffff << 16) > #define HORIZONTAL_ADDRESS_SHIFT 0 > #define HORIZONTAL_ADDRESS_MASK 0xffff > > #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) > -#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) > -#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ > - _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) > +#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) > +#define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ > + _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) > #define DBI_FIFO_EMPTY_HALF (0 << 0) > #define DBI_FIFO_EMPTY_QUARTER (1 << 0) > #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) > > /* regs below are bits 15:0 */ > #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) > -#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) > -#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) > +#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) > +#define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) > > #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) > -#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) > -#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ > - _MIPIB_HBP_COUNT) > +#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) > +#define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ > + _MIPIC_HBP_COUNT) > > #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) > -#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) > -#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ > - _MIPIB_HFP_COUNT) > +#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) > +#define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ > + _MIPIC_HFP_COUNT) > > #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) > -#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) > -#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) > +#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) > +#define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) > > #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) > -#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) > -#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) > +#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) > +#define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) > > #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) > -#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) > -#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ > - _MIPIB_VBP_COUNT) > +#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) > +#define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ > + _MIPIC_VBP_COUNT) > > #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) > -#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) > -#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ > - _MIPIB_VFP_COUNT) > +#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) > +#define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ > + _MIPIC_VFP_COUNT) > > #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) > -#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) > -#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ > - _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) > +#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) > +#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ > + _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) > > /* regs above are bits 15:0 */ > > #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) > -#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) > -#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ > - _MIPIB_DPI_CONTROL) > +#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) > +#define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ > + _MIPIC_DPI_CONTROL) > #define DPI_LP_MODE (1 << 6) > #define BACKLIGHT_OFF (1 << 5) > #define BACKLIGHT_ON (1 << 4) > @@ -6842,30 +6845,30 @@ enum punit_power_well { > #define SHUTDOWN (1 << 0) > > #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) > -#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) > -#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ > - _MIPIB_DPI_DATA) > +#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) > +#define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ > + _MIPIC_DPI_DATA) > #define COMMAND_BYTE_SHIFT 0 > #define COMMAND_BYTE_MASK (0x3f << 0) > > #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) > -#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) > -#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ > - _MIPIB_INIT_COUNT) > +#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) > +#define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ > + _MIPIC_INIT_COUNT) > #define MASTER_INIT_TIMER_SHIFT 0 > #define MASTER_INIT_TIMER_MASK (0xffff << 0) > > #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) > -#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) > -#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ > - _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) > +#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) > +#define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ > + _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) > #define MAX_RETURN_PKT_SIZE_SHIFT 0 > #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) > > #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) > -#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) > -#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ > - _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) > +#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) > +#define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ > + _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) > #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) > #define DISABLE_VIDEO_BTA (1 << 3) > #define IP_TG_CONFIG (1 << 2) > @@ -6874,9 +6877,9 @@ enum punit_power_well { > #define VIDEO_MODE_BURST (3 << 0) > > #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) > -#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) > -#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ > - _MIPIB_EOT_DISABLE) > +#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) > +#define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ > + _MIPIC_EOT_DISABLE) > #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) > #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) > #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) > @@ -6887,32 +6890,32 @@ enum punit_power_well { > #define EOT_DISABLE (1 << 0) > > #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) > -#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) > -#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ > - _MIPIB_LP_BYTECLK) > +#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) > +#define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ > + _MIPIC_LP_BYTECLK) > #define LP_BYTECLK_SHIFT 0 > #define LP_BYTECLK_MASK (0xffff << 0) > > /* bits 31:0 */ > #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) > -#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) > -#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ > - _MIPIB_LP_GEN_DATA) > +#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) > +#define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ > + _MIPIC_LP_GEN_DATA) > > /* bits 31:0 */ > #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) > -#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) > -#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ > - _MIPIB_HS_GEN_DATA) > +#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) > +#define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ > + _MIPIC_HS_GEN_DATA) > > #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) > -#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) > -#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ > - _MIPIB_LP_GEN_CTRL) > +#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) > +#define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ > + _MIPIC_LP_GEN_CTRL) > #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) > -#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) > -#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ > - _MIPIB_HS_GEN_CTRL) > +#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) > +#define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ > + _MIPIC_HS_GEN_CTRL) > #define LONG_PACKET_WORD_COUNT_SHIFT 8 > #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) > #define SHORT_PACKET_PARAM_SHIFT 8 > @@ -6924,9 +6927,9 @@ enum punit_power_well { > /* data type values, see include/video/mipi_display.h */ > > #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) > -#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) > -#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ > - _MIPIB_GEN_FIFO_STAT) > +#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) > +#define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ > + _MIPIC_GEN_FIFO_STAT) > #define DPI_FIFO_EMPTY (1 << 28) > #define DBI_FIFO_EMPTY (1 << 27) > #define LP_CTRL_FIFO_EMPTY (1 << 26) > @@ -6943,17 +6946,17 @@ enum punit_power_well { > #define HS_DATA_FIFO_FULL (1 << 0) > > #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) > -#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) > -#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ > - _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) > +#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) > +#define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ > + _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) > #define DBI_HS_LP_MODE_MASK (1 << 0) > #define DBI_LP_MODE (1 << 0) > #define DBI_HS_MODE (0 << 0) > > #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) > -#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) > -#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ > - _MIPIB_DPHY_PARAM) > +#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) > +#define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ > + _MIPIC_DPHY_PARAM) > #define EXIT_ZERO_COUNT_SHIFT 24 > #define EXIT_ZERO_COUNT_MASK (0x3f << 24) > #define TRAIL_COUNT_SHIFT 16 > @@ -6965,36 +6968,36 @@ enum punit_power_well { > > /* bits 31:0 */ > #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) > -#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) > -#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ > - _MIPIB_DBI_BW_CTRL) > +#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) > +#define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ > + _MIPIC_DBI_BW_CTRL) > > #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > + 0xb088) > -#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > +#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ > + 0xb888) > -#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ > - _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) > +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ > + _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) > #define LP_HS_SSW_CNT_SHIFT 16 > #define LP_HS_SSW_CNT_MASK (0xffff << 16) > #define HS_LP_PWR_SW_CNT_SHIFT 0 > #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) > > #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) > -#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) > -#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ > - _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) > +#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) > +#define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ > + _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) > #define STOP_STATE_STALL_COUNTER_SHIFT 0 > #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) > > #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) > -#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) > -#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ > - _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) > +#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) > +#define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ > + _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) > #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) > -#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) > -#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ > - _MIPIB_INTR_EN_REG_1) > +#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) > +#define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ > + _MIPIC_INTR_EN_REG_1) > #define RX_CONTENTION_DETECTED (1 << 0) > > /* XXX: only pipe A ?!? */ > @@ -7013,9 +7016,9 @@ enum punit_power_well { > /* MIPI adapter registers */ > > #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) > -#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) > -#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ > - _MIPIB_CTRL) > +#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) > +#define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ > + _MIPIC_CTRL) > #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ > #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) > #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) > @@ -7028,24 +7031,24 @@ enum punit_power_well { > #define RGB_FLIP_TO_BGR (1 << 2) > > #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) > -#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) > -#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ > - _MIPIB_DATA_ADDRESS) > +#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) > +#define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ > + _MIPIC_DATA_ADDRESS) > #define DATA_MEM_ADDRESS_SHIFT 5 > #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define DATA_VALID (1 << 0) > > #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) > -#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) > -#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ > - _MIPIB_DATA_LENGTH) > +#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) > +#define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ > + _MIPIC_DATA_LENGTH) > #define DATA_LENGTH_SHIFT 0 > #define DATA_LENGTH_MASK (0xfffff << 0) > > #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) > -#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) > -#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ > - _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) > +#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) > +#define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ > + _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) > #define COMMAND_MEM_ADDRESS_SHIFT 5 > #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) > #define AUTO_PWG_ENABLE (1 << 2) > @@ -7053,22 +7056,22 @@ enum punit_power_well { > #define COMMAND_VALID (1 << 0) > > #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) > -#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) > -#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ > - _MIPIB_COMMAND_LENGTH) > +#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) > +#define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ > + _MIPIC_COMMAND_LENGTH) > #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ > #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) > > #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) > -#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) > -#define MIPI_READ_DATA_RETURN(tc, n) \ > - (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ > +#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) > +#define MIPI_READ_DATA_RETURN(port, n) \ > + (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ > + 4 * (n)) /* n: 0...7 */ > > #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) > -#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) > -#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ > - _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) > +#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) > +#define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ > + _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) > #define READ_DATA_VALID(n) (1 << (n)) > > /* For UMS only (deprecated): */ > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 0b184079de14..35842a6687d8 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -106,7 +106,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > DRM_DEBUG_KMS("\n"); > @@ -120,17 +120,17 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > /* bandgap reset is needed after everytime we do power gate */ > band_gap_reset(dev_priv); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); > usleep_range(2500, 3000); > > - val = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); > + val = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); > + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); > usleep_range(2500, 3000); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); > usleep_range(2500, 3000); > } > > @@ -140,13 +140,13 @@ static void intel_dsi_enable(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > > DRM_DEBUG_KMS("\n"); > > if (is_cmd_mode(intel_dsi)) > - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); > + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); > else { > msleep(20); /* XXX */ > dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); > @@ -158,10 +158,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder) > wait_for_dsi_fifo_empty(intel_dsi); > > /* assert ip_tg_enable signal */ > - temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; > + temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK; > temp = temp | intel_dsi->port_bits; > - I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); > - POSTING_READ(MIPI_PORT_CTRL(pipe)); > + I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); > + POSTING_READ(MIPI_PORT_CTRL(port)); > } > } > > @@ -237,7 +237,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > > DRM_DEBUG_KMS("\n"); > @@ -246,29 +246,29 @@ static void intel_dsi_disable(struct intel_encoder *encoder) > wait_for_dsi_fifo_empty(intel_dsi); > > /* de-assert ip_tg_enable signal */ > - temp = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); > - POSTING_READ(MIPI_PORT_CTRL(pipe)); > + temp = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); > + POSTING_READ(MIPI_PORT_CTRL(port)); > > msleep(2); > } > > /* Panel commands can be sent when clock is in LP11 */ > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x0); > > - temp = I915_READ(MIPI_CTRL(pipe)); > + temp = I915_READ(MIPI_CTRL(port)); > temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - I915_WRITE(MIPI_CTRL(pipe), temp | > + I915_WRITE(MIPI_CTRL(port), temp | > intel_dsi->escape_clk_div << > ESCAPE_CLOCK_DIVIDER_SHIFT); > > - I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); > + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); > > - temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); > + temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); > temp &= ~VID_MODE_FORMAT_MASK; > - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); > + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x1); > > /* if disable packets are sent before sending shutdown packet then in > * some next enable sequence send turn on packet error is observed */ > @@ -282,29 +282,29 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > DRM_DEBUG_KMS("\n"); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT); > usleep_range(2000, 2500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); > + I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER); > usleep_range(2000, 2500); > > - if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) > + if (wait_for(((I915_READ(MIPI_PORT_CTRL(port)) & AFE_LATCHOUT) > == 0x00000), 30)) > DRM_ERROR("DSI LP not going Low\n"); > > - val = I915_READ(MIPI_PORT_CTRL(pipe)); > - I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); > + val = I915_READ(MIPI_PORT_CTRL(port)); > + I915_WRITE(MIPI_PORT_CTRL(port), val & ~LP_OUTPUT_HOLD); > usleep_range(1000, 1500); > > - I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); > + I915_WRITE(MIPI_DEVICE_READY(port), 0x00); > usleep_range(2000, 2500); > > vlv_disable_dsi_pll(encoder); > @@ -338,8 +338,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > enum intel_display_power_domain power_domain; > - u32 port, func; > - enum pipe p; > + u32 port_ctl, func; > + enum port port; > > DRM_DEBUG_KMS("\n"); > > @@ -348,13 +348,13 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > return false; > > /* XXX: this only works for one DSI output */ > - for (p = PIPE_A; p <= PIPE_B; p++) { > - port = I915_READ(MIPI_PORT_CTRL(p)); > - func = I915_READ(MIPI_DSI_FUNC_PRG(p)); > + for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) { > + port_ctl = I915_READ(MIPI_PORT_CTRL(port)); > + func = I915_READ(MIPI_DSI_FUNC_PRG(port)); > > - if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { > - if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { > - *pipe = p; > + if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { > + if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { > + *pipe = port == PORT_A ? PIPE_A : PIPE_C; > return true; > } > } > @@ -437,7 +437,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > unsigned int bpp = intel_crtc->config.pipe_bpp; > unsigned int lane_count = intel_dsi->lane_count; > > @@ -460,18 +460,18 @@ static void set_dsi_timings(struct drm_encoder *encoder, > intel_dsi->burst_mode_ratio); > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); > > - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); > - I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); > + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); > + I915_WRITE(MIPI_HFP_COUNT(port), hfp); > > /* meaningful for video mode non-burst sync pulse mode only, can be zero > * for non-burst sync events and burst modes */ > - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); > - I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); > + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); > + I915_WRITE(MIPI_HBP_COUNT(port), hbp); > > /* vertical values are in terms of lines */ > - I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); > - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); > - I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); > + I915_WRITE(MIPI_VFP_COUNT(port), vfp); > + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); > + I915_WRITE(MIPI_VBP_COUNT(port), vbp); > } > > static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > @@ -483,30 +483,30 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > struct drm_display_mode *adjusted_mode = > &intel_crtc->config.adjusted_mode; > - int pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > unsigned int bpp = intel_crtc->config.pipe_bpp; > u32 val, tmp; > > - DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); > + DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); > > /* escape clock divider, 20MHz, shared for A and C. device ready must be > * off when doing this! txclkesc? */ > - tmp = I915_READ(MIPI_CTRL(0)); > + tmp = I915_READ(MIPI_CTRL(PORT_A)); > tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; > - I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); > + I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); > > /* read request priority is per pipe */ > - tmp = I915_READ(MIPI_CTRL(pipe)); > + tmp = I915_READ(MIPI_CTRL(port)); > tmp &= ~READ_REQUEST_PRIORITY_MASK; > - I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); > + I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); > > /* XXX: why here, why like this? handling in irq handler?! */ > - I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); > - I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); > + I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); > + I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); > > - I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); > + I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); > > - I915_WRITE(MIPI_DPI_RESOLUTION(pipe), > + I915_WRITE(MIPI_DPI_RESOLUTION(port), > adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | > adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); > > @@ -522,7 +522,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > /* XXX: cross-check bpp vs. pixel format? */ > val |= intel_dsi->pixel_format; > } > - I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); > + I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); > > /* timeouts for recovery. one frame IIUC. if counter expires, EOT and > * stop state. */ > @@ -543,25 +543,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > > if (is_vid_mode(intel_dsi) && > intel_dsi->video_mode_format == VIDEO_MODE_BURST) { > - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), > + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), > txbyteclkhs(adjusted_mode->htotal, bpp, > intel_dsi->lane_count, > intel_dsi->burst_mode_ratio) + 1); > } else { > - I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), > + I915_WRITE(MIPI_HS_TX_TIMEOUT(port), > txbyteclkhs(adjusted_mode->vtotal * > adjusted_mode->htotal, > bpp, intel_dsi->lane_count, > intel_dsi->burst_mode_ratio) + 1); > } > - I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); > - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); > - I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); > + I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); > + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val); > + I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val); > > /* dphy stuff */ > > /* in terms of low power clock */ > - I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); > + I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); > > val = 0; > if (intel_dsi->eotp_pkt == 0) > @@ -571,17 +571,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > val |= CLOCKSTOP; > > /* recovery disables */ > - I915_WRITE(MIPI_EOT_DISABLE(pipe), val); > + I915_WRITE(MIPI_EOT_DISABLE(port), val); > > /* in terms of low power clock */ > - I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); > + I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); > > /* in terms of txbyteclkhs. actual high to low switch + > * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. > * > * XXX: write MIPI_STOP_STATE_STALL? > */ > - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), > + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), > intel_dsi->hs_to_lp_count); > > /* XXX: low power clock equivalence in terms of byte clock. the number > @@ -589,16 +589,16 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > * and txclkesc. txclkesc time / txbyteclk time * (105 + > * MIPI_STOP_STATE_STALL) / 105.??? > */ > - I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); > + I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); > > /* the bw essential for transmitting 16 long packets containing 252 > * bytes meant for dcs write memory command is programmed in this > * register in terms of byte clocks. based on dsi transfer rate and the > * number of lanes configured the time taken to transmit 16 long packets > * in a dsi stream varies. */ > - I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); > + I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); > > - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), > + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), > intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | > intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); > > @@ -606,7 +606,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > /* Some panels might have resolution which is not a multiple of > * 64 like 1366 x 768. Enable RANDOM resolution support for such > * panels by default */ > - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), > + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), > intel_dsi->video_frmt_cfg_bits | > intel_dsi->video_mode_format | > IP_TG_CONFIG | > @@ -748,6 +748,12 @@ void intel_dsi_init(struct drm_device *dev) > intel_connector->get_hw_state = intel_connector_get_hw_state; > intel_connector->unregister = intel_connector_unregister; > > + /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ > + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) > + intel_encoder->crtc_mask = (1 << PIPE_A); > + else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) > + intel_encoder->crtc_mask = (1 << PIPE_B); > + > for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { > dsi = &intel_dsi_devices[i]; > intel_dsi->dev = *dsi; > @@ -762,8 +768,6 @@ void intel_dsi_init(struct drm_device *dev) > } > > intel_encoder->type = INTEL_OUTPUT_DSI; > - intel_encoder->crtc_mask = (1 << 0); /* XXX */ > - > intel_encoder->cloneable = 0; > drm_connector_init(dev, connector, &intel_dsi_connector_funcs, > DRM_MODE_CONNECTOR_DSI); > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h > index 657eb5c1b9d8..97a6f621774f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -127,6 +127,22 @@ struct intel_dsi { > u16 panel_pwr_cycle_delay; > }; > > +/* XXX: Transitional before dual port configuration */ > +static inline enum port intel_dsi_pipe_to_port(enum pipe pipe) > +{ > + if (pipe == PIPE_A) > + return PORT_A; > + else if (pipe == PIPE_B) > + return PORT_C; > + > + WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe)); > + return PORT_C; > +} > + > +#define for_each_dsi_port(__port, __ports_mask) \ > + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > + if ((__ports_mask) & (1 << (__port))) > + > static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) > { > return container_of(encoder, struct intel_dsi, base.base); > diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c > index f4767fd2ebeb..004fa918ca03 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c > +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c > @@ -54,15 +54,15 @@ static void print_stat(struct intel_dsi *intel_dsi) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 val; > > - val = I915_READ(MIPI_INTR_STAT(pipe)); > + val = I915_READ(MIPI_INTR_STAT(port)); > > #define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : "" > - DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x" > + DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x" > "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" > - "\n", pipe, val, > + "\n", port_name(port), val, > STAT_BIT(val, TEARING_EFFECT), > STAT_BIT(val, SPL_PKT_SENT_INTERRUPT), > STAT_BIT(val, GEN_READ_DATA_AVAIL), > @@ -110,16 +110,16 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 temp; > u32 mask = DBI_FIFO_EMPTY; > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for DBI FIFO empty\n"); > > - temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe)); > + temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(port)); > temp &= DBI_HS_LP_MODE_MASK; > - I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE); > + I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), enable ? DBI_HS_MODE : DBI_LP_MODE); > > intel_dsi->hs = enable; > } > @@ -131,7 +131,7 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 ctrl_reg; > u32 ctrl; > u32 mask; > @@ -140,14 +140,14 @@ static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel, > channel, data_type, data); > > if (intel_dsi->hs) { > - ctrl_reg = MIPI_HS_GEN_CTRL(pipe); > + ctrl_reg = MIPI_HS_GEN_CTRL(port); > mask = HS_CTRL_FIFO_FULL; > } else { > - ctrl_reg = MIPI_LP_GEN_CTRL(pipe); > + ctrl_reg = MIPI_LP_GEN_CTRL(port); > mask = LP_CTRL_FIFO_FULL; > } > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) { > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) { > DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); > print_stat(intel_dsi); > } > @@ -173,7 +173,7 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 data_reg; > int i, j, n; > u32 mask; > @@ -182,14 +182,14 @@ static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel, > channel, data_type, len); > > if (intel_dsi->hs) { > - data_reg = MIPI_HS_GEN_DATA(pipe); > + data_reg = MIPI_HS_GEN_DATA(port); > mask = HS_DATA_FIFO_FULL; > } else { > - data_reg = MIPI_LP_GEN_DATA(pipe); > + data_reg = MIPI_LP_GEN_DATA(port); > mask = LP_DATA_FIFO_FULL; > } > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) > DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); > > for (i = 0; i < len; i += n) { > @@ -292,14 +292,14 @@ static int dsi_read_data_return(struct intel_dsi *intel_dsi, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > int i, len = 0; > u32 data_reg, val; > > if (intel_dsi->hs) { > - data_reg = MIPI_HS_GEN_DATA(pipe); > + data_reg = MIPI_HS_GEN_DATA(port); > } else { > - data_reg = MIPI_LP_GEN_DATA(pipe); > + data_reg = MIPI_LP_GEN_DATA(port); > } > > while (len < buflen) { > @@ -318,7 +318,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > int ret; > > @@ -327,14 +327,14 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, > * longer than MIPI_MAX_RETURN_PKT_SIZE > */ > > - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); > + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); > > ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd); > if (ret) > return ret; > > mask = GEN_READ_DATA_AVAIL; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for read data.\n"); > > ret = dsi_read_data_return(intel_dsi, buf, buflen); > @@ -354,7 +354,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > int ret; > > @@ -363,7 +363,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > * longer than MIPI_MAX_RETURN_PKT_SIZE > */ > > - I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL); > + I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); > > ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata, > reqlen); > @@ -371,7 +371,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, > return ret; > > mask = GEN_READ_DATA_AVAIL; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50)) > DRM_ERROR("Timeout waiting for read data.\n"); > > ret = dsi_read_data_return(intel_dsi, buf, buflen); > @@ -395,7 +395,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > > /* XXX: pipe, hs */ > @@ -405,16 +405,16 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) > cmd |= DPI_LP_MODE; > > /* clear bit */ > - I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT); > + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); > > /* XXX: old code skips write if control unchanged */ > - if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe))) > + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) > DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); > > - I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd); > + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); > > mask = SPL_PKT_SENT_INTERRUPT; > - if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100)) > + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) > DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); > > return 0; > @@ -426,12 +426,12 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi) > struct drm_device *dev = encoder->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > - enum pipe pipe = intel_crtc->pipe; > + enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); > u32 mask; > > mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | > LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; > > - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) > + if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) > DRM_ERROR("DPI FIFOs are not empty\n"); > } checkpatch.pl is throwing few warnings and one error which are mainly because of lines more than 80 characters. The patch is otherwise looking good. with regards, Gaurav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula @ 2014-11-14 14:54 ` Jani Nikula 2014-11-27 7:24 ` Singh, Gaurav K 2014-11-14 14:54 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual link for each port Jani Nikula 2014-11-24 8:10 ` [PATCH 0/3] BYT DSI Dual Link Support Singh, Gaurav K 3 siblings, 1 reply; 28+ messages in thread From: Jani Nikula @ 2014-11-14 14:54 UTC (permalink / raw) To: intel-gfx, shobhit.kumar, gaurav.k.singh; +Cc: jani.nikula Later on this can include multiple ports (e.g. (1 << PORT_A) | (1 << PORT_C)) to describe dual link DSI. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 7 +++++-- drivers/gpu/drm/i915/intel_dsi.h | 3 +++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 35842a6687d8..259cb4ab2067 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -749,10 +749,13 @@ void intel_dsi_init(struct drm_device *dev) intel_connector->unregister = intel_connector_unregister; /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ - if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { intel_encoder->crtc_mask = (1 << PIPE_A); - else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) + intel_dsi->ports = (1 << PORT_A); + } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { intel_encoder->crtc_mask = (1 << PIPE_B); + intel_dsi->ports = (1 << PORT_C); + } for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { dsi = &intel_dsi_devices[i]; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 97a6f621774f..7f5d0280b9d7 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -78,6 +78,9 @@ struct intel_dsi { struct intel_connector *attached_connector; + /* bit mask of ports being driven */ + u16 ports; + /* if true, use HS mode, otherwise LP */ bool hs; -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven 2014-11-14 14:54 ` [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven Jani Nikula @ 2014-11-27 7:24 ` Singh, Gaurav K 0 siblings, 0 replies; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-27 7:24 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar On 11/14/2014 8:24 PM, Jani Nikula wrote: > Later on this can include multiple ports (e.g. (1 << PORT_A) | (1 << > PORT_C)) to describe dual link DSI. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 7 +++++-- > drivers/gpu/drm/i915/intel_dsi.h | 3 +++ > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 35842a6687d8..259cb4ab2067 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -749,10 +749,13 @@ void intel_dsi_init(struct drm_device *dev) > intel_connector->unregister = intel_connector_unregister; > > /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ > - if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) > + if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { > intel_encoder->crtc_mask = (1 << PIPE_A); > - else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) > + intel_dsi->ports = (1 << PORT_A); > + } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { > intel_encoder->crtc_mask = (1 << PIPE_B); > + intel_dsi->ports = (1 << PORT_C); > + } > > for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { > dsi = &intel_dsi_devices[i]; > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h > index 97a6f621774f..7f5d0280b9d7 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -78,6 +78,9 @@ struct intel_dsi { > > struct intel_connector *attached_connector; > > + /* bit mask of ports being driven */ > + u16 ports; > + > /* if true, use HS mode, otherwise LP */ > bool hs; > This patch looks good. With regards, Gaurav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/3] drm/i915/dsi: an example how to handle dual link for each port 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula 2014-11-14 14:54 ` [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven Jani Nikula @ 2014-11-14 14:54 ` Jani Nikula 2014-11-15 1:15 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual shuang.he 2014-11-24 8:10 ` [PATCH 0/3] BYT DSI Dual Link Support Singh, Gaurav K 3 siblings, 1 reply; 28+ messages in thread From: Jani Nikula @ 2014-11-14 14:54 UTC (permalink / raw) To: intel-gfx, shobhit.kumar, gaurav.k.singh; +Cc: jani.nikula The same paradigm can be used all around. Certain places will need to special case "if (port == PORT_A)" in the loop, some other places will need to have some other special cases. However the idea should be future compatible. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_dsi_cmd.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c index 004fa918ca03..4fda8e3ded58 100644 --- a/drivers/gpu/drm/i915/intel_dsi_cmd.c +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c @@ -395,7 +395,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); - enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); + enum port port; u32 mask; /* XXX: pipe, hs */ @@ -404,18 +404,20 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs) else cmd |= DPI_LP_MODE; - /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); + for_each_dsi_port(port, intel_dsi->ports) { + /* clear bit */ + I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); - /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) - DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); + /* XXX: old code skips write if control unchanged */ + if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) + DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); - I915_WRITE(MIPI_DPI_CONTROL(port), cmd); + I915_WRITE(MIPI_DPI_CONTROL(port), cmd); - mask = SPL_PKT_SENT_INTERRUPT; - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) - DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); + mask = SPL_PKT_SENT_INTERRUPT; + if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) + DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); + } return 0; } -- 2.1.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 3/3] drm/i915/dsi: an example how to handle dual 2014-11-14 14:54 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual link for each port Jani Nikula @ 2014-11-15 1:15 ` shuang.he 0 siblings, 0 replies; 28+ messages in thread From: shuang.he @ 2014-11-15 1:15 UTC (permalink / raw) To: shuang.he, intel-gfx, jani.nikula Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=290/291->290/291 PNV: pass/total=351/356->355/356 ILK: pass/total=371/372->366/372 IVB: pass/total=545/546->545/546 SNB: pass/total=424/425->424/425 HSW: pass/total=579/579->579/579 BDW: pass/total=434/435->434/435 -------------------------------------Detailed------------------------------------- test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)... PNV: Intel_gpu_tools, igt_gen3_render_linear_blits, CRASH(1, M23) -> PASS(1, M23) PNV: Intel_gpu_tools, igt_gen3_render_mixed_blits, CRASH(1, M23) -> PASS(1, M23) PNV: Intel_gpu_tools, igt_gen3_render_tiledx_blits, CRASH(2, M23)DMESG_WARN(1, M23)NRUN(1, M23) -> PASS(1, M23) PNV: Intel_gpu_tools, igt_gen3_render_tiledy_blits, CRASH(1, M23) -> PASS(1, M23) ILK: Intel_gpu_tools, igt_kms_flip_bcs-flip-vs-modeset-interruptible, PASS(1, M6) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible, PASS(1, M6) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_rcs-flip-vs-dpms, PASS(1, M6) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-ts-check, PASS(1, M6) -> NSPT(1, M26)DMESG_WARN(2, M26)PASS(1, M26) ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, PASS(1, M6) -> DMESG_WARN(1, M26)PASS(3, M26) ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(1, M6) -> FAIL(1, M26)TIMEOUT(3, M26) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] BYT DSI Dual Link Support 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula ` (2 preceding siblings ...) 2014-11-14 14:54 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual link for each port Jani Nikula @ 2014-11-24 8:10 ` Singh, Gaurav K 2014-11-24 9:01 ` Jani Nikula 3 siblings, 1 reply; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-24 8:10 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar Hi Jani, Thanks for the review comments. Regarding the first 2 patches, I was doing almost the same thing in my 3rd and 4th patch. But your patches are more generic. Regarding the 3rd patch, I have a comment: Since in case of dual link panels, few panels may require sequence to be sent only on Port A or Port C or both. In that case, for_each_dsi_port(port, intel_dsi->ports) will cause it to be sent to both ports. To resolve this, in the earlier patches, intel_dsi->port was used which gets calculated to either 0 or 1 in mipi_exec_send_packet(). This value of 0 or 1 is dependent on sequence block#53. From now on as we will be using the _PORT3() macro for using proper MIPI regs, then for this scenario, we may need to have some workaround/hardcode type of code again. May I know your suggestion on this? With regards, Gaurav On 11/14/2014 8:24 PM, Jani Nikula wrote: > Hi Shobhit and Gaurav - > > I've been pondering this whole MIPI DSI pipes vs. ports thing and > discussing with Ville and others. Rather than try and fail in explaining > the ideas, here are some concrete patches to describe what I'd like to > be done first. > > The most important thing is that we don't confuse the pipes and > ports. Getting confused was easy with the pipe B mapping to port C, and > the register defines being very confused/confusing about it. These > patches attempt to fix that. Before adding dual link support, there's a > simple function mapping the pipe to port. > > Next up is expanding that to handle multiple ports driven from one > pipe. That's handled by adding intel_dsi->ports bitmap that has the bit > set for each port that is to be driven. I've added the bitmap and some > helpers to iterate over the configured ports, but there's no actual > support for doing the configuration. I'm hoping you could take over from > here. There's a sample patch about the usage. > > I'm sorry it's taken me so long to reply. With the new stuff coming in, > I really think it's important to get the foundation right > first. Especially because I'm to blame for getting some of the port/pipe > stuff confused in the first place... > > BR, > Jani. > > > > Jani Nikula (3): > drm/i915/dsi: clean up MIPI DSI pipe vs. port usage > drm/i915/dsi: add ports to intel_dsi to describe the ports being > driven > drm/i915/dsi: an example how to handle dual link for each port > > drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dsi.c | 151 ++++++++--------- > drivers/gpu/drm/i915/intel_dsi.h | 19 +++ > drivers/gpu/drm/i915/intel_dsi_cmd.c | 76 ++++----- > 4 files changed, 290 insertions(+), 259 deletions(-) > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] BYT DSI Dual Link Support 2014-11-24 8:10 ` [PATCH 0/3] BYT DSI Dual Link Support Singh, Gaurav K @ 2014-11-24 9:01 ` Jani Nikula 2014-11-26 17:21 ` Singh, Gaurav K 2014-11-27 7:50 ` Singh, Gaurav K 0 siblings, 2 replies; 28+ messages in thread From: Jani Nikula @ 2014-11-24 9:01 UTC (permalink / raw) To: Singh, Gaurav K, intel-gfx, shobhit.kumar On Mon, 24 Nov 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote: > Hi Jani, > > Thanks for the review comments. > > Regarding the first 2 patches, I was doing almost the same thing in my > 3rd and 4th patch. But your patches are more generic. > > Regarding the 3rd patch, I have a comment: > > Since in case of dual link panels, few panels may require sequence to be > sent only on Port A or Port C or both. In that case, > for_each_dsi_port(port, intel_dsi->ports) will cause it to be sent to > both ports. > To resolve this, in the earlier patches, intel_dsi->port was used which > gets calculated to either 0 or 1 in mipi_exec_send_packet(). This value > of 0 or 1 is dependent on sequence block#53. > > From now on as we will be using the _PORT3() macro for using proper > MIPI regs, then for this scenario, we may need to have some > workaround/hardcode type of code again. May I know your suggestion on this? Perhaps patch 3/3 was a bad place for the for_each_dsi_port example - it should have been put into intel_dsi.c. Maybe you'll need to add the port as parameter to the functions in intel_dsi_cmd.c, and let the caller decide which port should be used? I want to avoid any platform/panel specific special casing in intel_dsi.c and intel_dsi_cmd.c. I think the general case for for_each_dsi_port is in intel_dsi.c anyway. BR, Jani. > > With regards, > Gaurav > > On 11/14/2014 8:24 PM, Jani Nikula wrote: >> Hi Shobhit and Gaurav - >> >> I've been pondering this whole MIPI DSI pipes vs. ports thing and >> discussing with Ville and others. Rather than try and fail in explaining >> the ideas, here are some concrete patches to describe what I'd like to >> be done first. >> >> The most important thing is that we don't confuse the pipes and >> ports. Getting confused was easy with the pipe B mapping to port C, and >> the register defines being very confused/confusing about it. These >> patches attempt to fix that. Before adding dual link support, there's a >> simple function mapping the pipe to port. >> >> Next up is expanding that to handle multiple ports driven from one >> pipe. That's handled by adding intel_dsi->ports bitmap that has the bit >> set for each port that is to be driven. I've added the bitmap and some >> helpers to iterate over the configured ports, but there's no actual >> support for doing the configuration. I'm hoping you could take over from >> here. There's a sample patch about the usage. >> >> I'm sorry it's taken me so long to reply. With the new stuff coming in, >> I really think it's important to get the foundation right >> first. Especially because I'm to blame for getting some of the port/pipe >> stuff confused in the first place... >> >> BR, >> Jani. >> >> >> >> Jani Nikula (3): >> drm/i915/dsi: clean up MIPI DSI pipe vs. port usage >> drm/i915/dsi: add ports to intel_dsi to describe the ports being >> driven >> drm/i915/dsi: an example how to handle dual link for each port >> >> drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- >> drivers/gpu/drm/i915/intel_dsi.c | 151 ++++++++--------- >> drivers/gpu/drm/i915/intel_dsi.h | 19 +++ >> drivers/gpu/drm/i915/intel_dsi_cmd.c | 76 ++++----- >> 4 files changed, 290 insertions(+), 259 deletions(-) >> > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] BYT DSI Dual Link Support 2014-11-24 9:01 ` Jani Nikula @ 2014-11-26 17:21 ` Singh, Gaurav K 2014-11-27 7:50 ` Singh, Gaurav K 1 sibling, 0 replies; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-26 17:21 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar On 11/24/2014 2:31 PM, Jani Nikula wrote: > On Mon, 24 Nov 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote: >> Hi Jani, >> >> Thanks for the review comments. >> >> Regarding the first 2 patches, I was doing almost the same thing in my >> 3rd and 4th patch. But your patches are more generic. >> >> Regarding the 3rd patch, I have a comment: >> >> Since in case of dual link panels, few panels may require sequence to be >> sent only on Port A or Port C or both. In that case, >> for_each_dsi_port(port, intel_dsi->ports) will cause it to be sent to >> both ports. >> To resolve this, in the earlier patches, intel_dsi->port was used which >> gets calculated to either 0 or 1 in mipi_exec_send_packet(). This value >> of 0 or 1 is dependent on sequence block#53. >> >> From now on as we will be using the _PORT3() macro for using proper >> MIPI regs, then for this scenario, we may need to have some >> workaround/hardcode type of code again. May I know your suggestion on this? > Perhaps patch 3/3 was a bad place for the for_each_dsi_port example - it > should have been put into intel_dsi.c. Maybe you'll need to add the port > as parameter to the functions in intel_dsi_cmd.c, and let the caller > decide which port should be used? I want to avoid any platform/panel > specific special casing in intel_dsi.c and intel_dsi_cmd.c. > > I think the general case for for_each_dsi_port is in intel_dsi.c anyway. > > BR, > Jani. Hi Jani, My patches are ready on top of your first 2 patches. Once your patches are merged, I will push my whole set of patches for review. With regards, Gaurav > > >> With regards, >> Gaurav >> >> On 11/14/2014 8:24 PM, Jani Nikula wrote: >>> Hi Shobhit and Gaurav - >>> >>> I've been pondering this whole MIPI DSI pipes vs. ports thing and >>> discussing with Ville and others. Rather than try and fail in explaining >>> the ideas, here are some concrete patches to describe what I'd like to >>> be done first. >>> >>> The most important thing is that we don't confuse the pipes and >>> ports. Getting confused was easy with the pipe B mapping to port C, and >>> the register defines being very confused/confusing about it. These >>> patches attempt to fix that. Before adding dual link support, there's a >>> simple function mapping the pipe to port. >>> >>> Next up is expanding that to handle multiple ports driven from one >>> pipe. That's handled by adding intel_dsi->ports bitmap that has the bit >>> set for each port that is to be driven. I've added the bitmap and some >>> helpers to iterate over the configured ports, but there's no actual >>> support for doing the configuration. I'm hoping you could take over from >>> here. There's a sample patch about the usage. >>> >>> I'm sorry it's taken me so long to reply. With the new stuff coming in, >>> I really think it's important to get the foundation right >>> first. Especially because I'm to blame for getting some of the port/pipe >>> stuff confused in the first place... >>> >>> BR, >>> Jani. >>> >>> >>> >>> Jani Nikula (3): >>> drm/i915/dsi: clean up MIPI DSI pipe vs. port usage >>> drm/i915/dsi: add ports to intel_dsi to describe the ports being >>> driven >>> drm/i915/dsi: an example how to handle dual link for each port >>> >>> drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- >>> drivers/gpu/drm/i915/intel_dsi.c | 151 ++++++++--------- >>> drivers/gpu/drm/i915/intel_dsi.h | 19 +++ >>> drivers/gpu/drm/i915/intel_dsi_cmd.c | 76 ++++----- >>> 4 files changed, 290 insertions(+), 259 deletions(-) >>> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] BYT DSI Dual Link Support 2014-11-24 9:01 ` Jani Nikula 2014-11-26 17:21 ` Singh, Gaurav K @ 2014-11-27 7:50 ` Singh, Gaurav K 2014-11-28 17:19 ` Daniel Vetter 1 sibling, 1 reply; 28+ messages in thread From: Singh, Gaurav K @ 2014-11-27 7:50 UTC (permalink / raw) To: Jani Nikula, intel-gfx, shobhit.kumar On 11/24/2014 2:31 PM, Jani Nikula wrote: > On Mon, 24 Nov 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote: >> Hi Jani, >> >> Thanks for the review comments. >> >> Regarding the first 2 patches, I was doing almost the same thing in my >> 3rd and 4th patch. But your patches are more generic. >> >> Regarding the 3rd patch, I have a comment: >> >> Since in case of dual link panels, few panels may require sequence to be >> sent only on Port A or Port C or both. In that case, >> for_each_dsi_port(port, intel_dsi->ports) will cause it to be sent to >> both ports. >> To resolve this, in the earlier patches, intel_dsi->port was used which >> gets calculated to either 0 or 1 in mipi_exec_send_packet(). This value >> of 0 or 1 is dependent on sequence block#53. >> >> From now on as we will be using the _PORT3() macro for using proper >> MIPI regs, then for this scenario, we may need to have some >> workaround/hardcode type of code again. May I know your suggestion on this? > Perhaps patch 3/3 was a bad place for the for_each_dsi_port example - it > should have been put into intel_dsi.c. Maybe you'll need to add the port > as parameter to the functions in intel_dsi_cmd.c, and let the caller > decide which port should be used? I want to avoid any platform/panel > specific special casing in intel_dsi.c and intel_dsi_cmd.c. > > I think the general case for for_each_dsi_port is in intel_dsi.c anyway. > > BR, > Jani. Jani, I have taken care of this in the next version of dual link patches. PATCH 3/3 need not be merged as it has already been taken care as part of dual link implementation. Once your first two patches gets merged in drm-intel-nightly branch, I can push the next version of dual link patches for review. With regards, Gaurav > >> With regards, >> Gaurav >> >> On 11/14/2014 8:24 PM, Jani Nikula wrote: >>> Hi Shobhit and Gaurav - >>> >>> I've been pondering this whole MIPI DSI pipes vs. ports thing and >>> discussing with Ville and others. Rather than try and fail in explaining >>> the ideas, here are some concrete patches to describe what I'd like to >>> be done first. >>> >>> The most important thing is that we don't confuse the pipes and >>> ports. Getting confused was easy with the pipe B mapping to port C, and >>> the register defines being very confused/confusing about it. These >>> patches attempt to fix that. Before adding dual link support, there's a >>> simple function mapping the pipe to port. >>> >>> Next up is expanding that to handle multiple ports driven from one >>> pipe. That's handled by adding intel_dsi->ports bitmap that has the bit >>> set for each port that is to be driven. I've added the bitmap and some >>> helpers to iterate over the configured ports, but there's no actual >>> support for doing the configuration. I'm hoping you could take over from >>> here. There's a sample patch about the usage. >>> >>> I'm sorry it's taken me so long to reply. With the new stuff coming in, >>> I really think it's important to get the foundation right >>> first. Especially because I'm to blame for getting some of the port/pipe >>> stuff confused in the first place... >>> >>> BR, >>> Jani. >>> >>> >>> >>> Jani Nikula (3): >>> drm/i915/dsi: clean up MIPI DSI pipe vs. port usage >>> drm/i915/dsi: add ports to intel_dsi to describe the ports being >>> driven >>> drm/i915/dsi: an example how to handle dual link for each port >>> >>> drivers/gpu/drm/i915/i915_reg.h | 303 ++++++++++++++++++----------------- >>> drivers/gpu/drm/i915/intel_dsi.c | 151 ++++++++--------- >>> drivers/gpu/drm/i915/intel_dsi.h | 19 +++ >>> drivers/gpu/drm/i915/intel_dsi_cmd.c | 76 ++++----- >>> 4 files changed, 290 insertions(+), 259 deletions(-) >>> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] BYT DSI Dual Link Support 2014-11-27 7:50 ` Singh, Gaurav K @ 2014-11-28 17:19 ` Daniel Vetter 0 siblings, 0 replies; 28+ messages in thread From: Daniel Vetter @ 2014-11-28 17:19 UTC (permalink / raw) To: Singh, Gaurav K; +Cc: Jani Nikula, intel-gfx On Thu, Nov 27, 2014 at 01:20:06PM +0530, Singh, Gaurav K wrote: > > On 11/24/2014 2:31 PM, Jani Nikula wrote: > >On Mon, 24 Nov 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote: > >>Hi Jani, > >> > >>Thanks for the review comments. > >> > >>Regarding the first 2 patches, I was doing almost the same thing in my > >>3rd and 4th patch. But your patches are more generic. > >> > >>Regarding the 3rd patch, I have a comment: > >> > >>Since in case of dual link panels, few panels may require sequence to be > >>sent only on Port A or Port C or both. In that case, > >>for_each_dsi_port(port, intel_dsi->ports) will cause it to be sent to > >>both ports. > >>To resolve this, in the earlier patches, intel_dsi->port was used which > >>gets calculated to either 0 or 1 in mipi_exec_send_packet(). This value > >>of 0 or 1 is dependent on sequence block#53. > >> > >> From now on as we will be using the _PORT3() macro for using proper > >>MIPI regs, then for this scenario, we may need to have some > >>workaround/hardcode type of code again. May I know your suggestion on this? > >Perhaps patch 3/3 was a bad place for the for_each_dsi_port example - it > >should have been put into intel_dsi.c. Maybe you'll need to add the port > >as parameter to the functions in intel_dsi_cmd.c, and let the caller > >decide which port should be used? I want to avoid any platform/panel > >specific special casing in intel_dsi.c and intel_dsi_cmd.c. > > > >I think the general case for for_each_dsi_port is in intel_dsi.c anyway. > > > >BR, > >Jani. > Jani, > > I have taken care of this in the next version of dual link patches. PATCH > 3/3 need not be merged as it has already been taken care as part of dual > link implementation. Once your first two patches gets merged in > drm-intel-nightly branch, I can push the next version of dual link patches > for review. > > With regards, Both patches merged, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2014-11-28 17:19 UTC | newest] Thread overview: 28+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-10-29 8:42 [PATCH 00/11] BYT DSI Dual Link Support Gaurav K Singh 2014-10-29 8:42 ` [PATCH 01/11] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh 2014-10-29 8:42 ` [PATCH 02/11] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT Gaurav K Singh 2014-10-29 8:42 ` [PATCH 03/11] drm/i915: Cleanup in i915_reg.h for all MIPI regs Gaurav K Singh 2014-10-29 8:42 ` [PATCH 04/11] drm/i915: Cleanup patch for " Gaurav K Singh 2014-10-29 8:42 ` [PATCH 05/11] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh 2014-10-29 8:42 ` [PATCH 06/11] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh 2014-10-29 8:42 ` [PATCH 07/11] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh 2014-10-29 8:42 ` [PATCH 08/11] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh 2014-10-29 8:42 ` [PATCH 09/11] drm/i915: MIPI Timings related changes for " Gaurav K Singh 2014-10-29 8:42 ` [PATCH 10/11] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh 2014-10-29 8:42 ` [PATCH 11/11] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh 2014-11-13 14:53 ` [PATCH 00/11] BYT DSI Dual Link Support Kumar, Shobhit 2014-11-14 14:54 ` [PATCH 0/3] " Jani Nikula 2014-11-14 14:54 ` [PATCH 1/3] drm/i915/dsi: clean up MIPI DSI pipe vs. port usage Jani Nikula 2014-11-26 17:20 ` Singh, Gaurav K 2014-11-26 18:08 ` Daniel Vetter 2014-11-26 18:43 ` Singh, Gaurav K 2014-11-27 7:28 ` Singh, Gaurav K 2014-11-14 14:54 ` [PATCH 2/3] drm/i915/dsi: add ports to intel_dsi to describe the ports being driven Jani Nikula 2014-11-27 7:24 ` Singh, Gaurav K 2014-11-14 14:54 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual link for each port Jani Nikula 2014-11-15 1:15 ` [PATCH 3/3] drm/i915/dsi: an example how to handle dual shuang.he 2014-11-24 8:10 ` [PATCH 0/3] BYT DSI Dual Link Support Singh, Gaurav K 2014-11-24 9:01 ` Jani Nikula 2014-11-26 17:21 ` Singh, Gaurav K 2014-11-27 7:50 ` Singh, Gaurav K 2014-11-28 17:19 ` Daniel Vetter
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).