[PATCH 0/4] BYT DSI Enable on Port C

[PATCH 0/4] BYT DSI Enable on Port C

[Gaurav K Singh]

Hi,

These set of patches build on top of the existing DSI Video mode support to
enable DSI on Port C. These patches have been tested on a 1920 x 1200 panel
on Port C.

Regards
Gaurav

Gaurav K Singh (4):
  drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C
  drm/i915: DSI sequence related changes for DSI Port C
  drm/i915: Enable MIPI PHY transparent latch for DSI Port C
  drm/i915: Get HW state changes required for DSI port C

 drivers/gpu/drm/i915/intel_dsi.c           |   28 ++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
 drivers/gpu/drm/i915/intel_dsi_pll.c       |    3 ++-
 3 files changed, 32 insertions(+), 8 deletions(-)

-- 
1.7.9.5

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[PATCH 1/4] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Gaurav K Singh]

DSI Pll1 is used for enabling DSI on Port C.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..74a6fb5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -243,7 +243,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 
 	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
-	if (intel_dsi->dual_link)
+	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
+	    (intel_dsi->ports == (1 << PORT_C)))
 		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
 
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
-- 
1.7.9.5

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[PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Gaurav K Singh]

For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now  the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269..e7e2e52 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
 	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 
-	port = intel_dsi_seq_port_to_port(seq_port);
+	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
+	 * Now  the sequence of DSI single link on Port A and Port C will based
+	 * on the DVO port from VBT block 2.
+	 */
+	if (intel_dsi->ports == (1 << PORT_C))
+		port = PORT_C;
+	else
+		port = intel_dsi_seq_port_to_port(seq_port);
 	/* LP or HS mode */
 	intel_dsi->hs = mode;
 
-- 
1.7.9.5

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[PATCH 3/4] drm/i915: Enable MIPI PHY transparent latch for DSI Port C

[Gaurav K Singh]

Common bit to be used for both DSI Port A & DSI Port C.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8f8b952..215d004 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -177,7 +177,12 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 		usleep_range(2500, 3000);
 
 		val = I915_READ(MIPI_PORT_CTRL(port));
-		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+
+		/* Enable MIPI PHY transparent latch
+		 * Common bit for both MIPI Port A & MIPI Port C
+		 * No similar bit in MIPI Port C reg
+		 */
+		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 		usleep_range(1000, 1500);
 
 		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-- 
1.7.9.5

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[PATCH 4/4] drm/i915: Get HW state changes required for DSI port C

[Gaurav K Singh]

Due to some hardware limitations, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with Pipe B.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 215d004..0334c4d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -398,8 +398,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum intel_display_power_domain power_domain;
-	u32 port_ctl, func;
+	u32 dsi_status, func;
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
@@ -409,13 +410,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		return false;
 
 	/* XXX: this only works for one DSI output */
-	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
-		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
 		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 
-		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
+		/* Due to some hardware limitations, MIPI Port C DPI Enable
+		 * bit does not get set. To check whether DSI Port C was
+		 * enabled in BIOS, check the Pipe B enable bit
+		 */
+		if (port == PORT_C)
+			dsi_status = I915_READ(PIPECONF(PIPE_B)) &
+							PIPECONF_ENABLE;
+		else
+			dsi_status = I915_READ(MIPI_PORT_CTRL(port)) &
+							DPI_ENABLE;
+
+		if (dsi_status || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
-				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
+				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
 				return true;
 			}
 		}
-- 
1.7.9.5

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[PATCH] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Gaurav K Singh]

DSI Pll1 is used for enabling DSI on Port C.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..9b7f6a5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -241,9 +241,12 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 		return;
 	}
 
-	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
+	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
+	    (intel_dsi->ports == (1 << PORT_A)))
+		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
-	if (intel_dsi->dual_link)
+	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
+	    (intel_dsi->ports == (1 << PORT_C)))
 		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
 
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
-- 
1.7.9.5

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Re: [PATCH] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Jani Nikula]

On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> DSI Pll1 is used for enabling DSI on Port C.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 8957f10..9b7f6a5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -241,9 +241,12 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  		return;
>  	}
>  
> -	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
> +	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
> +	    (intel_dsi->ports == (1 << PORT_A)))
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> -	if (intel_dsi->dual_link)
> +	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
> +	    (intel_dsi->ports == (1 << PORT_C)))
>  		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

In other words, patches 1 and 2 can be squashed into one that has:

	if (intel_dsi->ports & (1 << PORT_A))
		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

	if (intel_dsi->ports & (1 << PORT_C))
		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

Right?

BR,
Jani.

>  
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
> -- 
> 1.7.9.5
>
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-- 
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Re: [PATCH 4/4] drm/i915: Get HW state changes required for DSI port C

[Jani Nikula]

On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Due to some hardware limitations, MIPI Port C DPI Enable bit
> does not get set. To check whether DSI Port C was enabled in BIOS,
> check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
> is linked with Pipe B.

"due to some hardware limitations" is awfully vague. The same code will
be used on many platforms; I doubt this applies to all of them. Is there
a workaround name for this?

BR,
Jani.

>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   21 ++++++++++++++++-----
>  1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 215d004..0334c4d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -398,8 +398,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  				   enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum intel_display_power_domain power_domain;
> -	u32 port_ctl, func;
> +	u32 dsi_status, func;
>  	enum port port;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -409,13 +410,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  		return false;
>  
>  	/* XXX: this only works for one DSI output */
> -	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
> -		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
>  		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
>  
> -		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
> +		/* Due to some hardware limitations, MIPI Port C DPI Enable
> +		 * bit does not get set. To check whether DSI Port C was
> +		 * enabled in BIOS, check the Pipe B enable bit
> +		 */
> +		if (port == PORT_C)
> +			dsi_status = I915_READ(PIPECONF(PIPE_B)) &
> +							PIPECONF_ENABLE;
> +		else
> +			dsi_status = I915_READ(MIPI_PORT_CTRL(port)) &
> +							DPI_ENABLE;
> +
> +		if (dsi_status || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>  			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
> -				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
> +				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
>  				return true;
>  			}
>  		}
> -- 
> 1.7.9.5
>
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-- 
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Re: [PATCH 4/4] drm/i915: Get HW state changes required for DSI port C

[Singh, Gaurav K]

On 12/8/2014 5:07 PM, Jani Nikula wrote:
> On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> Due to some hardware limitations, MIPI Port C DPI Enable bit
>> does not get set. To check whether DSI Port C was enabled in BIOS,
>> check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
>> is linked with Pipe B.
> "due to some hardware limitations" is awfully vague. The same code will
> be used on many platforms; I doubt this applies to all of them. Is there
> a workaround name for this?
>
> BR,
> Jani.

Hi Jani,

This is currently only for BYT, I missed to add in this patch commit header.

Software workaround for getting the HW status of DSI Port C on BYT, will 
it be fine if I include this in the commit header.

With regards,
Gaurav
>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi.c |   21 ++++++++++++++++-----
>>   1 file changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 215d004..0334c4d 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -398,8 +398,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>   				   enum pipe *pipe)
>>   {
>>   	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>   	enum intel_display_power_domain power_domain;
>> -	u32 port_ctl, func;
>> +	u32 dsi_status, func;
>>   	enum port port;
>>   
>>   	DRM_DEBUG_KMS("\n");
>> @@ -409,13 +410,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>   		return false;
>>   
>>   	/* XXX: this only works for one DSI output */
>> -	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
>> -		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>   		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
>>   
>> -		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>> +		/* Due to some hardware limitations, MIPI Port C DPI Enable
>> +		 * bit does not get set. To check whether DSI Port C was
>> +		 * enabled in BIOS, check the Pipe B enable bit
>> +		 */
>> +		if (port == PORT_C)
>> +			dsi_status = I915_READ(PIPECONF(PIPE_B)) &
>> +							PIPECONF_ENABLE;
>> +		else
>> +			dsi_status = I915_READ(MIPI_PORT_CTRL(port)) &
>> +							DPI_ENABLE;
>> +
>> +		if (dsi_status || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>>   			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
>> -				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
>> +				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
>>   				return true;
>>   			}
>>   		}
>> -- 
>> 1.7.9.5
>>
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Re: [PATCH 4/4] drm/i915: Get HW state changes required for DSI port C

[Jani Nikula]

On Mon, 08 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> On 12/8/2014 5:07 PM, Jani Nikula wrote:
>> On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>>> Due to some hardware limitations, MIPI Port C DPI Enable bit
>>> does not get set. To check whether DSI Port C was enabled in BIOS,
>>> check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
>>> is linked with Pipe B.
>> "due to some hardware limitations" is awfully vague. The same code will
>> be used on many platforms; I doubt this applies to all of them. Is there
>> a workaround name for this?
>>
>> BR,
>> Jani.
>
> Hi Jani,
>
> This is currently only for BYT, I missed to add in this patch commit header.
>
> Software workaround for getting the HW status of DSI Port C on BYT, will 
> it be fine if I include this in the commit header.

No, it's not enough to amend the commit message. I prefer the
implementation to be generic for all platforms, and quirks like this
need to be special cases isolated as much as possible.

Please do something along the lines of:

	port_ctl = I915_READ(MIPI_PORT_CTRL(port));
	func = I915_READ(MIPI_DSI_FUNC_PRG(port));

	dpi_enabled = port_ctl & DPI_ENABLE;

        /* Due to some BYT hardware limitation ... etc... */
        if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && port == PORT_C)
		dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

	if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK))

	/* etc */

As you see, the exception clearly stands out, it's specific to BYT, and
it's easy to amend the condition or rip it out altogether as needed.

BR,
Jani.

>
> With regards,
> Gaurav
>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_dsi.c |   21 ++++++++++++++++-----
>>>   1 file changed, 16 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>>> index 215d004..0334c4d 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>>> @@ -398,8 +398,9 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>>   				   enum pipe *pipe)
>>>   {
>>>   	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>   	enum intel_display_power_domain power_domain;
>>> -	u32 port_ctl, func;
>>> +	u32 dsi_status, func;
>>>   	enum port port;
>>>   
>>>   	DRM_DEBUG_KMS("\n");
>>> @@ -409,13 +410,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>>   		return false;
>>>   
>>>   	/* XXX: this only works for one DSI output */
>>> -	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
>>> -		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>   		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
>>>   
>>> -		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>>> +		/* Due to some hardware limitations, MIPI Port C DPI Enable
>>> +		 * bit does not get set. To check whether DSI Port C was
>>> +		 * enabled in BIOS, check the Pipe B enable bit
>>> +		 */
>>> +		if (port == PORT_C)
>>> +			dsi_status = I915_READ(PIPECONF(PIPE_B)) &
>>> +							PIPECONF_ENABLE;
>>> +		else
>>> +			dsi_status = I915_READ(MIPI_PORT_CTRL(port)) &
>>> +							DPI_ENABLE;
>>> +
>>> +		if (dsi_status || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>>>   			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
>>> -				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
>>> +				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
>>>   				return true;
>>>   			}
>>>   		}
>>> -- 
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

-- 
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Re: [PATCH 4/4] drm/i915: Get HW state changes required for DSI port C

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK              +1                 364/366              365/366
SNB                                  448/450              448/450
IVB                                  497/498              497/498
BYT                                  289/289              289/289
HSW                                  563/564              563/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 ILK  igt_kms_flip_wf_vblank-ts-check      DMESG_WARN(1, M26)PASS(3, M26M37)      PASS(1, M37)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK                 -1              364/366              363/366
SNB                 -1              448/450              447/450
IVB                                  497/498              497/498
BYT                                  289/289              289/289
HSW                                  563/564              563/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible      PASS(2, M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_wf_vblank-ts-check      DMESG_WARN(1, M26)PASS(3, M26M37)      NSPT(1, M26)
*SNB  igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2      PASS(2, M35M22)      DMESG_WARN(1, M22)
Note: You need to pay more attention to line start with '*'
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[PATCH 1/4] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Gaurav K Singh]

DSI Pll1 is used for enabling DSI on Port C.

v2: Addressed review comments of Jani
    - Used & operator instead of == for intel_dsi->ports

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..3622d0b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -241,9 +241,10 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 		return;
 	}
 
-	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
+	if (intel_dsi->ports & (1 << PORT_A))
+		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
-	if (intel_dsi->dual_link)
+	if (intel_dsi->ports & (1 << PORT_C))
 		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
 
 	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
-- 
1.7.9.5

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[PATCH 4/4] drm/i915: Software workaround for getting the HW status of DSI Port C on BYT

[Gaurav K Singh]

Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with Pipe B.

v2: Addressed review comments of Jani, Nikula
    - Used platform checks for this software workaround for BYT

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 215d004..42b6d6f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -398,8 +398,10 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct drm_device *dev = encoder->base.dev;
 	enum intel_display_power_domain power_domain;
-	u32 port_ctl, func;
+	u32 dpi_enabled, func;
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
@@ -409,13 +411,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		return false;
 
 	/* XXX: this only works for one DSI output */
-	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
-		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
+	for_each_dsi_port(port, intel_dsi->ports) {
 		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
+		dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
+							DPI_ENABLE;
+
+		/* Due to some hardware limitations on BYT, MIPI Port C DPI
+		 * Enable bit does not get set. To check whether DSI Port C
+		 * was enabled in BIOS, check the Pipe B enable bit
+		 */
+		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+		    (port == PORT_C))
+			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
+							PIPECONF_ENABLE;
 
-		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
+		if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
-				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
+				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
 				return true;
 			}
 		}
-- 
1.7.9.5

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Re: [PATCH] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Singh, Gaurav K]

On 12/8/2014 5:03 PM, Jani Nikula wrote:
> On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> DSI Pll1 is used for enabling DSI on Port C.
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi_pll.c |    7 +++++--
>>   1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index 8957f10..9b7f6a5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -241,9 +241,12 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>>   		return;
>>   	}
>>   
>> -	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>> +	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
>> +	    (intel_dsi->ports == (1 << PORT_A)))
>> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>>   
>> -	if (intel_dsi->dual_link)
>> +	if ((intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) ||
>> +	    (intel_dsi->ports == (1 << PORT_C)))
>>   		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> In other words, patches 1 and 2 can be squashed into one that has:
>
> 	if (intel_dsi->ports & (1 << PORT_A))
> 		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>
> 	if (intel_dsi->ports & (1 << PORT_C))
> 		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
>
> Right?
>
> BR,
> Jani.
Jani,

Yes, uploaded the new patch addressing your comments.

With regards,
Gaurav
>
>>   
>>   	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 1/4] drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

[Jani Nikula]

On Tue, 09 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> DSI Pll1 is used for enabling DSI on Port C.
>
> v2: Addressed review comments of Jani
>     - Used & operator instead of == for intel_dsi->ports
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 8957f10..3622d0b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -241,9 +241,10 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  		return;
>  	}
>  
> -	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
> +	if (intel_dsi->ports & (1 << PORT_A))
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> -	if (intel_dsi->dual_link)
> +	if (intel_dsi->ports & (1 << PORT_C))
>  		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
>  
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
> -- 
> 1.7.9.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 4/4] drm/i915: Software workaround for getting the HW status of DSI Port C on BYT

[Jani Nikula]

On Tue, 09 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
> does not get set. To check whether DSI Port C was enabled in BIOS,
> check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
> is linked with Pipe B.
>
> v2: Addressed review comments of Jani, Nikula
>     - Used platform checks for this software workaround for BYT
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

I'll take your word for the hardware limitation itself, otherwise

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 215d004..42b6d6f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -398,8 +398,10 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  				   enum pipe *pipe)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct drm_device *dev = encoder->base.dev;
>  	enum intel_display_power_domain power_domain;
> -	u32 port_ctl, func;
> +	u32 dpi_enabled, func;
>  	enum port port;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -409,13 +411,23 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  		return false;
>  
>  	/* XXX: this only works for one DSI output */
> -	for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) {
> -		port_ctl = I915_READ(MIPI_PORT_CTRL(port));
> +	for_each_dsi_port(port, intel_dsi->ports) {
>  		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
> +		dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
> +							DPI_ENABLE;
> +
> +		/* Due to some hardware limitations on BYT, MIPI Port C DPI
> +		 * Enable bit does not get set. To check whether DSI Port C
> +		 * was enabled in BIOS, check the Pipe B enable bit
> +		 */
> +		if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +		    (port == PORT_C))
> +			dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
> +							PIPECONF_ENABLE;
>  
> -		if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
> +		if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
>  			if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
> -				*pipe = port == PORT_A ? PIPE_A : PIPE_C;
> +				*pipe = port == PORT_A ? PIPE_A : PIPE_B;
>  				return true;
>  			}
>  		}
> -- 
> 1.7.9.5
>
> _______________________________________________
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-- 
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Re: [PATCH 3/4] drm/i915: Enable MIPI PHY transparent latch for DSI Port C

[Jani Nikula]

On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Common bit to be used for both DSI Port A & DSI Port C.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

At some point I'd like to have the bits specific to port A only
extracted outside of the for loop, but this is fine for now.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 8f8b952..215d004 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -177,7 +177,12 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  		usleep_range(2500, 3000);
>  
>  		val = I915_READ(MIPI_PORT_CTRL(port));
> -		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> +
> +		/* Enable MIPI PHY transparent latch
> +		 * Common bit for both MIPI Port A & MIPI Port C
> +		 * No similar bit in MIPI Port C reg
> +		 */
> +		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
>  		usleep_range(1000, 1500);
>  
>  		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> -- 
> 1.7.9.5
>
> _______________________________________________
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-- 
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Re: [PATCH 4/4] drm/i915: Software workaround for getting the HW status of DSI Port C on BYT

[Daniel Vetter]

On Tue, Dec 09, 2014 at 10:34:40AM +0200, Jani Nikula wrote:
> On Tue, 09 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> > Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
> > does not get set. To check whether DSI Port C was enabled in BIOS,
> > check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
> > is linked with Pipe B.
> >
> > v2: Addressed review comments of Jani, Nikula
> >     - Used platform checks for this software workaround for BYT
> >
> > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> I'll take your word for the hardware limitation itself, otherwise
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

All three (with the squashed one) patches merged to dinq, thanks.
-Daniel
-- 
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Re: [PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Singh, Gaurav K]

On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
> For DSI Port A & C, the seq_port value has been set to 0 now in VBT
> Now  the sequence of DSI single link on Port A and Port C will based
> on the DVO port from VBT block 2.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f8c2269..e7e2e52 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>   	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
>   	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>   
> -	port = intel_dsi_seq_port_to_port(seq_port);
> +	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
> +	 * Now  the sequence of DSI single link on Port A and Port C will based
> +	 * on the DVO port from VBT block 2.
> +	 */
> +	if (intel_dsi->ports == (1 << PORT_C))
> +		port = PORT_C;
> +	else
> +		port = intel_dsi_seq_port_to_port(seq_port);
>   	/* LP or HS mode */
>   	intel_dsi->hs = mode;
>   

Jani,

Need your reviewed-by on this patch too.

With regards,
Gaurav
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Re: [PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Jani Nikula]

On Tue, 09 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
>> For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>> Now  the sequence of DSI single link on Port A and Port C will based
>> on the DVO port from VBT block 2.
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
>>   1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index f8c2269..e7e2e52 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>>   	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
>>   	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>>   
>> -	port = intel_dsi_seq_port_to_port(seq_port);
>> +	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>> +	 * Now  the sequence of DSI single link on Port A and Port C will based
>> +	 * on the DVO port from VBT block 2.
>> +	 */
>> +	if (intel_dsi->ports == (1 << PORT_C))
>> +		port = PORT_C;
>> +	else
>> +		port = intel_dsi_seq_port_to_port(seq_port);
>>   	/* LP or HS mode */
>>   	intel_dsi->hs = mode;
>>   
>
> Jani,
>
> Need your reviewed-by on this patch too.

Okay, I was confused because there were actually five patches in this
four patch series! ;)

The *code* is

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

because I understand it, but frankly both the commit message and the
comment confuse me more.


>
> With regards,
> Gaurav
> _______________________________________________
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Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Singh, Gaurav K]

On 12/9/2014 4:00 PM, Jani Nikula wrote:
> On Tue, 09 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
>> On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
>>> For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>>> Now  the sequence of DSI single link on Port A and Port C will based
>>> on the DVO port from VBT block 2.
>>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
>>>    1 file changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> index f8c2269..e7e2e52 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>> @@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>>>    	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
>>>    	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>>>    
>>> -	port = intel_dsi_seq_port_to_port(seq_port);
>>> +	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>>> +	 * Now  the sequence of DSI single link on Port A and Port C will based
>>> +	 * on the DVO port from VBT block 2.
>>> +	 */
>>> +	if (intel_dsi->ports == (1 << PORT_C))
>>> +		port = PORT_C;
>>> +	else
>>> +		port = intel_dsi_seq_port_to_port(seq_port);
>>>    	/* LP or HS mode */
>>>    	intel_dsi->hs = mode;
>>>    
>> Jani,
>>
>> Need your reviewed-by on this patch too.
> Okay, I was confused because there were actually five patches in this
> four patch series! ;)
>
> The *code* is
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> because I understand it, but frankly both the commit message and the
> comment confuse me more.
Thanks Jani. I uploaded the next version of my 1/4 patch over my message 
id only, but sorry for the confusion.

Daniel,
Could you please merge this patch too, got reviewed-by from Jani. Thanks.

With regards,
Gaurav

>
>
>> With regards,
>> Gaurav
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Daniel Vetter]

On Tue, Dec 09, 2014 at 12:30:49PM +0200, Jani Nikula wrote:
> On Tue, 09 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> > On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
> >> For DSI Port A & C, the seq_port value has been set to 0 now in VBT
> >> Now  the sequence of DSI single link on Port A and Port C will based
> >> on the DVO port from VBT block 2.
> >>
> >> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
> >>   1 file changed, 8 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> index f8c2269..e7e2e52 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> @@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
> >>   	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
> >>   	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
> >>   
> >> -	port = intel_dsi_seq_port_to_port(seq_port);
> >> +	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
> >> +	 * Now  the sequence of DSI single link on Port A and Port C will based
> >> +	 * on the DVO port from VBT block 2.
> >> +	 */
> >> +	if (intel_dsi->ports == (1 << PORT_C))
> >> +		port = PORT_C;
> >> +	else
> >> +		port = intel_dsi_seq_port_to_port(seq_port);
> >>   	/* LP or HS mode */
> >>   	intel_dsi->hs = mode;
> >>   
> >
> > Jani,
> >
> > Need your reviewed-by on this patch too.
> 
> Okay, I was confused because there were actually five patches in this
> four patch series! ;)
> 
> The *code* is
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> because I understand it, but frankly both the commit message and the
> comment confuse me more.

Hm, do you have suggestions for a better commit message? Should we just
drop the comment. I agree that the talk about VBT is really confusing and
smells like leftovers from other stuff.

I'll wait with this one until this is resolved. Accurate and clear commit
messages are important.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 2/4] drm/i915: DSI sequence related changes for DSI Port C

[Singh, Gaurav K]

On 12/10/2014 2:50 PM, Daniel Vetter wrote:
> On Tue, Dec 09, 2014 at 12:30:49PM +0200, Jani Nikula wrote:
>> On Tue, 09 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
>>> On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
>>>> For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>>>> Now  the sequence of DSI single link on Port A and Port C will based
>>>> on the DVO port from VBT block 2.
>>>>
>>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    9 ++++++++-
>>>>    1 file changed, 8 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> index f8c2269..e7e2e52 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>>>> @@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
>>>>    	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
>>>>    	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
>>>>    
>>>> -	port = intel_dsi_seq_port_to_port(seq_port);
>>>> +	/* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
>>>> +	 * Now  the sequence of DSI single link on Port A and Port C will based
>>>> +	 * on the DVO port from VBT block 2.
>>>> +	 */
>>>> +	if (intel_dsi->ports == (1 << PORT_C))
>>>> +		port = PORT_C;
>>>> +	else
>>>> +		port = intel_dsi_seq_port_to_port(seq_port);
>>>>    	/* LP or HS mode */
>>>>    	intel_dsi->hs = mode;
>>>>    
>>> Jani,
>>>
>>> Need your reviewed-by on this patch too.
>> Okay, I was confused because there were actually five patches in this
>> four patch series! ;)
>>
>> The *code* is
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>> because I understand it, but frankly both the commit message and the
>> comment confuse me more.
> Hm, do you have suggestions for a better commit message? Should we just
> drop the comment. I agree that the talk about VBT is really confusing and
> smells like leftovers from other stuff.
>
> I'll wait with this one until this is resolved. Accurate and clear commit
> messages are important.
> -Daniel
Jani,

How is the below commit message?

 From now on for both DSI Ports A & C, the seq_port value has been set to 0.
seq_port value is parsed from Sequence block#53 of VBT.So, for packets that needs to be
read/write for DSI single link on Port A and Port C will based on the DVO port from VBT block 2.

With regards,
Gaurav
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[PATCH 2/4] drm/i915: Changes related to the sequence port no for

[Gaurav K Singh]

From now on for both DSI Ports A & C, the seq_port value has been
set to 0. seq_port value is parsed from Sequence block#53 of VBT.
So, for packets that needs to be read/write for DSI single link on
Port A and Port C will now be based on the DVO port from VBT block 2,
instead of seq_port.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269..5493aef 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,15 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
 	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
 	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 
-	port = intel_dsi_seq_port_to_port(seq_port);
+	/* For DSI single link on Port A & C, the seq_port value which is
+	 * parsed from Sequence Block#53 of VBT has been set to 0
+	 * Now, read/write of packets for the DSI single link on Port A and
+	 * Port C will based on the DVO port from VBT block 2.
+	 */
+	if (intel_dsi->ports == (1 << PORT_C))
+		port = PORT_C;
+	else
+		port = intel_dsi_seq_port_to_port(seq_port);
 	/* LP or HS mode */
 	intel_dsi->hs = mode;
 
-- 
1.7.9.5

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Re: [PATCH 2/4] drm/i915: Changes related to the sequence port no for

[Daniel Vetter]

On Wed, Dec 10, 2014 at 10:07:40PM +0530, Gaurav K Singh wrote:
> From now on for both DSI Ports A & C, the seq_port value has been
> set to 0. seq_port value is parsed from Sequence block#53 of VBT.
> So, for packets that needs to be read/write for DSI single link on
> Port A and Port C will now be based on the DVO port from VBT block 2,
> instead of seq_port.
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch.
-Daniel
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Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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