From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Yu Zhang <yu.c.zhang@linux.intel.com>, Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 0/8] Add enlightenments for vGPU
Date: Thu, 11 Dec 2014 17:03:46 +0000 [thread overview]
Message-ID: <5489CE72.6010009@linux.intel.com> (raw)
In-Reply-To: <1415880169-7656-1-git-send-email-yu.c.zhang@linux.intel.com>
Hi,
I'll try to do the detailed review of your series in the following few
days. I might ask some questions on the design also to help me
understand the bigger picture.
First thing, I see that patches are checkpatch.pl clean, apart when run
in strict mode. I think Daniel prefers "--strict" nowadays, at least I
needed to fix up those in my patches so you should probably do the same.
On 11/13/2014 12:02 PM, Yu Zhang wrote:
[snip]
> The primary change introduced here is to implement so-called
> "address space ballooning" technique. XenGT partitions global
> graphics memory among multiple VMs, so each VM can directly
> access a portion of the memory w/o hypervisor's intervention,
> e.g. filling textures or queuing commands. However w/ the
> partitioning an unmodified i915 driver would assume a smaller
> graphics memory starting from address ZERO, so requires XenGT
> core module (vgt) to translate the graphics address between
> 'guest view' and 'host view', for all registers and command
> opcodes which contain a graphics memory address. To reduce the
> complexity, XenGT introduces "address space ballooning", by
> telling the exact partitioning knowledge to each guest i915
> driver, which then reserves and prevents non-allocated portions
> from allocation. Then vgt module only needs to scan and validate
> graphics addresses w/o complexity of translation.
I couldn't figure this out - is there any hardware protection in there,
or a virtual i915 instance could access memory outside it's area if
there was a security bug/exploit in the driver, or the balloon was
incorrectly set up?
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-12-11 17:04 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-13 12:02 [PATCH v3 0/8] Add enlightenments for vGPU Yu Zhang
2014-11-13 12:02 ` [PATCH v3 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g Yu Zhang
2014-12-11 17:33 ` Tvrtko Ursulin
2014-12-15 8:12 ` Daniel Vetter
2014-12-16 12:51 ` Yu, Zhang
2014-12-16 13:19 ` Tvrtko Ursulin
2014-12-17 2:49 ` Yu, Zhang
2014-12-17 5:04 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 2/8] drm/i915: Adds graphic address space ballooning logic Yu Zhang
2014-11-14 10:16 ` Daniel Vetter
2014-11-14 12:00 ` Yu, Zhang
2014-12-12 13:00 ` Tvrtko Ursulin
2014-12-16 13:22 ` Yu, Zhang
2014-12-16 13:41 ` Tvrtko Ursulin
2014-12-16 14:39 ` Gerd Hoffmann
2014-12-16 15:15 ` Tvrtko Ursulin
2014-12-17 3:10 ` Yu, Zhang
2014-12-17 5:20 ` Tian, Kevin
2014-12-17 10:06 ` Tvrtko Ursulin
2014-12-17 5:57 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver Yu Zhang
2014-12-12 13:07 ` Tvrtko Ursulin
2014-12-16 13:32 ` Yu, Zhang
2014-12-16 13:44 ` Tvrtko Ursulin
2014-12-16 14:41 ` Gerd Hoffmann
2014-12-16 15:01 ` Tvrtko Ursulin
2014-12-17 7:33 ` Gerd Hoffmann
2014-12-17 9:59 ` Tvrtko Ursulin
2014-12-17 11:06 ` Gerd Hoffmann
2014-12-17 11:25 ` Yu, Zhang
2014-12-17 11:50 ` Tvrtko Ursulin
2014-12-17 17:10 ` Daniel Vetter
2014-12-17 17:11 ` Daniel Vetter
2014-12-18 0:36 ` Tian, Kevin
2014-12-18 8:08 ` Daniel Vetter
2014-12-18 8:39 ` Tian, Kevin
2014-12-17 4:58 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 4/8] drm/i915: Disable framebuffer compression for i915 driver in VM Yu Zhang
2014-12-12 13:13 ` Tvrtko Ursulin
2014-12-17 3:15 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 5/8] drm/i915: Add the display switch logic for vGPU in i915 driver Yu Zhang
2014-12-12 13:18 ` Tvrtko Ursulin
2014-12-15 8:16 ` Daniel Vetter
2014-12-17 3:17 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 6/8] drm/i915: Disable power management for i915 driver in VM Yu Zhang
2014-12-12 13:27 ` Tvrtko Ursulin
2014-12-17 3:25 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 7/8] drm/i915: Create vGPU specific write MMIO to reduce traps Yu Zhang
2014-12-12 13:31 ` Tvrtko Ursulin
2014-12-17 7:28 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled Yu Zhang
2014-11-14 0:29 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if shuang.he
2014-12-12 13:37 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled Tvrtko Ursulin
2014-11-14 10:17 ` [PATCH v3 0/8] Add enlightenments for vGPU Daniel Vetter
2014-11-14 12:01 ` Yu, Zhang
2014-12-11 17:03 ` Tvrtko Ursulin [this message]
2014-12-15 8:18 ` Daniel Vetter
2014-12-15 9:16 ` Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5489CE72.6010009@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=Intel-gfx@lists.freedesktop.org \
--cc=yu.c.zhang@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox