Re: [PATCH 03/10] drm/i915: Updating assorted register and status page definitions

Daniel Vetter
2014-12-10T10:39:36Z

On Tue, Dec 09, 2014 at 12:59:06PM +0000, John.C.Harrison@Intel.com wrote:
> From: Dave Gordon <david.s.gordon@intel.com>
>
> Added various definitions that will be useful for the scheduler in general and
> pre-emptive context switching in particular.
>
> Change-Id: Ica805b94160426def51f5d520f5ce51c60864a98
> For: VIZ-1587
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 40 +++++++++++++++++++++++++++++--
> 2 files changed, 67 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 869e5ae..6169720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -216,6 +216,10 @@
> #define MI_GLOBAL_GTT (1<<22)
>
> #define MI_NOOP MI_INSTR(0, 0)
> +#define MI_NOOP_WRITE_ID (1<<22)
> +#define MI_NOOP_ID_MASK ((1<<22) - 1)
> +#define MI_NOOP_MID(id) ((id) & MI_NOOP_ID_MASK)
> +#define MI_NOOP_WITH_ID(id) MI_INSTR(0, MI_NOOP_WRITE_ID|MI_NOOP_MID(id))
> #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
> #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
> #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
> @@ -233,6 +237,7 @@
> #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
> #define MI_ARB_ENABLE (1<<0)
> #define MI_ARB_DISABLE (0<<0)
> +#define MI_ARB_CHECK MI_INSTR(0x05, 0)
> #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
> #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
> #define MI_SUSPEND_FLUSH_EN (1<<0)
> @@ -281,6 +286,8 @@
> #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
> #define MI_SEMAPHORE_SYNC_MASK (3<<16)
> #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
> +#define MI_CONTEXT_ADDR_MASK ((~0)<<12)
> +#define MI_SET_CONTEXT_FLAG_MASK ((1<<12)-1)
> #define MI_MM_SPACE_GTT (1<<8)
> #define MI_MM_SPACE_PHYSICAL (0<<8)
> #define MI_SAVE_EXT_STATE_EN (1<<3)
> @@ -298,6 +305,10 @@
> #define MI_USE_GGTT (1 << 22) /* g4x+ */
> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
> #define MI_STORE_DWORD_INDEX_SHIFT 2
> +#define MI_STORE_REG_MEM MI_INSTR(0x24, 1)
> +#define MI_STORE_REG_MEM_GTT (1 << 22)
> +#define MI_STORE_REG_MEM_PREDICATE (1 << 21)
> +
> /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
> * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
> * simply ignores the register load under certain conditions.
> @@ -312,7 +323,10 @@
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> +#define MI_FLUSH_DW_OP_NONE (0<<14)
> #define MI_FLUSH_DW_OP_STOREDW (1<<14)
> +#define MI_FLUSH_DW_OP_RSVD (2<<14)
> +#define MI_FLUSH_DW_OP_STAMP (3<<14)
> #define MI_FLUSH_DW_OP_MASK (3<<14)
> #define MI_FLUSH_DW_NOTIFY (1<<8)
> #define MI_INVALIDATE_BSD (1<<7)
> @@ -1119,6 +1133,19 @@ enum punit_power_well {
> #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
> #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
> #define GEN6_NOSYNC 0
> +
> +/*
> + * Premption-related registers
> + */
> +#define RING_UHPTR(base) ((base)+0x134)
> +#define UHPTR_GFX_ADDR_ALIGN (0x7)
> +#define UHPTR_VALID (0x1)
> +#define RING_PREEMPT_ADDR 0x0214c
> +#define PREEMPT_BATCH_LEVEL_MASK (0x3)
> +#define BB_PREEMPT_ADDR 0x02148
> +#define SBB_PREEMPT_ADDR 0x0213c
> +#define RS_PREEMPT_STATUS 0x0215c
> +
> #define RING_MAX_IDLE(base) ((base)+0x54)
> #define RING_HWS_PGA(base) ((base)+0x80)
> #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
> @@ -5917,7 +5944,8 @@ enum punit_power_well {
> #define VLV_SPAREG2H 0xA194
>
> #define GTFIFODBG 0x120000
> -#define GT_FIFO_SBDROPERR (1<<6)
> +#define GT_FIFO_CPU_ERROR_MASK 0xf
> +#define GT_FIFO_SDDROPERR (1<<6)
> #define GT_FIFO_BLOBDROPERR (1<<5)
> #define GT_FIFO_SB_READ_ABORTERR (1<<4)
> #define GT_FIFO_DROPERR (1<<3)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2e0fa7b..f15fc46 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -47,6 +47,12 @@ struct intel_hw_status_page {
> #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
> #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
>
> +#define I915_READ_UHPTR(ring) \
> + I915_READ(RING_UHPTR((ring)->mmio_base))
> +#define I915_WRITE_UHPTR(ring, val) \
> + I915_WRITE(RING_UHPTR((ring)->mmio_base), val)
> +#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
> +
> /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
> * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
> */
> @@ -377,10 +383,40 @@ intel_write_status_page(struct intel_engine_cs *ring,
> * 0x1f: Last written status offset. (GM45)
> *
> * The area from dword 0x20 to 0x3ff is available for driver usage.
> + *
> + * Note: in general the allocation of these indices is arbitrary, as long
> + * as they are all unique. But a few of them are used with instructions that
> + * have specific alignment requirements, those particular indices must be
> + * chosen carefully to meet those requirements. The list below shows the
> + * currently-known alignment requirements:
> + *
> + * I915_GEM_SCRATCH_INDEX must be EVEN
> */
> #define I915_GEM_HWS_INDEX 0x20
> -#define I915_GEM_HWS_SCRATCH_INDEX 0x30
> -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
> +
> +#define I915_GEM_HWS_SCRATCH_INDEX 0x24 /* QWord */
> +#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
> +
> +/*
> + * Tracking; these are updated by the GPU at the beginning and/or end of every
> + * batch. One pair for regular buffers, the other for preemptive ones.
> + */
> +#define I915_BATCH_DONE_SEQNO 0x30 /* Completed batch seqno */
> +#define I915_BATCH_ACTIVE_SEQNO 0x31 /* In progress batch seqno */
> +#define I915_PREEMPTIVE_DONE_SEQNO 0x32 /* Completed preemptive batch */
> +#define I915_PREEMPTIVE_ACTIVE_SEQNO 0x33 /* In progress preemptive batch */

This are software define and currently not yet used I think. Imo better to
add them together with the scheduler code that uses them. Splitting out
#define patches only makes sense if they can be reviewed separately (e.g.
registers with Bspec). Just adding software stuff (structs, enums, offsets
not enforced by hw) should be added with the actual code using it.

> +
> +/*
> + * Preemption; these are used by the GPU to save important registers
> + */
> +#define I915_SAVE_PREEMPTED_RING_PTR 0x34 /* HEAD before preemption */
> +#define I915_SAVE_PREEMPTED_BB_PTR 0x35 /* BB ptr before preemption */
> +#define I915_SAVE_PREEMPTED_SBB_PTR 0x36 /* SBB before preemption */
> +#define I915_SAVE_PREEMPTED_UHPTR 0x37 /* UHPTR after preemption */
> +#define I915_SAVE_PREEMPTED_HEAD 0x38 /* HEAD after preemption */
> +#define I915_SAVE_PREEMPTED_TAIL 0x39 /* TAIL after preemption */
> +#define I915_SAVE_PREEMPTED_STATUS 0x3A /* RS preemption status */
> +#define I915_SAVE_PREEMPTED_NOPID 0x3B /* Dummy */

I guess this is hardcoded in hw? In that case a HWS instead of I915 prefix
sounds better to me to make it clear this is not something i915/gem code
invented. Also comment should state whether this is execlist or gen8+ or
something like that.
-Daniel

>
> void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
> int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
> --
> 1.7.9.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch