Re: [PATCH 04/10] drm/i915: FIFO space query code refactor

Daniel Vetter
2014-12-10T10:40:56Z

On Tue, Dec 09, 2014 at 12:59:07PM +0000, John.C.Harrison@Intel.com wrote:
> From: Dave Gordon <david.s.gordon@intel.com>
>
> When querying the GTFIFOCTL register to check the FIFO space, the read value
> must be masked. The operation is repeated explicitly in several places. This
> change refactors the read-and-mask code into a function call.
>
> Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>

Looks like an unrelated patch and probably collides with Mika's forcewake
refactoring. Please rebase on top of that series if still needed.
-Daniel

> ---
> drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++-------
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 46de8d7..4021831 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -47,6 +47,13 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv)
> "Device suspended\n");
> }
>
> +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
> +{
> + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
> +
> + return count & GT_FIFO_FREE_ENTRIES_MASK;
> +}
> +
> static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
> {
> /* w/a for a sporadic read returning 0 by waiting for the GT
> @@ -154,16 +161,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
> /* On VLV, FIFO will be shared by both SW and HW.
> * So, we need to read the FREE_ENTRIES everytime */
> if (IS_VALLEYVIEW(dev_priv->dev))
> - dev_priv->uncore.fifo_count =
> - __raw_i915_read32(dev_priv, GTFIFOCTL) &
> - GT_FIFO_FREE_ENTRIES_MASK;
> + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
>
> if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
> int loop = 500;
> - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
> + u32 fifo = fifo_free_entries(dev_priv);
> +
> while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
> udelay(10);
> - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
> + fifo = fifo_free_entries(dev_priv);
> }
> if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
> ++ret;
> @@ -505,8 +511,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
>
> if (IS_GEN6(dev) || IS_GEN7(dev))
> dev_priv->uncore.fifo_count =
> - __raw_i915_read32(dev_priv, GTFIFOCTL) &
> - GT_FIFO_FREE_ENTRIES_MASK;
> + fifo_free_entries(dev_priv);
> }
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> --
> 1.7.9.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch