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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Chris Wilson <chris@chris-wilson.co.uk>,
	Ben Widawsky <benjamin.widawsky@intel.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	Intel GFX <intel-gfx@lists.freedesktop.org>,
	Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/cache: Try to be smarter about clflushing on x86
Date: Sun, 14 Dec 2014 20:06:20 -0800	[thread overview]
Message-ID: <548E5E3C.4060900@virtuousgeek.org> (raw)
In-Reply-To: <20141214125941.GB32601@nuc-i3427.alporthouse.com>

On 12/14/2014 4:59 AM, Chris Wilson wrote:
> One of the things wbinvd is considered evil for is that it blocks the
> CPU for an indeterminate amount of time - upsetting latency critcial
> aspects of the OS. For example, the x86/mm has similar code to use
> wbinvd for large clflushes that caused a bit of controversy with RT:
>
> http://linux-kernel.2935.n7.nabble.com/PATCH-x86-Use-clflush-instead-of-wbinvd-whenever-possible-when-changing-mapping-td493751.html
>
> and also the use of wbinvd in the nvidia driver has also been noted as
> evil by RT folks.
>
> However as the wbinvd still exists, it can't be all that bad...

Yeah there are definitely tradeoffs here.  In this particular case, 
we're trying to flush out a ~140M object on every frame, which just 
seems silly.

There's definitely room for optimization in Mesa too; avoiding a mapping 
that marks a large bo as dirty would be good, but if we improve the 
kernel in this area, even sloppy apps and existing binaries will speed up.

Maybe we could apply this only on !llc systems or something?  I wonder 
how much wbinvd performance varies across microarchitectures; maybe 
Thomas's issue isn't really relevant anymore (at least one can hope).

When digging into this, I found that an optimization to remove the IPI 
for wbinvd was clobbered during a merge; maybe that should be 
resurrected too.  Surely a single, global wbinvd is sufficient; we don't 
need to do n_cpus^2 wbinvd + the associated invalidation bus signals here...

Alternately, we could insert some delays into this path just to make it 
extra clear to userspace that they really shouldn't be hitting this in 
the common case (and provide some additional interfaces to let them 
avoid it by allowing flushing and dirty management in userspace).

Jesse
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  reply	other threads:[~2014-12-15  4:06 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1418526504-26316-1-git-send-email-benjamin.widawsky@intel.com>
2014-12-14  3:08 ` [PATCH 1/4] drm/cache: Use wbinvd helpers Ben Widawsky
2014-12-14 12:43   ` Chris Wilson
2014-12-15  7:49     ` Daniel Vetter
2014-12-15 20:26   ` [PATCH] [v2] " Ben Widawsky
2014-12-16  2:26     ` shuang.he
2014-12-16  7:56     ` Daniel Vetter
2014-12-14  3:08 ` [PATCH 2/4] drm/cache: Try to be smarter about clflushing on x86 Ben Widawsky
2014-12-14  4:15   ` Matt Turner
2014-12-15 22:07     ` Ben Widawsky
2014-12-14 12:59   ` [Intel-gfx] " Chris Wilson
2014-12-15  4:06     ` Jesse Barnes [this message]
2014-12-15 19:54       ` Ben Widawsky
2014-12-14  3:08 ` [PATCH 3/4] drm/cache: Return what type of cache flush occurred Ben Widawsky
2014-12-14  3:08 ` [PATCH 4/4] drm/i915: Opportunistically reduce flushing at execbuf Ben Widawsky
2014-12-14  9:35   ` shuang.he
2014-12-14 13:12   ` [Intel-gfx] " Ville Syrjälä
2014-12-14 23:37     ` Ben Widawsky
2014-12-15  7:55       ` [Intel-gfx] " Daniel Vetter
2014-12-15  8:20         ` Chris Wilson
2014-12-15 19:56           ` Ben Widawsky
2014-12-15 20:39             ` Chris Wilson
2014-12-15 21:06               ` [Intel-gfx] " Ben Widawsky
2014-12-16  7:57                 ` Chris Wilson
2014-12-16 19:38                   ` Ben Widawsky

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