From: "Yu, Zhang" <yu.c.zhang@linux.intel.com>
To: Gerd Hoffmann <kraxel@redhat.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver
Date: Wed, 17 Dec 2014 19:25:31 +0800 [thread overview]
Message-ID: <5491682B.9050706@linux.intel.com> (raw)
In-Reply-To: <1418814392.18828.18.camel@nilsson.home.kraxel.org>
On 12/17/2014 7:06 PM, Gerd Hoffmann wrote:
> Hi,
>
>>> It's not possible to allow guests direct access to the fence registers
>>> though. And if every fence register access traps into the hypervisor
>>> anyway the hypervisor can easily map the guest virtual fence to host
>>> physical fence, so there is no need to tell the guest which fences it
>>> owns, the number of fences is enough.
>>
>> That exactly is the part I don't understand - if it is not required to
>> tell the guest which fences it owns, why it is required to say how many?
>
> There is a fixed assignment of fences to guests, so it's a fixed number.
> But as the hypervisor is involved in any fence access anyway there is no
> need for the guest to know which of the fences it owns, the hypervisor
> can remap that transparently for the guest, without performance penalty.
Thanks Gerd. Exactly.
Although fence registers are parititioned to vGPU, it is not necessary
for a vGPU to know the physical mmio addresses of the allocated fence
registers.
For example, vGPU 1 with fence size 4 can access the fence registers
from 0x100000-10001f; at the same time, vGPU 2 with fence size 8 can
access the fence registers from 0x100000-0x10003f. Although this seems
conflicting, it does not matter. Because these mmio addresses are all
supposed to be trapped in the host side, which will keep a record of the
real fence offset of different vGPUs(say 0 for vGPU 1 and 4 for vGPU 2),
and then does the remapping. Therefore, the physical operations on the
fence register will be performed by host code on different ones(say,
0x100000-10001fh for vGPU 1 and 0x100020-0x10005f for vGPU 2).
>
>> With this scheme it could be one guest wants more and can't get them
>> even if no one else is using any. If not limited they could be
>> dynamically allocated by the hypervisor, no?
>
> Should be possible as extension, but I think[1] for now the goal is to
> stay as close as possible to physical hardware, where you can't
> dynamically allocate fences in the first place.
Yes. By now we have feature to configure the fence numbers for a vGPU.
But we do not support the dynamical allocations.
>
> cheers,
> Gerd
>
> [1] Not being deeply involved into vgpu development, just reviewing
> the bits with some kvm background.
>
>
>
>
Thanks
Yu
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next prev parent reply other threads:[~2014-12-17 11:27 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-13 12:02 [PATCH v3 0/8] Add enlightenments for vGPU Yu Zhang
2014-11-13 12:02 ` [PATCH v3 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g Yu Zhang
2014-12-11 17:33 ` Tvrtko Ursulin
2014-12-15 8:12 ` Daniel Vetter
2014-12-16 12:51 ` Yu, Zhang
2014-12-16 13:19 ` Tvrtko Ursulin
2014-12-17 2:49 ` Yu, Zhang
2014-12-17 5:04 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 2/8] drm/i915: Adds graphic address space ballooning logic Yu Zhang
2014-11-14 10:16 ` Daniel Vetter
2014-11-14 12:00 ` Yu, Zhang
2014-12-12 13:00 ` Tvrtko Ursulin
2014-12-16 13:22 ` Yu, Zhang
2014-12-16 13:41 ` Tvrtko Ursulin
2014-12-16 14:39 ` Gerd Hoffmann
2014-12-16 15:15 ` Tvrtko Ursulin
2014-12-17 3:10 ` Yu, Zhang
2014-12-17 5:20 ` Tian, Kevin
2014-12-17 10:06 ` Tvrtko Ursulin
2014-12-17 5:57 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver Yu Zhang
2014-12-12 13:07 ` Tvrtko Ursulin
2014-12-16 13:32 ` Yu, Zhang
2014-12-16 13:44 ` Tvrtko Ursulin
2014-12-16 14:41 ` Gerd Hoffmann
2014-12-16 15:01 ` Tvrtko Ursulin
2014-12-17 7:33 ` Gerd Hoffmann
2014-12-17 9:59 ` Tvrtko Ursulin
2014-12-17 11:06 ` Gerd Hoffmann
2014-12-17 11:25 ` Yu, Zhang [this message]
2014-12-17 11:50 ` Tvrtko Ursulin
2014-12-17 17:10 ` Daniel Vetter
2014-12-17 17:11 ` Daniel Vetter
2014-12-18 0:36 ` Tian, Kevin
2014-12-18 8:08 ` Daniel Vetter
2014-12-18 8:39 ` Tian, Kevin
2014-12-17 4:58 ` Tian, Kevin
2014-11-13 12:02 ` [PATCH v3 4/8] drm/i915: Disable framebuffer compression for i915 driver in VM Yu Zhang
2014-12-12 13:13 ` Tvrtko Ursulin
2014-12-17 3:15 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 5/8] drm/i915: Add the display switch logic for vGPU in i915 driver Yu Zhang
2014-12-12 13:18 ` Tvrtko Ursulin
2014-12-15 8:16 ` Daniel Vetter
2014-12-17 3:17 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 6/8] drm/i915: Disable power management for i915 driver in VM Yu Zhang
2014-12-12 13:27 ` Tvrtko Ursulin
2014-12-17 3:25 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 7/8] drm/i915: Create vGPU specific write MMIO to reduce traps Yu Zhang
2014-12-12 13:31 ` Tvrtko Ursulin
2014-12-17 7:28 ` Yu, Zhang
2014-11-13 12:02 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled Yu Zhang
2014-11-14 0:29 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if shuang.he
2014-12-12 13:37 ` [PATCH v3 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled Tvrtko Ursulin
2014-11-14 10:17 ` [PATCH v3 0/8] Add enlightenments for vGPU Daniel Vetter
2014-11-14 12:01 ` Yu, Zhang
2014-12-11 17:03 ` Tvrtko Ursulin
2014-12-15 8:18 ` Daniel Vetter
2014-12-15 9:16 ` Jani Nikula
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