* [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
@ 2014-12-10 14:08 Gaurav K Singh
2014-12-10 20:04 ` shuang.he
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Gaurav K Singh @ 2014-12-10 14:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Shobhit Kumar
For CHT changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 43 ++++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..9236b66 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
#endif
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
+ u32 dsi_clk, struct dsi_mnp *dsi_mnp)
{
u32 m, n, p;
u32 ref_clk;
@@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
u32 calc_m;
u32 calc_p;
u32 m_seed;
+ u32 m_start;
+ u32 m_limit;
+ u32 n_limit;
+ u32 p_limit;
/* dsi_clk is expected in KHZ */
if (dsi_clk < 300000 || dsi_clk > 1150000) {
@@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
return -ECHRNG;
}
- ref_clk = 25000;
+ if (IS_CHERRYVIEW(dev_priv->dev)) {
+ ref_clk = 100000;
+ m_start = 70;
+ m_limit = 96;
+ n_limit = 4;
+ p_limit = 6;
+ } else if (IS_VALLEYVIEW(dev_priv->dev)) {
+ ref_clk = 25000;
+ m_start = 62;
+ m_limit = 92;
+ n_limit = 1;
+ p_limit = 6;
+ } else {
+ DRM_ERROR("Unsupported device\n");
+ return -ENODEV;
+ }
target_dsi_clk = dsi_clk;
error = 0xFFFFFFFF;
tmp_error = 0xFFFFFFFF;
calc_m = 0;
calc_p = 0;
- for (m = 62; m <= 92; m++) {
- for (p = 2; p <= 6; p++) {
+ for (m = m_start; m <= m_limit; m++) {
+ for (p = 2; p <= p_limit; p++) {
/* Find the optimal m and p divisors
with minimal error +/- the required clock */
- calc_dsi_clk = (m * ref_clk) / p;
+ calc_dsi_clk = (m * ref_clk) / (p * n_limit);
if (calc_dsi_clk == target_dsi_clk) {
calc_m = m;
calc_p = p;
@@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
}
m_seed = lfsr_converts[calc_m - 62];
- n = 1;
+ n = n_limit;
dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
- dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
- m_seed << DSI_PLL_M1_DIV_SHIFT;
-
+ if (IS_CHERRYVIEW(dev_priv->dev))
+ dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
+ m_seed << DSI_PLL_M1_DIV_SHIFT;
+ else
+ dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+ m_seed << DSI_PLL_M1_DIV_SHIFT;
return 0;
}
@@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count);
- ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
+ ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
return;
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2014-12-10 14:08 [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT Gaurav K Singh
@ 2014-12-10 20:04 ` shuang.he
2014-12-12 7:33 ` Singh, Gaurav K
2014-12-19 9:33 ` Jani Nikula
2 siblings, 0 replies; 8+ messages in thread
From: shuang.he @ 2014-12-10 20:04 UTC (permalink / raw)
To: shuang.he, intel-gfx, gaurav.k.singh
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 364/364 363/364
ILK +1-3 364/366 362/366
SNB 448/450 448/450
IVB -1 497/498 496/498
BYT 289/289 289/289
HSW 563/564 563/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fd_exhaustion PASS(2, M23) FAIL(1, M23)
*ILK igt_kms_flip_flip-vs-dpms-interruptible PASS(5, M26) DMESG_WARN(1, M26)
ILK igt_kms_flip_flip-vs-panning DMESG_WARN(1, M26)PASS(7, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_flip-vs-rmfb-interruptible NSPT(1, M26)PASS(4, M26) DMESG_WARN(1, M26)
ILK igt_kms_flip_wf_vblank-ts-check DMESG_WARN(3, M26)PASS(17, M26M37) PASS(1, M26)
*IVB igt_kms_cursor_crc_cursor-256x256-sliding PASS(3, M4M21) DMESG_WARN(1, M21)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2014-12-10 14:08 [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT Gaurav K Singh
2014-12-10 20:04 ` shuang.he
@ 2014-12-12 7:33 ` Singh, Gaurav K
2015-01-14 9:31 ` Singh, Gaurav K
2014-12-19 9:33 ` Jani Nikula
2 siblings, 1 reply; 8+ messages in thread
From: Singh, Gaurav K @ 2014-12-12 7:33 UTC (permalink / raw)
To: intel-gfx, jani.nikula; +Cc: Shobhit Kumar
On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
> For CHT changes are required for calculating the correct m,n & p with
> minimal error +/- for the required DSI clock, so that the correct dividor
> & ctrl values are written in cck regs for DSI. This patch has been tested
> on CHT RVP with 1200 x 1920 panel.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 43 ++++++++++++++++++++++++++--------
> 1 file changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 8957f10..9236b66 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>
> #endif
>
> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
> + u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> {
> u32 m, n, p;
> u32 ref_clk;
> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> u32 calc_m;
> u32 calc_p;
> u32 m_seed;
> + u32 m_start;
> + u32 m_limit;
> + u32 n_limit;
> + u32 p_limit;
>
> /* dsi_clk is expected in KHZ */
> if (dsi_clk < 300000 || dsi_clk > 1150000) {
> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> return -ECHRNG;
> }
>
> - ref_clk = 25000;
> + if (IS_CHERRYVIEW(dev_priv->dev)) {
> + ref_clk = 100000;
> + m_start = 70;
> + m_limit = 96;
> + n_limit = 4;
> + p_limit = 6;
> + } else if (IS_VALLEYVIEW(dev_priv->dev)) {
> + ref_clk = 25000;
> + m_start = 62;
> + m_limit = 92;
> + n_limit = 1;
> + p_limit = 6;
> + } else {
> + DRM_ERROR("Unsupported device\n");
> + return -ENODEV;
> + }
> target_dsi_clk = dsi_clk;
> error = 0xFFFFFFFF;
> tmp_error = 0xFFFFFFFF;
> calc_m = 0;
> calc_p = 0;
>
> - for (m = 62; m <= 92; m++) {
> - for (p = 2; p <= 6; p++) {
> + for (m = m_start; m <= m_limit; m++) {
> + for (p = 2; p <= p_limit; p++) {
> /* Find the optimal m and p divisors
> with minimal error +/- the required clock */
> - calc_dsi_clk = (m * ref_clk) / p;
> + calc_dsi_clk = (m * ref_clk) / (p * n_limit);
> if (calc_dsi_clk == target_dsi_clk) {
> calc_m = m;
> calc_p = p;
> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> }
>
> m_seed = lfsr_converts[calc_m - 62];
> - n = 1;
> + n = n_limit;
> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
> - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> - m_seed << DSI_PLL_M1_DIV_SHIFT;
> -
> + if (IS_CHERRYVIEW(dev_priv->dev))
> + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> + else
> + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> return 0;
> }
>
> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> intel_dsi->lane_count);
>
> - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
> + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
> if (ret) {
> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> return;
Hi Jani,
Could you please review this patch?
With regards,
Gaurav
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2014-12-12 7:33 ` Singh, Gaurav K
@ 2015-01-14 9:31 ` Singh, Gaurav K
2015-01-15 11:25 ` Jani Nikula
0 siblings, 1 reply; 8+ messages in thread
From: Singh, Gaurav K @ 2015-01-14 9:31 UTC (permalink / raw)
To: intel-gfx, jani.nikula, jani.nikula; +Cc: Shobhit Kumar
On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
>
> On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
>> For CHT changes are required for calculating the correct m,n & p with
>> minimal error +/- for the required DSI clock, so that the correct
>> dividor
>> & ctrl values are written in cck regs for DSI. This patch has been
>> tested
>> on CHT RVP with 1200 x 1920 panel.
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 43
>> ++++++++++++++++++++++++++--------
>> 1 file changed, 33 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index 8957f10..9236b66 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int
>> pixel_format, int lane_count)
>> #endif
>> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
>> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
>> + u32 dsi_clk, struct dsi_mnp *dsi_mnp)
>> {
>> u32 m, n, p;
>> u32 ref_clk;
>> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>> dsi_mnp *dsi_mnp)
>> u32 calc_m;
>> u32 calc_p;
>> u32 m_seed;
>> + u32 m_start;
>> + u32 m_limit;
>> + u32 n_limit;
>> + u32 p_limit;
>> /* dsi_clk is expected in KHZ */
>> if (dsi_clk < 300000 || dsi_clk > 1150000) {
>> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>> dsi_mnp *dsi_mnp)
>> return -ECHRNG;
>> }
>> - ref_clk = 25000;
>> + if (IS_CHERRYVIEW(dev_priv->dev)) {
>> + ref_clk = 100000;
>> + m_start = 70;
>> + m_limit = 96;
>> + n_limit = 4;
>> + p_limit = 6;
>> + } else if (IS_VALLEYVIEW(dev_priv->dev)) {
>> + ref_clk = 25000;
>> + m_start = 62;
>> + m_limit = 92;
>> + n_limit = 1;
>> + p_limit = 6;
>> + } else {
>> + DRM_ERROR("Unsupported device\n");
>> + return -ENODEV;
>> + }
>> target_dsi_clk = dsi_clk;
>> error = 0xFFFFFFFF;
>> tmp_error = 0xFFFFFFFF;
>> calc_m = 0;
>> calc_p = 0;
>> - for (m = 62; m <= 92; m++) {
>> - for (p = 2; p <= 6; p++) {
>> + for (m = m_start; m <= m_limit; m++) {
>> + for (p = 2; p <= p_limit; p++) {
>> /* Find the optimal m and p divisors
>> with minimal error +/- the required clock */
>> - calc_dsi_clk = (m * ref_clk) / p;
>> + calc_dsi_clk = (m * ref_clk) / (p * n_limit);
>> if (calc_dsi_clk == target_dsi_clk) {
>> calc_m = m;
>> calc_p = p;
>> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>> dsi_mnp *dsi_mnp)
>> }
>> m_seed = lfsr_converts[calc_m - 62];
>> - n = 1;
>> + n = n_limit;
>> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT +
>> calc_p - 2);
>> - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
>> - m_seed << DSI_PLL_M1_DIV_SHIFT;
>> -
>> + if (IS_CHERRYVIEW(dev_priv->dev))
>> + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
>> + else
>> + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
>> return 0;
>> }
>> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct
>> intel_encoder *encoder)
>> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
>> intel_dsi->pixel_format,
>> intel_dsi->lane_count);
>> - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
>> + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
>> if (ret) {
>> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
>> return;
> Hi Jani,
>
> Could you please review this patch?
>
> With regards,
> Gaurav
>
Hi Jani,
Could you please review this patch?
With regards,
Gaurav
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2015-01-14 9:31 ` Singh, Gaurav K
@ 2015-01-15 11:25 ` Jani Nikula
2015-01-17 4:05 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2015-01-15 11:25 UTC (permalink / raw)
To: Singh, Gaurav K, intel-gfx, Daniel Vetter; +Cc: Shobhit Kumar
On Wed, 14 Jan 2015, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
>>
>> On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
>>> For CHT changes are required for calculating the correct m,n & p with
>>> minimal error +/- for the required DSI clock, so that the correct
>>> dividor
>>> & ctrl values are written in cck regs for DSI. This patch has been
>>> tested
>>> on CHT RVP with 1200 x 1920 panel.
>>>
>>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_dsi_pll.c | 43
>>> ++++++++++++++++++++++++++--------
>>> 1 file changed, 33 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> b/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> index 8957f10..9236b66 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int
>>> pixel_format, int lane_count)
>>> #endif
>>> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
>>> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
>>> + u32 dsi_clk, struct dsi_mnp *dsi_mnp)
>>> {
>>> u32 m, n, p;
>>> u32 ref_clk;
>>> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>>> dsi_mnp *dsi_mnp)
>>> u32 calc_m;
>>> u32 calc_p;
>>> u32 m_seed;
>>> + u32 m_start;
>>> + u32 m_limit;
>>> + u32 n_limit;
>>> + u32 p_limit;
>>> /* dsi_clk is expected in KHZ */
>>> if (dsi_clk < 300000 || dsi_clk > 1150000) {
>>> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>>> dsi_mnp *dsi_mnp)
>>> return -ECHRNG;
>>> }
>>> - ref_clk = 25000;
>>> + if (IS_CHERRYVIEW(dev_priv->dev)) {
>>> + ref_clk = 100000;
>>> + m_start = 70;
>>> + m_limit = 96;
>>> + n_limit = 4;
>>> + p_limit = 6;
>>> + } else if (IS_VALLEYVIEW(dev_priv->dev)) {
>>> + ref_clk = 25000;
>>> + m_start = 62;
>>> + m_limit = 92;
>>> + n_limit = 1;
>>> + p_limit = 6;
>>> + } else {
>>> + DRM_ERROR("Unsupported device\n");
>>> + return -ENODEV;
>>> + }
>>> target_dsi_clk = dsi_clk;
>>> error = 0xFFFFFFFF;
>>> tmp_error = 0xFFFFFFFF;
>>> calc_m = 0;
>>> calc_p = 0;
>>> - for (m = 62; m <= 92; m++) {
>>> - for (p = 2; p <= 6; p++) {
>>> + for (m = m_start; m <= m_limit; m++) {
>>> + for (p = 2; p <= p_limit; p++) {
>>> /* Find the optimal m and p divisors
>>> with minimal error +/- the required clock */
>>> - calc_dsi_clk = (m * ref_clk) / p;
>>> + calc_dsi_clk = (m * ref_clk) / (p * n_limit);
>>> if (calc_dsi_clk == target_dsi_clk) {
>>> calc_m = m;
>>> calc_p = p;
>>> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
>>> dsi_mnp *dsi_mnp)
>>> }
>>> m_seed = lfsr_converts[calc_m - 62];
>>> - n = 1;
>>> + n = n_limit;
>>> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT +
>>> calc_p - 2);
>>> - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
>>> - m_seed << DSI_PLL_M1_DIV_SHIFT;
>>> -
>>> + if (IS_CHERRYVIEW(dev_priv->dev))
>>> + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
>>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
>>> + else
>>> + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
>>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
>>> return 0;
>>> }
>>> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct
>>> intel_encoder *encoder)
>>> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
>>> intel_dsi->pixel_format,
>>> intel_dsi->lane_count);
>>> - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
>>> + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
>>> if (ret) {
>>> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
>>> return;
>> Hi Jani,
>>
>> Could you please review this patch?
>>
>> With regards,
>> Gaurav
>>
> Hi Jani,
>
> Could you please review this patch?
I did, almost a month ago!
http://mid.mail-archive.com/87h9ws2dbz.fsf@intel.com
Daniel, please pick it up.
Gaurav, please let us know if there are any more pending patches that
we've failed to review or apply!
Thanks,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2015-01-15 11:25 ` Jani Nikula
@ 2015-01-17 4:05 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2015-01-17 4:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: Shobhit Kumar, intel-gfx
On Thu, Jan 15, 2015 at 01:25:02PM +0200, Jani Nikula wrote:
> On Wed, 14 Jan 2015, "Singh, Gaurav K" <gaurav.k.singh@intel.com> wrote:
> > On 12/12/2014 1:03 PM, Singh, Gaurav K wrote:
> >>
> >> On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
> >>> For CHT changes are required for calculating the correct m,n & p with
> >>> minimal error +/- for the required DSI clock, so that the correct
> >>> dividor
> >>> & ctrl values are written in cck regs for DSI. This patch has been
> >>> tested
> >>> on CHT RVP with 1200 x 1920 panel.
> >>>
> >>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/intel_dsi_pll.c | 43
> >>> ++++++++++++++++++++++++++--------
> >>> 1 file changed, 33 insertions(+), 10 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> index 8957f10..9236b66 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >>> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int
> >>> pixel_format, int lane_count)
> >>> #endif
> >>> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> >>> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
> >>> + u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> >>> {
> >>> u32 m, n, p;
> >>> u32 ref_clk;
> >>> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> u32 calc_m;
> >>> u32 calc_p;
> >>> u32 m_seed;
> >>> + u32 m_start;
> >>> + u32 m_limit;
> >>> + u32 n_limit;
> >>> + u32 p_limit;
> >>> /* dsi_clk is expected in KHZ */
> >>> if (dsi_clk < 300000 || dsi_clk > 1150000) {
> >>> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> return -ECHRNG;
> >>> }
> >>> - ref_clk = 25000;
> >>> + if (IS_CHERRYVIEW(dev_priv->dev)) {
> >>> + ref_clk = 100000;
> >>> + m_start = 70;
> >>> + m_limit = 96;
> >>> + n_limit = 4;
> >>> + p_limit = 6;
> >>> + } else if (IS_VALLEYVIEW(dev_priv->dev)) {
> >>> + ref_clk = 25000;
> >>> + m_start = 62;
> >>> + m_limit = 92;
> >>> + n_limit = 1;
> >>> + p_limit = 6;
> >>> + } else {
> >>> + DRM_ERROR("Unsupported device\n");
> >>> + return -ENODEV;
> >>> + }
> >>> target_dsi_clk = dsi_clk;
> >>> error = 0xFFFFFFFF;
> >>> tmp_error = 0xFFFFFFFF;
> >>> calc_m = 0;
> >>> calc_p = 0;
> >>> - for (m = 62; m <= 92; m++) {
> >>> - for (p = 2; p <= 6; p++) {
> >>> + for (m = m_start; m <= m_limit; m++) {
> >>> + for (p = 2; p <= p_limit; p++) {
> >>> /* Find the optimal m and p divisors
> >>> with minimal error +/- the required clock */
> >>> - calc_dsi_clk = (m * ref_clk) / p;
> >>> + calc_dsi_clk = (m * ref_clk) / (p * n_limit);
> >>> if (calc_dsi_clk == target_dsi_clk) {
> >>> calc_m = m;
> >>> calc_p = p;
> >>> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct
> >>> dsi_mnp *dsi_mnp)
> >>> }
> >>> m_seed = lfsr_converts[calc_m - 62];
> >>> - n = 1;
> >>> + n = n_limit;
> >>> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT +
> >>> calc_p - 2);
> >>> - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> >>> - m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> -
> >>> + if (IS_CHERRYVIEW(dev_priv->dev))
> >>> + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
> >>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> + else
> >>> + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> >>> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> >>> return 0;
> >>> }
> >>> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct
> >>> intel_encoder *encoder)
> >>> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk,
> >>> intel_dsi->pixel_format,
> >>> intel_dsi->lane_count);
> >>> - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
> >>> + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
> >>> if (ret) {
> >>> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> >>> return;
> >> Hi Jani,
> >>
> >> Could you please review this patch?
> >>
> >> With regards,
> >> Gaurav
> >>
> > Hi Jani,
> >
> > Could you please review this patch?
>
> I did, almost a month ago!
> http://mid.mail-archive.com/87h9ws2dbz.fsf@intel.com
>
> Daniel, please pick it up.
Well, review said "Otherwise r-b: Jani" which I interpreted as "please
apply my suggestions, with that's it's good for a review tag. And since
Gaurav didn't reply I've figured that a revised version is in the works
...
Gaurav, can you please apply the bit of polish plus Jani's r-b tag an
resend?
Thanks, Daniel
>
> Gaurav, please let us know if there are any more pending patches that
> we've failed to review or apply!
>
> Thanks,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
2014-12-10 14:08 [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT Gaurav K Singh
2014-12-10 20:04 ` shuang.he
2014-12-12 7:33 ` Singh, Gaurav K
@ 2014-12-19 9:33 ` Jani Nikula
2 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2014-12-19 9:33 UTC (permalink / raw)
To: Gaurav K Singh, intel-gfx; +Cc: Shobhit Kumar
On Wed, 10 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For CHT changes are required for calculating the correct m,n & p with
> minimal error +/- for the required DSI clock, so that the correct dividor
> & ctrl values are written in cck regs for DSI. This patch has been tested
> on CHT RVP with 1200 x 1920 panel.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 43 ++++++++++++++++++++++++++--------
> 1 file changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 8957f10..9236b66 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>
> #endif
>
> -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> +static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
> + u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> {
> u32 m, n, p;
> u32 ref_clk;
> @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> u32 calc_m;
> u32 calc_p;
> u32 m_seed;
> + u32 m_start;
> + u32 m_limit;
> + u32 n_limit;
> + u32 p_limit;
>
> /* dsi_clk is expected in KHZ */
> if (dsi_clk < 300000 || dsi_clk > 1150000) {
> @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> return -ECHRNG;
> }
>
> - ref_clk = 25000;
> + if (IS_CHERRYVIEW(dev_priv->dev)) {
You can use IS_CHERRYVIEW(dev_priv) directly. It's magic.
> + ref_clk = 100000;
> + m_start = 70;
> + m_limit = 96;
> + n_limit = 4;
> + p_limit = 6;
> + } else if (IS_VALLEYVIEW(dev_priv->dev)) {
Same.
> + ref_clk = 25000;
> + m_start = 62;
> + m_limit = 92;
> + n_limit = 1;
> + p_limit = 6;
> + } else {
> + DRM_ERROR("Unsupported device\n");
> + return -ENODEV;
> + }
We don't really do this kind of else branches, otherwise the driver
would be full of it.
Otherwise,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> target_dsi_clk = dsi_clk;
> error = 0xFFFFFFFF;
> tmp_error = 0xFFFFFFFF;
> calc_m = 0;
> calc_p = 0;
>
> - for (m = 62; m <= 92; m++) {
> - for (p = 2; p <= 6; p++) {
> + for (m = m_start; m <= m_limit; m++) {
> + for (p = 2; p <= p_limit; p++) {
> /* Find the optimal m and p divisors
> with minimal error +/- the required clock */
> - calc_dsi_clk = (m * ref_clk) / p;
> + calc_dsi_clk = (m * ref_clk) / (p * n_limit);
> if (calc_dsi_clk == target_dsi_clk) {
> calc_m = m;
> calc_p = p;
> @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
> }
>
> m_seed = lfsr_converts[calc_m - 62];
> - n = 1;
> + n = n_limit;
> dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
> - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> - m_seed << DSI_PLL_M1_DIV_SHIFT;
> -
> + if (IS_CHERRYVIEW(dev_priv->dev))
> + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> + else
> + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
> + m_seed << DSI_PLL_M1_DIV_SHIFT;
> return 0;
> }
>
> @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
> dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> intel_dsi->lane_count);
>
> - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
> + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
> if (ret) {
> DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
> return;
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT
@ 2015-03-02 10:31 Gaurav K Singh
0 siblings, 0 replies; 8+ messages in thread
From: Gaurav K Singh @ 2015-03-02 10:31 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Shobhit Kumar
On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 43 ++++++++++++++++++++++++++--------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 3622d0b..b7a94c2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
#endif
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
+ u32 dsi_clk, struct dsi_mnp *dsi_mnp)
{
u32 m, n, p;
u32 ref_clk;
@@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
u32 calc_m;
u32 calc_p;
u32 m_seed;
+ u32 m_start;
+ u32 m_limit;
+ u32 n_limit;
+ u32 p_limit;
/* dsi_clk is expected in KHZ */
if (dsi_clk < 300000 || dsi_clk > 1150000) {
@@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
return -ECHRNG;
}
- ref_clk = 25000;
+ if (IS_CHERRYVIEW(dev_priv->dev)) {
+ ref_clk = 100000;
+ m_start = 70;
+ m_limit = 96;
+ n_limit = 4;
+ p_limit = 6;
+ } else if (IS_VALLEYVIEW(dev_priv->dev)) {
+ ref_clk = 25000;
+ m_start = 62;
+ m_limit = 92;
+ n_limit = 1;
+ p_limit = 6;
+ } else {
+ DRM_ERROR("Unsupported device\n");
+ return -ENODEV;
+ }
target_dsi_clk = dsi_clk;
error = 0xFFFFFFFF;
tmp_error = 0xFFFFFFFF;
calc_m = 0;
calc_p = 0;
- for (m = 62; m <= 92; m++) {
- for (p = 2; p <= 6; p++) {
+ for (m = m_start; m <= m_limit; m++) {
+ for (p = 2; p <= p_limit; p++) {
/* Find the optimal m and p divisors
with minimal error +/- the required clock */
- calc_dsi_clk = (m * ref_clk) / p;
+ calc_dsi_clk = (m * ref_clk) / (p * n_limit);
if (calc_dsi_clk == target_dsi_clk) {
calc_m = m;
calc_p = p;
@@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
}
m_seed = lfsr_converts[calc_m - 62];
- n = 1;
+ n = n_limit;
dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
- dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
- m_seed << DSI_PLL_M1_DIV_SHIFT;
-
+ if (IS_CHERRYVIEW(dev_priv->dev))
+ dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
+ m_seed << DSI_PLL_M1_DIV_SHIFT;
+ else
+ dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+ m_seed << DSI_PLL_M1_DIV_SHIFT;
return 0;
}
@@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count);
- ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
+ ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
return;
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-03-02 10:33 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-10 14:08 [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT Gaurav K Singh
2014-12-10 20:04 ` shuang.he
2014-12-12 7:33 ` Singh, Gaurav K
2015-01-14 9:31 ` Singh, Gaurav K
2015-01-15 11:25 ` Jani Nikula
2015-01-17 4:05 ` Daniel Vetter
2014-12-19 9:33 ` Jani Nikula
-- strict thread matches above, loose matches on Subject: below --
2015-03-02 10:31 Gaurav K Singh
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