[PATCH 0/7] drm/i915: CHV RC6/turbo fixes and improvements

[PATCH 0/7] drm/i915: CHV RC6/turbo fixes and improvements

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This series fixes the performance regression caused by the CHV RC6
EI->TO mode change. I also slapped on some other cleanups, and I
added a new media_rc6 residency file to sysfs so that we can observe
the RC6 residency of the media well and not just the render well.

Ville Syrjälä (7):
  drm/i915: Disable RC6 before configuring in on VLV/CHV
  drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimal
  drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV
  Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv""
  drm/i915: Drop VLV checks from rc6p and rc6pp sysfs files
  drm/i915: Rename 'reg' to 'clk_reg' to unconfuse it from the other
    'reg'
  drm/i915: Add media rc6 residency file to sysfs

 drivers/gpu/drm/i915/i915_sysfs.c | 37 +++++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_pm.c   | 14 +++++++++++---
 2 files changed, 40 insertions(+), 11 deletions(-)

-- 
2.0.5

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[PATCH 1/7] drm/i915: Disable RC6 before configuring in on VLV/CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Follow the sequence in the BIOS spec and clear the RC_CONTROL register
before changing any of the other RC6/RP registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b73d601..e7f0f21 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4712,6 +4712,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
 	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 
+	/*  Disable RC states. */
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+
 	/* 2a: Program RC6 thresholds.*/
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4801,6 +4804,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
 	/* If VLV, Forcewake all wells, else re-direct to regular path */
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 
+	/*  Disable RC states. */
+	I915_WRITE(GEN6_RC_CONTROL, 0);
+
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
-- 
2.0.5

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Re: [PATCH 1/7] drm/i915: Disable RC6 before configuring in on VLV/CHV

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:47PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Follow the sequence in the BIOS spec and clear the RC_CONTROL register
> before changing any of the other RC6/RP registers.

Hmm, we do disable RC_CONTROL except for a very notable absence of
santiizing register state following a reset.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I do like this patch for its documentary though.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
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Re: [PATCH 1/7] drm/i915: Disable RC6 before configuring in on VLV/CHV

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Follow the sequence in the BIOS spec and clear the RC_CONTROL register
> before changing any of the other RC6/RP registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b73d601..e7f0f21 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4712,6 +4712,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
>   	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
>   	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
>   
> +	/*  Disable RC states. */
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
>   	/* 2a: Program RC6 thresholds.*/
>   	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>   	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> @@ -4801,6 +4804,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
>   	/* If VLV, Forcewake all wells, else re-direct to regular path */
>   	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
>   
> +	/*  Disable RC states. */
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
> +
>   	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>   	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>   	I915_WRITE(GEN6_RP_UP_EI, 66000);

Reviewed-by: Deepak S<deepak.s@intel.com>

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[PATCH 2/7] drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimal

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We use decimal for all the other RP magic values, so change
GEN6_RP_DOWN_TIMEOUT to decimal as well. Also change the order
of the register writes to match the BIOS spec for easier verification.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e7f0f21..ee9a5f9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4807,13 +4807,13 @@ static void valleyview_enable_rps(struct drm_device *dev)
 	/*  Disable RC states. */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
 	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
-	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
 
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_TURBO |
-- 
2.0.5

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Re: [PATCH 2/7] drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimal

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:48PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We use decimal for all the other RP magic values, so change
> GEN6_RP_DOWN_TIMEOUT to decimal as well. Also change the order
> of the register writes to match the BIOS spec for easier verification.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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Re: [PATCH 2/7] drm/i915: Change VLV GEN6_RP_DOWN_TIMEOUT value to decimal

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We use decimal for all the other RP magic values, so change
> GEN6_RP_DOWN_TIMEOUT to decimal as well. Also change the order
> of the register writes to match the BIOS spec for easier verification.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e7f0f21..ee9a5f9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4807,13 +4807,13 @@ static void valleyview_enable_rps(struct drm_device *dev)
>   	/*  Disable RC states. */
>   	I915_WRITE(GEN6_RC_CONTROL, 0);
>   
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
>   	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>   	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>   	I915_WRITE(GEN6_RP_UP_EI, 66000);
>   	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
>   
>   	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> -	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
>   
>   	I915_WRITE(GEN6_RP_CONTROL,
>   		   GEN6_RP_MEDIA_TURBO |

:)
Reviewed-by: Deepak S<deepak.s@intel.com>

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[PATCH 3/7] drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
the RP down timeout interrupt, and says that the timeout value is hence
not used. We do enable that interrupt currently though, so leaving the
timeout as 0 results in very poor performance as the GPU frequency keeps
dropping constantly. So just program the register with the recommended
value.

Leaving the interrupt enabled doesn't seem to do any harm so far. So
I've decided to leave it on for now, just to avoid making CHV a
special case.

This fixes the performance regression from:
 commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7
 Author: Deepak S <deepak.s@linux.intel.com>
 Date:   Sat Dec 13 11:43:27 2014 +0530

    drm/i915/chv: Use timeout mode for RC6 on chv

Cc: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee9a5f9..8c7a07d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4743,6 +4743,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
 	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
-- 
2.0.5

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Re: [PATCH 3/7] drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
> the RP down timeout interrupt, and says that the timeout value is hence
> not used. We do enable that interrupt currently though, so leaving the
> timeout as 0 results in very poor performance as the GPU frequency keeps
> dropping constantly. So just program the register with the recommended
> value.
>
> Leaving the interrupt enabled doesn't seem to do any harm so far. So
> I've decided to leave it on for now, just to avoid making CHV a
> special case.
>
> This fixes the performance regression from:
>   commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7
>   Author: Deepak S <deepak.s@linux.intel.com>
>   Date:   Sat Dec 13 11:43:27 2014 +0530
>
>      drm/i915/chv: Use timeout mode for RC6 on chv
>
> Cc: Deepak S <deepak.s@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ee9a5f9..8c7a07d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4743,6 +4743,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>   
>   	/* 4 Program defaults and thresholds for RPS*/
> +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

I agree programing RP_DOWN_TIMEOUT Can cause the perf issue. I am surprised why we are not seeing similar issues with RC6 EI?

anways, we do not use GEN6_RP_DOWN_TIMEOUT in chv. Programing it's value to default should not harm
Reviewed-by: Deepak S <deepak.s@intel.com>

>   	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>   	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>   	I915_WRITE(GEN6_RP_UP_EI, 66000);

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Re: [PATCH 3/7] drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV

[Ville Syrjälä]

On Tue, Jan 20, 2015 at 08:45:50AM +0530, Deepak S wrote:
> 
> On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable
> > the RP down timeout interrupt, and says that the timeout value is hence
> > not used. We do enable that interrupt currently though, so leaving the
> > timeout as 0 results in very poor performance as the GPU frequency keeps
> > dropping constantly. So just program the register with the recommended
> > value.
> >
> > Leaving the interrupt enabled doesn't seem to do any harm so far. So
> > I've decided to leave it on for now, just to avoid making CHV a
> > special case.
> >
> > This fixes the performance regression from:
> >   commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7
> >   Author: Deepak S <deepak.s@linux.intel.com>
> >   Date:   Sat Dec 13 11:43:27 2014 +0530
> >
> >      drm/i915/chv: Use timeout mode for RC6 on chv
> >
> > Cc: Deepak S <deepak.s@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_pm.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ee9a5f9..8c7a07d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4743,6 +4743,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
> >   
> >   	/* 4 Program defaults and thresholds for RPS*/
> > +	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> 
> I agree programing RP_DOWN_TIMEOUT Can cause the perf issue. I am surprised why we are not seeing similar issues with RC6 EI?

My observation running xonotic was that the freq did seem to drop in
EI mode too (as it should since the TO vs. EI is about RC not RP), but
somehow it didn't impact performance. I can't really explain why.
RC6 residency was a flat 0 with EI, and 5-20% with TO. With the fix
performace was the more or less the same in both cases, without the
fix TO mode suffered a 40% performance drop whereas EI didn't.

> 
> anways, we do not use GEN6_RP_DOWN_TIMEOUT in chv. Programing it's value to default should not harm

Except we do use GEN6_RP_DOWN_TIMEOUT, as in we enable the relevant
interrupt. I did also test a patch that left GEN6_RP_DOWN_TIMEOUT at 0,
and instead disabled the interrupt, and that also fixed the performance
bug. But I wanted to avoid making CHV even more of a special case, so
I've left the interrupt enabled, at least for now.

> Reviewed-by: Deepak S <deepak.s@intel.com>
> 
> >   	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
> >   	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
> >   	I915_WRITE(GEN6_RP_UP_EI, 66000);

-- 
Ville Syrjälä
Intel OTC
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[PATCH 4/7] Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv""

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The performance regression from the CHV RC6 EI->TO change is now fixed
so re-enable TO mode for better RC6 resicency.

This reverts commit e85a5c7989c5be8fe30acc35eba9fb54b3450f36.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8c7a07d..8ee65da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4724,7 +4724,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 
-	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+	/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
+	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
 
 	/* allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4738,7 +4739,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 	/* 3: Enable RC6 */
 	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
 						(pcbr >> VLV_PCBR_ADDR_SHIFT))
-		rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+		rc6_mode = GEN7_RC_CTL_TO_MODE;
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-- 
2.0.5

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Re: [PATCH 4/7] Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv""

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The performance regression from the CHV RC6 EI->TO change is now fixed
> so re-enable TO mode for better RC6 resicency.
>
> This reverts commit e85a5c7989c5be8fe30acc35eba9fb54b3450f36.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8c7a07d..8ee65da 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4724,7 +4724,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
>   		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>   	I915_WRITE(GEN6_RC_SLEEP, 0);
>   
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> +	/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
> +	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
>   
>   	/* allows RC6 residency counter to work */
>   	I915_WRITE(VLV_COUNTER_CONTROL,
> @@ -4738,7 +4739,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
>   	/* 3: Enable RC6 */
>   	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
>   						(pcbr >> VLV_PCBR_ADDR_SHIFT))
> -		rc6_mode = GEN6_RC_CTL_EI_MODE(1);
> +		rc6_mode = GEN7_RC_CTL_TO_MODE;
>   
>   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>   

Reviewed-by: Deepak S<deepak.s@linux.intel.com>


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[PATCH 5/7] drm/i915: Drop VLV checks from rc6p and rc6pp sysfs files

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't register the rc6p and rc6pp sysfs files on VLV, so there's no
point in having any VLV checks in them. Drop the checks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 4a5af69..04174f0 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -116,8 +116,6 @@ show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_minor *dminor = dev_to_drm_minor(kdev);
 	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
-	if (IS_VALLEYVIEW(dminor->dev))
-		rc6p_residency = 0;
 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
 }
 
@@ -126,8 +124,6 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 {
 	struct drm_minor *dminor = dev_to_drm_minor(kdev);
 	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
-	if (IS_VALLEYVIEW(dminor->dev))
-		rc6pp_residency = 0;
 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
 }
 
-- 
2.0.5

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Re: [PATCH 5/7] drm/i915: Drop VLV checks from rc6p and rc6pp sysfs files

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:51PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We don't register the rc6p and rc6pp sysfs files on VLV, so there's no
> point in having any VLV checks in them. Drop the checks.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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Re: [PATCH 5/7] drm/i915: Drop VLV checks from rc6p and rc6pp sysfs files

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't register the rc6p and rc6pp sysfs files on VLV, so there's no
> point in having any VLV checks in them. Drop the checks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_sysfs.c | 4 ----
>   1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 4a5af69..04174f0 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -116,8 +116,6 @@ show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
>   {
>   	struct drm_minor *dminor = dev_to_drm_minor(kdev);
>   	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
> -	if (IS_VALLEYVIEW(dminor->dev))
> -		rc6p_residency = 0;
>   	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
>   }
>   
> @@ -126,8 +124,6 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
>   {
>   	struct drm_minor *dminor = dev_to_drm_minor(kdev);
>   	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
> -	if (IS_VALLEYVIEW(dminor->dev))
> -		rc6pp_residency = 0;
>   	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
>   }
>   

Reviewed-by: Deepak S<deepak.s@linux.intel.com>

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[PATCH 6/7] drm/i915: Rename 'reg' to 'clk_reg' to unconfuse it from the other 'reg'

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On VLV/CHV the rc6 residency calculations read a second register to
determine the actual units used for the residency value. The variable
name 'reg' where that register value is stored shadows the function
argument 'reg'. That can easily leave the readed utterly confused, so
rename the internal variable to 'clk_reg'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 04174f0..1ca944b 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,14 +49,14 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev)) {
-		u32 reg, czcount_30ns;
+		u32 clk_reg, czcount_30ns;
 
 		if (IS_CHERRYVIEW(dev))
-			reg = CHV_CLK_CTL1;
+			clk_reg = CHV_CLK_CTL1;
 		else
-			reg = VLV_CLK_CTL2;
+			clk_reg = VLV_CLK_CTL2;
 
-		czcount_30ns = I915_READ(reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
+		czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
 
 		if (!czcount_30ns) {
 			WARN(!czcount_30ns, "bogus CZ count value");
-- 
2.0.5

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Re: [PATCH 6/7] drm/i915: Rename 'reg' to 'clk_reg' to unconfuse it from the other 'reg'

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:52PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On VLV/CHV the rc6 residency calculations read a second register to
> determine the actual units used for the residency value. The variable
> name 'reg' where that register value is stored shadows the function
> argument 'reg'. That can easily leave the readed utterly confused, so
> rename the internal variable to 'clk_reg'.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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Re: [PATCH 6/7] drm/i915: Rename 'reg' to 'clk_reg' to unconfuse it from the other 'reg'

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:52PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On VLV/CHV the rc6 residency calculations read a second register to
> determine the actual units used for the residency value. The variable
> name 'reg' where that register value is stored shadows the function
> argument 'reg'. That can easily leave the readed utterly confused, so
> rename the internal variable to 'clk_reg'.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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Re: [PATCH 6/7] drm/i915: Rename 'reg' to 'clk_reg' to unconfuse it from the other 'reg'

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On VLV/CHV the rc6 residency calculations read a second register to
> determine the actual units used for the residency value. The variable
> name 'reg' where that register value is stored shadows the function
> argument 'reg'. That can easily leave the readed utterly confused, so
> rename the internal variable to 'clk_reg'.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_sysfs.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 04174f0..1ca944b 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -49,14 +49,14 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
>   
>   	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>   	if (IS_VALLEYVIEW(dev)) {
> -		u32 reg, czcount_30ns;
> +		u32 clk_reg, czcount_30ns;
>   
>   		if (IS_CHERRYVIEW(dev))
> -			reg = CHV_CLK_CTL1;
> +			clk_reg = CHV_CLK_CTL1;
>   		else
> -			reg = VLV_CLK_CTL2;
> +			clk_reg = VLV_CLK_CTL2;
>   
> -		czcount_30ns = I915_READ(reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
> +		czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
>   
>   		if (!czcount_30ns) {
>   			WARN(!czcount_30ns, "bogus CZ count value");

Reviewed-by: Deepak S<deepak.s@linux.intel.com>

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[PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On VLV/CHV the media well rc6 residency gets reported separately
from the render well, so add another file to sysfs so that we can
report the residency to the user.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_sysfs.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 1ca944b..db14d3e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -127,10 +127,19 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
 }
 
+static ssize_t
+show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+	struct drm_minor *dminor = dev_get_drvdata(kdev);
+	u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
+	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
+}
+
 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
+static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
 
 static struct attribute *rc6_attrs[] = {
 	&dev_attr_rc6_enable.attr,
@@ -153,6 +162,16 @@ static struct attribute_group rc6p_attr_group = {
 	.name = power_group_name,
 	.attrs =  rc6p_attrs
 };
+
+static struct attribute *media_rc6_attrs[] = {
+	&dev_attr_media_rc6_residency_ms.attr,
+	NULL
+};
+
+static struct attribute_group media_rc6_attr_group = {
+	.name = power_group_name,
+	.attrs =  media_rc6_attrs
+};
 #endif
 
 static int l3_access_valid(struct drm_device *dev, loff_t offset)
@@ -612,6 +631,12 @@ void i915_setup_sysfs(struct drm_device *dev)
 		if (ret)
 			DRM_ERROR("RC6p residency sysfs setup failed\n");
 	}
+	if (IS_VALLEYVIEW(dev)) {
+		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
+					&media_rc6_attr_group);
+		if (ret)
+			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
+	}
 #endif
 	if (HAS_L3_DPF(dev)) {
 		ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
-- 
2.0.5

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Re: [PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[Chris Wilson]

On Mon, Jan 19, 2015 at 01:50:53PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On VLV/CHV the media well rc6 residency gets reported separately
> from the render well, so add another file to sysfs so that we can
> report the residency to the user.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

To be extended in future I am sure.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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Re: [PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5603
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              353/353              352/353
ILK                                  353/353              353/353
SNB                                  400/422              400/422
IVB                                  487/487              487/487
BYT                                  296/296              296/296
HSW              +21                 487/508              508/508
BDW                                  401/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gen3_render_linear_blits      PASS(5, M25M23)      CRASH(1, M23)
 HSW  igt_kms_cursor_crc_cursor-size-change      NSPT(1, M19)TIMEOUT(1, M40)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_kms_fence_pin_leak      NSPT(1, M19)DMESG_WARN(1, M40)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_lpsp_non-edp      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_cursor      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_cursor-dpms      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_drm-resources-equal      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_fences      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_fences-dpms      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-execbuf      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-pread      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_i2c      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_pci-d3-state      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
 HSW  igt_pm_rpm_rte      NSPT(1, M19)PASS(4, M20M19)      PASS(1, M19)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[Deepak S]

On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On VLV/CHV the media well rc6 residency gets reported separately
> from the render well, so add another file to sysfs so that we can
> report the residency to the user.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks like we missed Media well completely :) and I think we need igt test to verify media residency?

Reviewed-by: Deepak S<deepak.s@linux.intel.com>

> ---
>   drivers/gpu/drm/i915/i915_sysfs.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 1ca944b..db14d3e 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -127,10 +127,19 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
>   	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
>   }
>   
> +static ssize_t
> +show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
> +{
> +	struct drm_minor *dminor = dev_get_drvdata(kdev);
> +	u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
> +	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
> +}
> +
>   static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
>   static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
>   static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
>   static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
> +static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
>   
>   static struct attribute *rc6_attrs[] = {
>   	&dev_attr_rc6_enable.attr,
> @@ -153,6 +162,16 @@ static struct attribute_group rc6p_attr_group = {
>   	.name = power_group_name,
>   	.attrs =  rc6p_attrs
>   };
> +
> +static struct attribute *media_rc6_attrs[] = {
> +	&dev_attr_media_rc6_residency_ms.attr,
> +	NULL
> +};
> +
> +static struct attribute_group media_rc6_attr_group = {
> +	.name = power_group_name,
> +	.attrs =  media_rc6_attrs
> +};
>   #endif
>   
>   static int l3_access_valid(struct drm_device *dev, loff_t offset)
> @@ -612,6 +631,12 @@ void i915_setup_sysfs(struct drm_device *dev)
>   		if (ret)
>   			DRM_ERROR("RC6p residency sysfs setup failed\n");
>   	}
> +	if (IS_VALLEYVIEW(dev)) {
> +		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
> +					&media_rc6_attr_group);
> +		if (ret)
> +			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
> +	}
>   #endif
>   	if (HAS_L3_DPF(dev)) {
>   		ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);

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Re: [PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[Daniel Vetter]

On Tue, Jan 20, 2015 at 08:54:58AM +0530, Deepak S wrote:
> 
> On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >On VLV/CHV the media well rc6 residency gets reported separately
> >from the render well, so add another file to sysfs so that we can
> >report the residency to the user.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Looks like we missed Media well completely :) and I think we need igt test to verify media residency?

Indeed, Testcase: line is missing. And unfortunately the current testcase
is severly broken, so there's some work to be done there.

I've merged all the other patches from this series.

Thanks, Daniel
> 
> Reviewed-by: Deepak S<deepak.s@linux.intel.com>
> 
> >---
> >  drivers/gpu/drm/i915/i915_sysfs.c | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> >index 1ca944b..db14d3e 100644
> >--- a/drivers/gpu/drm/i915/i915_sysfs.c
> >+++ b/drivers/gpu/drm/i915/i915_sysfs.c
> >@@ -127,10 +127,19 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
> >  	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
> >  }
> >+static ssize_t
> >+show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
> >+{
> >+	struct drm_minor *dminor = dev_get_drvdata(kdev);
> >+	u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
> >+	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
> >+}
> >+
> >  static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
> >  static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
> >  static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
> >  static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
> >+static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
> >  static struct attribute *rc6_attrs[] = {
> >  	&dev_attr_rc6_enable.attr,
> >@@ -153,6 +162,16 @@ static struct attribute_group rc6p_attr_group = {
> >  	.name = power_group_name,
> >  	.attrs =  rc6p_attrs
> >  };
> >+
> >+static struct attribute *media_rc6_attrs[] = {
> >+	&dev_attr_media_rc6_residency_ms.attr,
> >+	NULL
> >+};
> >+
> >+static struct attribute_group media_rc6_attr_group = {
> >+	.name = power_group_name,
> >+	.attrs =  media_rc6_attrs
> >+};
> >  #endif
> >  static int l3_access_valid(struct drm_device *dev, loff_t offset)
> >@@ -612,6 +631,12 @@ void i915_setup_sysfs(struct drm_device *dev)
> >  		if (ret)
> >  			DRM_ERROR("RC6p residency sysfs setup failed\n");
> >  	}
> >+	if (IS_VALLEYVIEW(dev)) {
> >+		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
> >+					&media_rc6_attr_group);
> >+		if (ret)
> >+			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
> >+	}
> >  #endif
> >  	if (HAS_L3_DPF(dev)) {
> >  		ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 7/7] drm/i915: Add media rc6 residency file to sysfs

[Ville Syrjälä]

On Tue, Jan 20, 2015 at 09:50:36AM +0100, Daniel Vetter wrote:
> On Tue, Jan 20, 2015 at 08:54:58AM +0530, Deepak S wrote:
> > 
> > On Monday 19 January 2015 05:20 PM, ville.syrjala@linux.intel.com wrote:
> > >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > >On VLV/CHV the media well rc6 residency gets reported separately
> > >from the render well, so add another file to sysfs so that we can
> > >report the residency to the user.
> > >
> > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Looks like we missed Media well completely :) and I think we need igt test to verify media residency?
> 
> Indeed, Testcase: line is missing. And unfortunately the current testcase
> is severly broken, so there's some work to be done there.

Do we have any volunteers? I have a boatload of bigger fish to fry at
the moment so can't take up another project.

> 
> I've merged all the other patches from this series.
> 
> Thanks, Daniel
> > 
> > Reviewed-by: Deepak S<deepak.s@linux.intel.com>
> > 
> > >---
> > >  drivers/gpu/drm/i915/i915_sysfs.c | 25 +++++++++++++++++++++++++
> > >  1 file changed, 25 insertions(+)
> > >
> > >diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> > >index 1ca944b..db14d3e 100644
> > >--- a/drivers/gpu/drm/i915/i915_sysfs.c
> > >+++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > >@@ -127,10 +127,19 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
> > >  	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
> > >  }
> > >+static ssize_t
> > >+show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
> > >+{
> > >+	struct drm_minor *dminor = dev_get_drvdata(kdev);
> > >+	u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
> > >+	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
> > >+}
> > >+
> > >  static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
> > >  static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
> > >  static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
> > >  static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
> > >+static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
> > >  static struct attribute *rc6_attrs[] = {
> > >  	&dev_attr_rc6_enable.attr,
> > >@@ -153,6 +162,16 @@ static struct attribute_group rc6p_attr_group = {
> > >  	.name = power_group_name,
> > >  	.attrs =  rc6p_attrs
> > >  };
> > >+
> > >+static struct attribute *media_rc6_attrs[] = {
> > >+	&dev_attr_media_rc6_residency_ms.attr,
> > >+	NULL
> > >+};
> > >+
> > >+static struct attribute_group media_rc6_attr_group = {
> > >+	.name = power_group_name,
> > >+	.attrs =  media_rc6_attrs
> > >+};
> > >  #endif
> > >  static int l3_access_valid(struct drm_device *dev, loff_t offset)
> > >@@ -612,6 +631,12 @@ void i915_setup_sysfs(struct drm_device *dev)
> > >  		if (ret)
> > >  			DRM_ERROR("RC6p residency sysfs setup failed\n");
> > >  	}
> > >+	if (IS_VALLEYVIEW(dev)) {
> > >+		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
> > >+					&media_rc6_attr_group);
> > >+		if (ret)
> > >+			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
> > >+	}
> > >  #endif
> > >  	if (HAS_L3_DPF(dev)) {
> > >  		ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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