* [PATCH 1/9] drm/i915: Change plane_config to store a tiling_mode
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 2/9] drm/i915: Use a common function for computing the fb height alignment Damien Lespiau
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
Rather than having "tiled" meaning "is it X-tiled?" convert the field to
explicitely store the tiling mode. The code doesn't have to change much
as 1 is conveniently I915_TILING_X.
This is to accommodate future changes around tiling modes and scannout
buffers.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 17 ++++++++---------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91d8ada..f5c4d18 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2352,10 +2352,9 @@ static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
if (!obj)
return false;
- if (plane_config->tiled) {
- obj->tiling_mode = I915_TILING_X;
+ obj->tiling_mode = plane_config->tiling;
+ if (obj->tiling_mode == I915_TILING_X)
obj->stride = crtc->base.primary->fb->pitches[0];
- }
mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
mode_cmd.width = crtc->base.primary->fb->width;
@@ -6560,7 +6559,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
if (INTEL_INFO(dev)->gen >= 4)
if (val & DISPPLANE_TILED)
- plane_config->tiled = true;
+ plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
fourcc = intel_format_to_fourcc(pixel_format);
@@ -6569,7 +6568,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
drm_format_plane_cpp(fourcc, 0) * 8;
if (INTEL_INFO(dev)->gen >= 4) {
- if (plane_config->tiled)
+ if (plane_config->tiling)
offset = I915_READ(DSPTILEOFF(plane));
else
offset = I915_READ(DSPLINOFF(plane));
@@ -6587,7 +6586,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
- plane_config->tiled);
+ plane_config->tiling);
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
aligned_height);
@@ -7611,7 +7610,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
if (INTEL_INFO(dev)->gen >= 4)
if (val & DISPPLANE_TILED)
- plane_config->tiled = true;
+ plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
fourcc = intel_format_to_fourcc(pixel_format);
@@ -7623,7 +7622,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
offset = I915_READ(DSPOFFSET(plane));
} else {
- if (plane_config->tiled)
+ if (plane_config->tiling)
offset = I915_READ(DSPTILEOFF(plane));
else
offset = I915_READ(DSPLINOFF(plane));
@@ -7638,7 +7637,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
- plane_config->tiled);
+ plane_config->tiling);
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
aligned_height);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30e968f..2ff94d3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -258,7 +258,7 @@ struct intel_plane_state {
};
struct intel_plane_config {
- bool tiled;
+ unsigned int tiling;
int size;
u32 base;
};
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 850cf7d..4ee6d85 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -593,7 +593,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
}
cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay;
- cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
+ cur_size = ALIGN(cur_size, plane_config->tiling ? (IS_GEN2(dev) ? 16 : 8) : 1);
cur_size *= fb->base.pitches[0];
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
pipe_name(intel_crtc->pipe),
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/9] drm/i915: Use a common function for computing the fb height alignment
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
2015-01-19 18:44 ` [PATCH 1/9] drm/i915: Change plane_config to store a tiling_mode Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 3/9] drm/i915: Unclutter the get_plane() functions Damien Lespiau
` (7 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
If we need to change the fb height constraints, it sounds like a good
idea to have to do it in one place only.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_fbdev.c | 3 ++-
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f5c4d18..1ff7402 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2188,11 +2188,12 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
-static int intel_align_height(struct drm_device *dev, int height, bool tiled)
+int
+intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
{
int tile_height;
- tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
+ tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
return ALIGN(height, tile_height);
}
@@ -6585,8 +6586,9 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
val = I915_READ(DSPSTRIDE(pipe));
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
- aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
- plane_config->tiling);
+ aligned_height = intel_fb_align_height(dev,
+ crtc->base.primary->fb->height,
+ plane_config->tiling);
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
aligned_height);
@@ -7636,8 +7638,9 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
val = I915_READ(DSPSTRIDE(pipe));
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
- aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
- plane_config->tiling);
+ aligned_height = intel_fb_align_height(dev,
+ crtc->base.primary->fb->height,
+ plane_config->tiling);
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
aligned_height);
@@ -12599,8 +12602,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
if (mode_cmd->offsets[0] != 0)
return -EINVAL;
- aligned_height = intel_align_height(dev, mode_cmd->height,
- obj->tiling_mode);
+ aligned_height = intel_fb_align_height(dev, mode_cmd->height,
+ obj->tiling_mode);
/* FIXME drm helper for size checks (especially planar formats)? */
if (obj->base.size < aligned_height * mode_cmd->pitches[0])
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2ff94d3..f7a2906 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -896,6 +896,8 @@ void intel_frontbuffer_flip(struct drm_device *dev,
intel_frontbuffer_flush(dev, frontbuffer_bits);
}
+int intel_fb_align_height(struct drm_device *dev, int height,
+ unsigned int tiling);
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 4ee6d85..1202f42 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -593,7 +593,8 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
}
cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay;
- cur_size = ALIGN(cur_size, plane_config->tiling ? (IS_GEN2(dev) ? 16 : 8) : 1);
+ cur_size = intel_fb_align_height(dev, cur_size,
+ plane_config->tiling);
cur_size *= fb->base.pitches[0];
DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
pipe_name(intel_crtc->pipe),
--
1.8.3.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 3/9] drm/i915: Unclutter the get_plane() functions
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
2015-01-19 18:44 ` [PATCH 1/9] drm/i915: Change plane_config to store a tiling_mode Damien Lespiau
2015-01-19 18:44 ` [PATCH 2/9] drm/i915: Use a common function for computing the fb height alignment Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 4/9] drm/i915: Don't use crtc->plane in ILK+ get_config() Damien Lespiau
` (6 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
crtc->base.primary->fb was used everywhere. Use fb to temporarily point
there and don't forget to assign fb to its final destination at the end.
v2: Rebase on top of misc changes (mask of DSPSURF, PAGE_ALIGN)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 61 ++++++++++++++++--------------------
1 file changed, 27 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1ff7402..3357b66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6549,9 +6549,10 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
int pipe = crtc->pipe, plane = crtc->plane;
int fourcc, pixel_format;
int aligned_height;
+ struct drm_framebuffer *fb;
- crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
- if (!crtc->base.primary->fb) {
+ fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
+ if (!fb) {
DRM_DEBUG_KMS("failed to alloc fb\n");
return;
}
@@ -6564,9 +6565,8 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
fourcc = intel_format_to_fourcc(pixel_format);
- crtc->base.primary->fb->pixel_format = fourcc;
- crtc->base.primary->fb->bits_per_pixel =
- drm_format_plane_cpp(fourcc, 0) * 8;
+ fb->pixel_format = fourcc;
+ fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
if (INTEL_INFO(dev)->gen >= 4) {
if (plane_config->tiling)
@@ -6580,26 +6580,22 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
plane_config->base = base;
val = I915_READ(PIPESRC(pipe));
- crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
- crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
+ fb->width = ((val >> 16) & 0xfff) + 1;
+ fb->height = ((val >> 0) & 0xfff) + 1;
val = I915_READ(DSPSTRIDE(pipe));
- crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
+ fb->pitches[0] = val & 0xffffffc0;
- aligned_height = intel_fb_align_height(dev,
- crtc->base.primary->fb->height,
+ aligned_height = intel_fb_align_height(dev, fb->height,
plane_config->tiling);
- plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
- aligned_height);
+ plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
- pipe, plane, crtc->base.primary->fb->width,
- crtc->base.primary->fb->height,
- crtc->base.primary->fb->bits_per_pixel, base,
- crtc->base.primary->fb->pitches[0],
- plane_config->size);
+ pipe, plane, fb->width, fb->height, fb->bits_per_pixel,
+ base, fb->pitches[0], plane_config->size);
+ crtc->base.primary->fb = fb;
}
static void chv_crtc_clock_get(struct intel_crtc *crtc,
@@ -7601,9 +7597,10 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
int pipe = crtc->pipe, plane = crtc->plane;
int fourcc, pixel_format;
int aligned_height;
+ struct drm_framebuffer *fb;
- crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
- if (!crtc->base.primary->fb) {
+ fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
+ if (!fb) {
DRM_DEBUG_KMS("failed to alloc fb\n");
return;
}
@@ -7616,9 +7613,8 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
fourcc = intel_format_to_fourcc(pixel_format);
- crtc->base.primary->fb->pixel_format = fourcc;
- crtc->base.primary->fb->bits_per_pixel =
- drm_format_plane_cpp(fourcc, 0) * 8;
+ fb->pixel_format = fourcc;
+ fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
base = I915_READ(DSPSURF(plane)) & 0xfffff000;
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
@@ -7632,25 +7628,22 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
plane_config->base = base;
val = I915_READ(PIPESRC(pipe));
- crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
- crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
+ fb->width = ((val >> 16) & 0xfff) + 1;
+ fb->height = ((val >> 0) & 0xfff) + 1;
val = I915_READ(DSPSTRIDE(pipe));
- crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
+ fb->pitches[0] = val & 0xffffffc0;
- aligned_height = intel_fb_align_height(dev,
- crtc->base.primary->fb->height,
+ aligned_height = intel_fb_align_height(dev, fb->height,
plane_config->tiling);
- plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
- aligned_height);
+ plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
- pipe, plane, crtc->base.primary->fb->width,
- crtc->base.primary->fb->height,
- crtc->base.primary->fb->bits_per_pixel, base,
- crtc->base.primary->fb->pitches[0],
- plane_config->size);
+ pipe, plane, fb->width, fb->height, fb->bits_per_pixel,
+ base, fb->pitches[0], plane_config->size);
+
+ crtc->base.primary->fb = fb;
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 4/9] drm/i915: Don't use crtc->plane in ILK+ get_config()
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (2 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 3/9] drm/i915: Unclutter the get_plane() functions Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 5/9] drm/i915: Use pipe_name() in the get_plane_config() functions Damien Lespiau
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
crtc->plane can only be different from crtc->pipe pre-Gen4. Don't use it
in new-ish code.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3357b66..633173a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7594,7 +7594,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 val, base, offset;
- int pipe = crtc->pipe, plane = crtc->plane;
+ int pipe = crtc->pipe;
int fourcc, pixel_format;
int aligned_height;
struct drm_framebuffer *fb;
@@ -7605,7 +7605,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
return;
}
- val = I915_READ(DSPCNTR(plane));
+ val = I915_READ(DSPCNTR(pipe));
if (INTEL_INFO(dev)->gen >= 4)
if (val & DISPPLANE_TILED)
@@ -7616,14 +7616,14 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
- base = I915_READ(DSPSURF(plane)) & 0xfffff000;
+ base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
- offset = I915_READ(DSPOFFSET(plane));
+ offset = I915_READ(DSPOFFSET(pipe));
} else {
if (plane_config->tiling)
- offset = I915_READ(DSPTILEOFF(plane));
+ offset = I915_READ(DSPTILEOFF(pipe));
else
- offset = I915_READ(DSPLINOFF(plane));
+ offset = I915_READ(DSPLINOFF(pipe));
}
plane_config->base = base;
@@ -7639,8 +7639,8 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
- DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
- pipe, plane, fb->width, fb->height, fb->bits_per_pixel,
+ DRM_DEBUG_KMS("pipe %d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+ pipe, fb->width, fb->height, fb->bits_per_pixel,
base, fb->pitches[0], plane_config->size);
crtc->base.primary->fb = fb;
--
1.8.3.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 5/9] drm/i915: Use pipe_name() in the get_plane_config() functions
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (3 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 4/9] drm/i915: Don't use crtc->plane in ILK+ get_config() Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 6/9] drm/i915: Make intel_format_to_fourcc() static Damien Lespiau
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
We may as well try to be consistent everywhere and know the pipes by
their name.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 633173a..eed2050 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6591,9 +6591,10 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
- DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
- pipe, plane, fb->width, fb->height, fb->bits_per_pixel,
- base, fb->pitches[0], plane_config->size);
+ DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+ pipe_name(pipe), plane, fb->width, fb->height,
+ fb->bits_per_pixel, base, fb->pitches[0],
+ plane_config->size);
crtc->base.primary->fb = fb;
}
@@ -7639,9 +7640,10 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
- DRM_DEBUG_KMS("pipe %d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
- pipe, fb->width, fb->height, fb->bits_per_pixel,
- base, fb->pitches[0], plane_config->size);
+ DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+ pipe_name(pipe), fb->width, fb->height,
+ fb->bits_per_pixel, base, fb->pitches[0],
+ plane_config->size);
crtc->base.primary->fb = fb;
}
--
1.8.3.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 6/9] drm/i915: Make intel_format_to_fourcc() static
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (4 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 5/9] drm/i915: Use pipe_name() in the get_plane_config() functions Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 7/9] drm/i915/skl: intel_format_to_fourcc() doesn't work for SKL planes Damien Lespiau
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eed2050..1678dd3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2316,7 +2316,7 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
}
}
-int intel_format_to_fourcc(int format)
+static int intel_format_to_fourcc(int format)
{
switch (format) {
case DISPPLANE_8BPP:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f7a2906..0c7f241 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1014,7 +1014,6 @@ enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_config *pipe_config);
-int intel_format_to_fourcc(int format);
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
--
1.8.3.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 7/9] drm/i915/skl: intel_format_to_fourcc() doesn't work for SKL planes
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (5 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 6/9] drm/i915: Make intel_format_to_fourcc() static Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 8/9] drm/i915/skl: Provide a Skylake version of get_plane_config() Damien Lespiau
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
We will have a skl_ version shortly!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1678dd3..08a7130 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2316,7 +2316,7 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
}
}
-static int intel_format_to_fourcc(int format)
+static int i9xx_format_to_fourcc(int format)
{
switch (format) {
case DISPPLANE_8BPP:
@@ -6564,7 +6564,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
- fourcc = intel_format_to_fourcc(pixel_format);
+ fourcc = i9xx_format_to_fourcc(pixel_format);
fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
@@ -7613,7 +7613,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
- fourcc = intel_format_to_fourcc(pixel_format);
+ fourcc = i9xx_format_to_fourcc(pixel_format);
fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
--
1.8.3.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 8/9] drm/i915/skl: Provide a Skylake version of get_plane_config()
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (6 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 7/9] drm/i915/skl: intel_format_to_fourcc() doesn't work for SKL planes Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-19 18:44 ` [PATCH 9/9] drm/i915: Rename plane_config to initial_plane_config Damien Lespiau
2015-01-20 11:25 ` [PATCH 0/9] Skylake primary plane read-out v2 Tvrtko Ursulin
9 siblings, 0 replies; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
Universal planes have changed a bit the register organization.
v2: Rebase on top of the latest drm-intel-nightly
v3: Use PLANE_SIZE to retrieve the fb size (Tvrtko)
Don't use BUG() (Tvrtko)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 113 ++++++++++++++++++++++++++++++++---
1 file changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 08a7130..24e74c0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2337,6 +2337,32 @@ static int i9xx_format_to_fourcc(int format)
}
}
+static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+{
+ switch (format) {
+ case PLANE_CTL_FORMAT_RGB_565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case PLANE_CTL_FORMAT_XRGB_8888:
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR8888;
+ else
+ return DRM_FORMAT_XBGR8888;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB8888;
+ else
+ return DRM_FORMAT_XRGB8888;
+ }
+ case PLANE_CTL_FORMAT_XRGB_2101010:
+ if (rgb_order)
+ return DRM_FORMAT_XBGR2101010;
+ else
+ return DRM_FORMAT_XRGB2101010;
+ }
+}
+
static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
struct intel_plane_config *plane_config)
{
@@ -7565,6 +7591,73 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
}
}
+static void skylake_get_plane_config(struct intel_crtc *crtc,
+ struct intel_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val, base, offset, stride_mult;
+ int pipe = crtc->pipe;
+ int fourcc, pixel_format;
+ int aligned_height;
+ struct drm_framebuffer *fb;
+
+ fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
+ if (!fb) {
+ DRM_DEBUG_KMS("failed to alloc fb\n");
+ return;
+ }
+
+ val = I915_READ(PLANE_CTL(pipe, 0));
+ if (val & PLANE_CTL_TILED_MASK)
+ plane_config->tiling = I915_TILING_X;
+
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+ fb->pixel_format = fourcc;
+ fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
+
+ base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
+ plane_config->base = base;
+
+ offset = I915_READ(PLANE_OFFSET(pipe, 0));
+
+ val = I915_READ(PLANE_SIZE(pipe, 0));
+ fb->height = ((val >> 16) & 0xfff) + 1;
+ fb->width = ((val >> 0) & 0x1fff) + 1;
+
+ val = I915_READ(PLANE_STRIDE(pipe, 0));
+ switch (plane_config->tiling) {
+ case I915_TILING_NONE:
+ stride_mult = 64;
+ break;
+ case I915_TILING_X:
+ stride_mult = 512;
+ break;
+ default:
+ goto error;
+ }
+ fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ aligned_height = intel_fb_align_height(dev, fb->height,
+ plane_config->tiling);
+
+ plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
+
+ DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
+ pipe_name(pipe), fb->width, fb->height,
+ fb->bits_per_pixel, base, fb->pitches[0],
+ plane_config->size);
+
+ crtc->base.primary->fb = fb;
+ return;
+
+error:
+ kfree(fb);
+}
+
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -12658,7 +12751,17 @@ static void intel_init_display(struct drm_device *dev)
else
dev_priv->display.find_dpll = i9xx_find_best_dpll;
- if (HAS_DDI(dev)) {
+ if (INTEL_INFO(dev)->gen >= 9) {
+ dev_priv->display.get_pipe_config = haswell_get_pipe_config;
+ dev_priv->display.get_plane_config = skylake_get_plane_config;
+ dev_priv->display.crtc_compute_clock =
+ haswell_crtc_compute_clock;
+ dev_priv->display.crtc_enable = haswell_crtc_enable;
+ dev_priv->display.crtc_disable = haswell_crtc_disable;
+ dev_priv->display.off = ironlake_crtc_off;
+ dev_priv->display.update_primary_plane =
+ skylake_update_primary_plane;
+ } else if (HAS_DDI(dev)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_plane_config = ironlake_get_plane_config;
dev_priv->display.crtc_compute_clock =
@@ -12666,12 +12769,8 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
- if (INTEL_INFO(dev)->gen >= 9)
- dev_priv->display.update_primary_plane =
- skylake_update_primary_plane;
- else
- dev_priv->display.update_primary_plane =
- ironlake_update_primary_plane;
+ dev_priv->display.update_primary_plane =
+ ironlake_update_primary_plane;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_plane_config = ironlake_get_plane_config;
--
1.8.3.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 9/9] drm/i915: Rename plane_config to initial_plane_config
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (7 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 8/9] drm/i915/skl: Provide a Skylake version of get_plane_config() Damien Lespiau
@ 2015-01-19 18:44 ` Damien Lespiau
2015-01-20 3:48 ` shuang.he
2015-01-20 11:25 ` [PATCH 0/9] Skylake primary plane read-out v2 Tvrtko Ursulin
9 siblings, 1 reply; 13+ messages in thread
From: Damien Lespiau @ 2015-01-19 18:44 UTC (permalink / raw)
To: intel-gfx
This vfunc and related structure are only used for fast boot, so let's
rename them to not take them as general purpose ones.
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++---
drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++--------------
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
4 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a4d026d..cc2c593 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,7 +504,7 @@ struct drm_i915_error_state {
struct intel_connector;
struct intel_encoder;
struct intel_crtc_config;
-struct intel_plane_config;
+struct intel_initial_plane_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
@@ -543,8 +543,8 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
- void (*get_plane_config)(struct intel_crtc *,
- struct intel_plane_config *);
+ void (*get_initial_plane_config)(struct intel_crtc *,
+ struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc);
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 24e74c0..60e99ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2363,8 +2363,9 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
}
}
-static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
- struct intel_plane_config *plane_config)
+static bool
+intel_alloc_plane_obj(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_gem_object *obj = NULL;
@@ -2408,8 +2409,9 @@ out_unref_obj:
return false;
}
-static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
- struct intel_plane_config *plane_config)
+static void
+intel_find_plane_obj(struct intel_crtc *intel_crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6566,8 +6568,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = clock.dot / 5;
}
-static void i9xx_get_plane_config(struct intel_crtc *crtc,
- struct intel_plane_config *plane_config)
+static void
+i9xx_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7591,8 +7594,9 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
}
}
-static void skylake_get_plane_config(struct intel_crtc *crtc,
- struct intel_plane_config *plane_config)
+static void
+skylake_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7682,8 +7686,9 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
}
}
-static void ironlake_get_plane_config(struct intel_crtc *crtc,
- struct intel_plane_config *plane_config)
+static void
+ironlake_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -12753,7 +12758,8 @@ static void intel_init_display(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 9) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
- dev_priv->display.get_plane_config = skylake_get_plane_config;
+ dev_priv->display.get_initial_plane_config =
+ skylake_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -12763,7 +12769,8 @@ static void intel_init_display(struct drm_device *dev)
skylake_update_primary_plane;
} else if (HAS_DDI(dev)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
- dev_priv->display.get_plane_config = ironlake_get_plane_config;
+ dev_priv->display.get_initial_plane_config =
+ ironlake_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -12773,7 +12780,8 @@ static void intel_init_display(struct drm_device *dev)
ironlake_update_primary_plane;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
- dev_priv->display.get_plane_config = ironlake_get_plane_config;
+ dev_priv->display.get_initial_plane_config =
+ ironlake_get_initial_plane_config;
dev_priv->display.crtc_compute_clock =
ironlake_crtc_compute_clock;
dev_priv->display.crtc_enable = ironlake_crtc_enable;
@@ -12783,7 +12791,8 @@ static void intel_init_display(struct drm_device *dev)
ironlake_update_primary_plane;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.get_plane_config = i9xx_get_plane_config;
+ dev_priv->display.get_initial_plane_config =
+ i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
dev_priv->display.crtc_enable = valleyview_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -12792,7 +12801,8 @@ static void intel_init_display(struct drm_device *dev)
i9xx_update_primary_plane;
} else {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.get_plane_config = i9xx_get_plane_config;
+ dev_priv->display.get_initial_plane_config =
+ i9xx_get_initial_plane_config;
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
dev_priv->display.crtc_enable = i9xx_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -13164,8 +13174,8 @@ void intel_modeset_init(struct drm_device *dev)
* can even allow for smooth boot transitions if the BIOS
* fb is large enough for the active pipe configuration.
*/
- if (dev_priv->display.get_plane_config) {
- dev_priv->display.get_plane_config(crtc,
+ if (dev_priv->display.get_initial_plane_config) {
+ dev_priv->display.get_initial_plane_config(crtc,
&crtc->plane_config);
/*
* If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0c7f241..cb85509 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -257,7 +257,7 @@ struct intel_plane_state {
bool hides_primary;
};
-struct intel_plane_config {
+struct intel_initial_plane_config {
unsigned int tiling;
int size;
u32 base;
@@ -476,7 +476,7 @@ struct intel_crtc {
uint32_t cursor_size;
uint32_t cursor_base;
- struct intel_plane_config plane_config;
+ struct intel_initial_plane_config plane_config;
struct intel_crtc_config config;
struct intel_crtc_config *new_config;
bool new_enabled;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 1202f42..d766867 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -531,7 +531,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
struct intel_framebuffer *fb = NULL;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
- struct intel_plane_config *plane_config = NULL;
+ struct intel_initial_plane_config *plane_config = NULL;
unsigned int max_size = 0;
if (!i915.fastboot)
--
1.8.3.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 9/9] drm/i915: Rename plane_config to initial_plane_config
2015-01-19 18:44 ` [PATCH 9/9] drm/i915: Rename plane_config to initial_plane_config Damien Lespiau
@ 2015-01-20 3:48 ` shuang.he
0 siblings, 0 replies; 13+ messages in thread
From: shuang.he @ 2015-01-20 3:48 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5606
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 353/353 353/353
ILK 353/353 353/353
SNB 400/422 400/422
IVB 487/487 487/487
BYT 296/296 296/296
HSW +21 487/508 508/508
BDW 401/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
HSW igt_kms_cursor_crc_cursor-size-change NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_kms_fence_pin_leak NSPT(1, M19)DMESG_WARN(1, M40)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_lpsp_non-edp NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_cursor NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_cursor-dpms NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_dpms-non-lpsp NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_drm-resources-equal NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_fences NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_fences-dpms NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_gem-execbuf NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_gem-mmap-cpu NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_gem-mmap-gtt NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_gem-pread NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_i2c NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_modeset-non-lpsp NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_pci-d3-state NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
HSW igt_pm_rpm_rte NSPT(1, M19)PASS(8, M20M19M40) PASS(1, M19)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/9] Skylake primary plane read-out v2
2015-01-19 18:44 [PATCH 0/9] Skylake primary plane read-out v2 Damien Lespiau
` (8 preceding siblings ...)
2015-01-19 18:44 ` [PATCH 9/9] drm/i915: Rename plane_config to initial_plane_config Damien Lespiau
@ 2015-01-20 11:25 ` Tvrtko Ursulin
9 siblings, 0 replies; 13+ messages in thread
From: Tvrtko Ursulin @ 2015-01-20 11:25 UTC (permalink / raw)
To: Damien Lespiau, intel-gfx
Hi,
On 01/19/2015 06:44 PM, Damien Lespiau wrote:
> Follow up of http://lists.freedesktop.org/archives/intel-gfx/2014-October/054391.html
>
> with:
> - Remarks from Tvrtko on patch 8 addressed.
> - Suggestion from Daniel implemented (patch 9)
All looks fine to me, you can add my r-b to the series:
Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
P.S. Applies also if you decide to add the MISSING_CASE() Daniel suggested.
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^ permalink raw reply [flat|nested] 13+ messages in thread