From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ramalingam C Subject: Re: [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR Date: Wed, 21 Jan 2015 16:49:54 +0530 Message-ID: <54BF8B5A.7060700@intel.com> References: <1420836965-10068-1-git-send-email-vandana.kannan@intel.com> <1420836965-10068-6-git-send-email-vandana.kannan@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1149014267==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FF406E746 for ; Wed, 21 Jan 2015 03:24:18 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi , Vandana Kannan Cc: intel-gfx , Paulo Zanoni , "Vivi, Rodrigo" List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============1149014267== Content-Type: multipart/alternative; boundary="------------030804070609090003020506" This is a multi-part message in MIME format. --------------030804070609090003020506 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit On Friday 16 January 2015 04:30 AM, Rodrigo Vivi wrote: > On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan > wrote: >> For Broadwell, there is one instance of Transcoder MN values per transcoder. >> For dynamic switching between multiple refreshr rates, M/N values may be >> reprogrammed on the fly. Link N programming triggers update of all data and >> link M & N registers and the new M/N values will be used in the next frame >> that is output. >> >> Signed-off-by: Vandana Kannan >> Signed-off-by: Pradeep Bhat >> --- >> drivers/gpu/drm/i915/intel_display.c | 9 +++------ >> drivers/gpu/drm/i915/intel_dp.c | 15 ++++++++++++++- >> drivers/gpu/drm/i915/intel_drv.h | 3 +++ >> 3 files changed, 20 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index a03955d..25596ca 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev, >> struct drm_i915_gem_object *obj); >> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); >> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); >> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, >> - struct intel_link_m_n *m_n, >> - struct intel_link_m_n *m2_n2); >> static void ironlake_set_pipeconf(struct drm_crtc *crtc); >> static void haswell_set_pipeconf(struct drm_crtc *crtc); >> static void intel_set_pipe_csc(struct drm_crtc *crtc); >> @@ -5795,9 +5792,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, >> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); >> } >> >> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, >> - struct intel_link_m_n *m_n, >> - struct intel_link_m_n *m2_n2) >> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, >> + struct intel_link_m_n *m_n, >> + struct intel_link_m_n *m2_n2) >> { >> struct drm_device *dev = crtc->base.dev; >> struct drm_i915_private *dev_priv = dev->dev_private; >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index ca89e59..85a029e 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -4802,7 +4802,20 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) >> return; >> } >> >> - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { >> + if (INTEL_INFO(dev)->gen >= 8) { >> + switch(index) { >> + case DRRS_HIGH_RR: >> + intel_dp_set_m_n(intel_crtc); >> + break; >> + case DRRS_LOW_RR: >> + intel_cpu_transcoder_set_m_n(intel_crtc, > I didn't like this mix of intel_dp_set and intel_cpu set when > intel_dp_set calls cpu set only when it doesn't have pch... > It seems at least strange. > > Maybe change intel_dp_set_m_n to support different sets... > >> + &intel_crtc->config.dp_m2_n2, NULL); > Also didn't understand why sending m2_n2 on m1_n1 and NULL on m2_n2. > > Is there a way to change that function to support different ways > instead of doing this? Agreed. I will rewrite the intel_dp_set_m_n to handle all different sets. > >> + break; >> + case DRRS_MAX_RR: >> + default: >> + break; >> + } >> + } else if (INTEL_INFO(dev)->gen > 6) { >> reg = PIPECONF(intel_crtc->config.cpu_transcoder); >> val = I915_READ(reg); >> if (index > DRRS_HIGH_RR) { >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> index 17f168a..f5846cf 100644 >> --- a/drivers/gpu/drm/i915/intel_drv.h >> +++ b/drivers/gpu/drm/i915/intel_drv.h >> @@ -953,6 +953,9 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv); >> void intel_dp_get_m_n(struct intel_crtc *crtc, >> struct intel_crtc_config *pipe_config); >> void intel_dp_set_m_n(struct intel_crtc *crtc); >> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, >> + struct intel_link_m_n *m_n, >> + struct intel_link_m_n *m2_n2); >> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); >> void >> ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, >> -- >> 2.0.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > --Ram --------------030804070609090003020506 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit
On Friday 16 January 2015 04:30 AM, Rodrigo Vivi wrote:
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:

For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  9 +++------
 drivers/gpu/drm/i915/intel_dp.c      | 15 ++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h     |  3 +++
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a03955d..25596ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
                                  struct drm_i915_gem_object *obj);
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-                                        struct intel_link_m_n *m_n,
-                                        struct intel_link_m_n *m2_n2);
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -5795,9 +5792,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
        I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
 }

-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-                                        struct intel_link_m_n *m_n,
-                                        struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+                                struct intel_link_m_n *m_n,
+                                struct intel_link_m_n *m2_n2)
 {
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca89e59..85a029e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4802,7 +4802,20 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
                return;
        }

-       if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+       if (INTEL_INFO(dev)->gen >= 8) {
+               switch(index) {
+               case DRRS_HIGH_RR:
+                       intel_dp_set_m_n(intel_crtc);
+                       break;
+               case DRRS_LOW_RR:
+                       intel_cpu_transcoder_set_m_n(intel_crtc,

I didn't like this mix of intel_dp_set and intel_cpu set when
intel_dp_set calls cpu set only when it doesn't have pch...
It seems at least strange.

Maybe change intel_dp_set_m_n to support different sets...


+                                       &intel_crtc->config.dp_m2_n2, NULL);

Also didn't understand why sending m2_n2 on m1_n1 and NULL on m2_n2.

Is there a way to change that function to support different ways
instead of doing this?
Agreed. I will rewrite the intel_dp_set_m_n to handle all different sets.


+                       break;
+               case DRRS_MAX_RR:
+               default:
+                       break;
+               }
+       } else if (INTEL_INFO(dev)->gen > 6) {
                reg = PIPECONF(intel_crtc->config.cpu_transcoder);
                val = I915_READ(reg);
                if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17f168a..f5846cf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -953,6 +953,9 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
                      struct intel_crtc_config *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+                                struct intel_link_m_n *m_n,
+                                struct intel_link_m_n *m2_n2);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 void
 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
--
2.0.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--Ram
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