* [PATCH 1/10] drm/i915: Modifying structures related to DRRS
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
@ 2015-01-09 20:55 ` Vandana Kannan
2015-01-14 1:27 ` Rodrigo Vivi
2015-01-09 20:55 ` [PATCH 2/10] drm/i915: Initialize DRRS delayed work Vandana Kannan
` (8 subsequent siblings)
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Earlier, DRRS structures were specific to eDP (used only in intel_dp).
Since DRRS can be extended to other internal display types
(if the panel supports multiple RR), modifying structures
to be part of drm_i915_private and have a provision to add display related
structs like intel_dp.
Also, aligning with frontbuffer tracking mechanism, the new structure
contains data for busy frontbuffer bits.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 32 ++++++++++++++++++-------
drivers/gpu/drm/i915/intel_dp.c | 50 ++++++++++++++++++----------------------
drivers/gpu/drm/i915/intel_drv.h | 18 ---------------
3 files changed, 47 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f771af..ed368ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -771,11 +771,33 @@ struct i915_fbc {
} no_fbc_reason;
};
-struct i915_drrs {
- struct intel_connector *connector;
+/**
+ * HIGH_RR is the highest eDP panel refresh rate read from EDID
+ * LOW_RR is the lowest eDP panel refresh rate found from EDID
+ * parsing for same resolution.
+ */
+enum drrs_refresh_rate_type {
+ DRRS_HIGH_RR,
+ DRRS_LOW_RR,
+ DRRS_MAX_RR, /* RR count */
+};
+
+enum drrs_support_type {
+ DRRS_NOT_SUPPORTED = 0,
+ STATIC_DRRS_SUPPORT = 1,
+ SEAMLESS_DRRS_SUPPORT = 2
};
struct intel_dp;
+struct i915_drrs {
+ struct mutex mutex;
+ struct delayed_work work;
+ struct intel_dp *dp;
+ unsigned busy_frontbuffer_bits;
+ enum drrs_refresh_rate_type refresh_rate_type;
+ enum drrs_support_type type;
+};
+
struct i915_psr {
struct mutex lock;
bool sink_support;
@@ -1354,12 +1376,6 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
};
-enum drrs_support_type {
- DRRS_NOT_SUPPORTED = 0,
- STATIC_DRRS_SUPPORT = 1,
- SEAMLESS_DRRS_SUPPORT = 2
-};
-
enum psr_lines_to_wait {
PSR_0_LINES_TO_WAIT = 0,
PSR_1_LINE_TO_WAIT,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 88d81a8..778dcd0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1269,7 +1269,7 @@ found:
&pipe_config->dp_m_n);
if (intel_connector->panel.downclock_mode != NULL &&
- intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
pipe_config->has_drrs = true;
intel_link_compute_m_n(bpp, lane_count,
intel_connector->panel.downclock_mode->clock,
@@ -4745,24 +4745,24 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_READ(pp_div_reg));
}
-void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder;
- struct intel_dp *intel_dp = NULL;
+ struct intel_digital_port *dig_port = NULL;
+ struct intel_dp *intel_dp = dev_priv->drrs.dp;
struct intel_crtc_config *config = NULL;
struct intel_crtc *intel_crtc = NULL;
- struct intel_connector *intel_connector = dev_priv->drrs.connector;
u32 reg, val;
- enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
+ enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
if (refresh_rate <= 0) {
DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
return;
}
- if (intel_connector == NULL) {
- DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
+ if (intel_dp == NULL) {
+ DRM_DEBUG_KMS("DRRS not supported.\n");
return;
}
@@ -4771,8 +4771,8 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
* platforms that cannot have PSR and DRRS enabled at the same time.
*/
- encoder = intel_attached_encoder(&intel_connector->base);
- intel_dp = enc_to_intel_dp(&encoder->base);
+ dig_port = dp_to_dig_port(intel_dp);
+ encoder = &dig_port->base;
intel_crtc = encoder->new_crtc;
if (!intel_crtc) {
@@ -4782,15 +4782,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
config = &intel_crtc->config;
- if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
+ if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
return;
}
- if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
+ if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
+ refresh_rate)
index = DRRS_LOW_RR;
- if (index == intel_dp->drrs_state.refresh_rate_type) {
+ if (index == dev_priv->drrs.refresh_rate_type) {
DRM_DEBUG_KMS(
"DRRS requested for previously set RR...ignoring\n");
return;
@@ -4820,23 +4821,21 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
* possible calls from user space to set differnt RR are made.
*/
- mutex_lock(&intel_dp->drrs_state.mutex);
+ mutex_lock(&dev_priv->drrs.mutex);
- intel_dp->drrs_state.refresh_rate_type = index;
+ dev_priv->drrs.refresh_rate_type = index;
- mutex_unlock(&intel_dp->drrs_state.mutex);
+ mutex_unlock(&dev_priv->drrs.mutex);
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}
static struct drm_display_mode *
-intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
- struct intel_connector *intel_connector,
- struct drm_display_mode *fixed_mode)
+intel_dp_drrs_init(struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
{
struct drm_connector *connector = &intel_connector->base;
- struct intel_dp *intel_dp = &intel_dig_port->dp;
- struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *downclock_mode = NULL;
@@ -4858,13 +4857,11 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
return NULL;
}
- dev_priv->drrs.connector = intel_connector;
-
- mutex_init(&intel_dp->drrs_state.mutex);
+ mutex_init(&dev_priv->drrs.mutex);
- intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+ dev_priv->drrs.type = dev_priv->vbt.drrs_type;
- intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
return downclock_mode;
}
@@ -4884,7 +4881,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct edid *edid;
enum pipe pipe = INVALID_PIPE;
- intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+ dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
if (!is_edp(intel_dp))
return true;
@@ -4933,7 +4930,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
- intel_dig_port,
intel_connector, fixed_mode);
break;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bb871f3..2ba045d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -566,17 +566,6 @@ struct intel_hdmi {
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS 0x10
-/**
- * HIGH_RR is the highest eDP panel refresh rate read from EDID
- * LOW_RR is the lowest eDP panel refresh rate found from EDID
- * parsing for same resolution.
- */
-enum edp_drrs_refresh_rate_type {
- DRRS_HIGH_RR,
- DRRS_LOW_RR,
- DRRS_MAX_RR, /* RR count */
-};
-
struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -632,12 +621,6 @@ struct intel_dp {
bool has_aux_irq,
int send_bytes,
uint32_t aux_clock_divider);
- struct {
- enum drrs_support_type type;
- enum edp_drrs_refresh_rate_type refresh_rate_type;
- struct mutex mutex;
- } drrs_state;
-
};
struct intel_digital_port {
@@ -1006,7 +989,6 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp);
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp);
-void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
--
2.0.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 1/10] drm/i915: Modifying structures related to DRRS
2015-01-09 20:55 ` [PATCH 1/10] drm/i915: Modifying structures related to DRRS Vandana Kannan
@ 2015-01-14 1:27 ` Rodrigo Vivi
2015-01-22 6:48 ` Daniel Vetter
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-14 1:27 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
I believe we could start this re-org by moving it out to intel_drrs.c
renaming functions and adding entry docbook entry.
But anyway this patch is right and doesn't seem to change anything
that is already working so free free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
I'll continue the reviews tomorrow and intend to finish by Thursday.
I'll also resend 2 patches that had conflicts with latest -nightly...
On Fri, Jan 9, 2015 at 12:55 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> Earlier, DRRS structures were specific to eDP (used only in intel_dp).
> Since DRRS can be extended to other internal display types
> (if the panel supports multiple RR), modifying structures
> to be part of drm_i915_private and have a provision to add display related
> structs like intel_dp.
> Also, aligning with frontbuffer tracking mechanism, the new structure
> contains data for busy frontbuffer bits.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 32 ++++++++++++++++++-------
> drivers/gpu/drm/i915/intel_dp.c | 50 ++++++++++++++++++----------------------
> drivers/gpu/drm/i915/intel_drv.h | 18 ---------------
> 3 files changed, 47 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8f771af..ed368ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -771,11 +771,33 @@ struct i915_fbc {
> } no_fbc_reason;
> };
>
> -struct i915_drrs {
> - struct intel_connector *connector;
> +/**
> + * HIGH_RR is the highest eDP panel refresh rate read from EDID
> + * LOW_RR is the lowest eDP panel refresh rate found from EDID
> + * parsing for same resolution.
> + */
> +enum drrs_refresh_rate_type {
> + DRRS_HIGH_RR,
> + DRRS_LOW_RR,
> + DRRS_MAX_RR, /* RR count */
> +};
> +
> +enum drrs_support_type {
> + DRRS_NOT_SUPPORTED = 0,
> + STATIC_DRRS_SUPPORT = 1,
> + SEAMLESS_DRRS_SUPPORT = 2
> };
>
> struct intel_dp;
> +struct i915_drrs {
> + struct mutex mutex;
> + struct delayed_work work;
> + struct intel_dp *dp;
> + unsigned busy_frontbuffer_bits;
> + enum drrs_refresh_rate_type refresh_rate_type;
> + enum drrs_support_type type;
> +};
> +
> struct i915_psr {
> struct mutex lock;
> bool sink_support;
> @@ -1354,12 +1376,6 @@ struct ddi_vbt_port_info {
> uint8_t supports_dp:1;
> };
>
> -enum drrs_support_type {
> - DRRS_NOT_SUPPORTED = 0,
> - STATIC_DRRS_SUPPORT = 1,
> - SEAMLESS_DRRS_SUPPORT = 2
> -};
> -
> enum psr_lines_to_wait {
> PSR_0_LINES_TO_WAIT = 0,
> PSR_1_LINE_TO_WAIT,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 88d81a8..778dcd0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1269,7 +1269,7 @@ found:
> &pipe_config->dp_m_n);
>
> if (intel_connector->panel.downclock_mode != NULL &&
> - intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
> + dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
> pipe_config->has_drrs = true;
> intel_link_compute_m_n(bpp, lane_count,
> intel_connector->panel.downclock_mode->clock,
> @@ -4745,24 +4745,24 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> I915_READ(pp_div_reg));
> }
>
> -void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> +static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *encoder;
> - struct intel_dp *intel_dp = NULL;
> + struct intel_digital_port *dig_port = NULL;
> + struct intel_dp *intel_dp = dev_priv->drrs.dp;
> struct intel_crtc_config *config = NULL;
> struct intel_crtc *intel_crtc = NULL;
> - struct intel_connector *intel_connector = dev_priv->drrs.connector;
> u32 reg, val;
> - enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
> + enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>
> if (refresh_rate <= 0) {
> DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
> return;
> }
>
> - if (intel_connector == NULL) {
> - DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
> + if (intel_dp == NULL) {
> + DRM_DEBUG_KMS("DRRS not supported.\n");
> return;
> }
>
> @@ -4771,8 +4771,8 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> * platforms that cannot have PSR and DRRS enabled at the same time.
> */
>
> - encoder = intel_attached_encoder(&intel_connector->base);
> - intel_dp = enc_to_intel_dp(&encoder->base);
> + dig_port = dp_to_dig_port(intel_dp);
> + encoder = &dig_port->base;
> intel_crtc = encoder->new_crtc;
>
> if (!intel_crtc) {
> @@ -4782,15 +4782,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>
> config = &intel_crtc->config;
>
> - if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
> + if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
> return;
> }
>
> - if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
> + if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
> + refresh_rate)
> index = DRRS_LOW_RR;
>
> - if (index == intel_dp->drrs_state.refresh_rate_type) {
> + if (index == dev_priv->drrs.refresh_rate_type) {
> DRM_DEBUG_KMS(
> "DRRS requested for previously set RR...ignoring\n");
> return;
> @@ -4820,23 +4821,21 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> * possible calls from user space to set differnt RR are made.
> */
>
> - mutex_lock(&intel_dp->drrs_state.mutex);
> + mutex_lock(&dev_priv->drrs.mutex);
>
> - intel_dp->drrs_state.refresh_rate_type = index;
> + dev_priv->drrs.refresh_rate_type = index;
>
> - mutex_unlock(&intel_dp->drrs_state.mutex);
> + mutex_unlock(&dev_priv->drrs.mutex);
>
> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> }
>
> static struct drm_display_mode *
> -intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
> - struct intel_connector *intel_connector,
> - struct drm_display_mode *fixed_mode)
> +intel_dp_drrs_init(struct intel_connector *intel_connector,
> + struct drm_display_mode *fixed_mode)
> {
> struct drm_connector *connector = &intel_connector->base;
> - struct intel_dp *intel_dp = &intel_dig_port->dp;
> - struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_display_mode *downclock_mode = NULL;
>
> @@ -4858,13 +4857,11 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
> return NULL;
> }
>
> - dev_priv->drrs.connector = intel_connector;
> -
> - mutex_init(&intel_dp->drrs_state.mutex);
> + mutex_init(&dev_priv->drrs.mutex);
>
> - intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
> + dev_priv->drrs.type = dev_priv->vbt.drrs_type;
>
> - intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
> + dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
> DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
> return downclock_mode;
> }
> @@ -4884,7 +4881,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct edid *edid;
> enum pipe pipe = INVALID_PIPE;
>
> - intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
> + dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
>
> if (!is_edp(intel_dp))
> return true;
> @@ -4933,7 +4930,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
> fixed_mode = drm_mode_duplicate(dev, scan);
> downclock_mode = intel_dp_drrs_init(
> - intel_dig_port,
> intel_connector, fixed_mode);
> break;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index bb871f3..2ba045d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -566,17 +566,6 @@ struct intel_hdmi {
> struct intel_dp_mst_encoder;
> #define DP_MAX_DOWNSTREAM_PORTS 0x10
>
> -/**
> - * HIGH_RR is the highest eDP panel refresh rate read from EDID
> - * LOW_RR is the lowest eDP panel refresh rate found from EDID
> - * parsing for same resolution.
> - */
> -enum edp_drrs_refresh_rate_type {
> - DRRS_HIGH_RR,
> - DRRS_LOW_RR,
> - DRRS_MAX_RR, /* RR count */
> -};
> -
> struct intel_dp {
> uint32_t output_reg;
> uint32_t aux_ch_ctl_reg;
> @@ -632,12 +621,6 @@ struct intel_dp {
> bool has_aux_irq,
> int send_bytes,
> uint32_t aux_clock_divider);
> - struct {
> - enum drrs_support_type type;
> - enum edp_drrs_refresh_rate_type refresh_rate_type;
> - struct mutex mutex;
> - } drrs_state;
> -
> };
>
> struct intel_digital_port {
> @@ -1006,7 +989,6 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp);
> void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
> void intel_edp_panel_on(struct intel_dp *intel_dp);
> void intel_edp_panel_off(struct intel_dp *intel_dp);
> -void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
> void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
> void intel_dp_mst_suspend(struct drm_device *dev);
> void intel_dp_mst_resume(struct drm_device *dev);
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 1/10] drm/i915: Modifying structures related to DRRS
2015-01-14 1:27 ` Rodrigo Vivi
@ 2015-01-22 6:48 ` Daniel Vetter
2015-01-22 11:35 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Daniel Vetter @ 2015-01-22 6:48 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Vivi, Rodrigo, Paulo Zanoni
On Tue, Jan 13, 2015 at 05:27:01PM -0800, Rodrigo Vivi wrote:
> I believe we could start this re-org by moving it out to intel_drrs.c
> renaming functions and adding entry docbook entry.
>
> But anyway this patch is right and doesn't seem to change anything
> that is already working so free free to use:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> I'll continue the reviews tomorrow and intend to finish by Thursday.
> I'll also resend 2 patches that had conflicts with latest -nightly...
I merged this, but it causes a compiler warning. Which means I need the
revised patches to get this all into shape asap or need to drop the patch
again.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 1/10] drm/i915: Modifying structures related to DRRS
2015-01-22 6:48 ` Daniel Vetter
@ 2015-01-22 11:35 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 11:35 UTC (permalink / raw)
To: Daniel Vetter, Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
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On Thursday 22 January 2015 12:18 PM, Daniel Vetter wrote:
> On Tue, Jan 13, 2015 at 05:27:01PM -0800, Rodrigo Vivi wrote:
>> I believe we could start this re-org by moving it out to intel_drrs.c
>> renaming functions and adding entry docbook entry.
>>
>> But anyway this patch is right and doesn't seem to change anything
>> that is already working so free free to use:
>>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> I'll continue the reviews tomorrow and intend to finish by Thursday.
>> I'll also resend 2 patches that had conflicts with latest -nightly...
> I merged this, but it causes a compiler warning. Which means I need the
> revised patches to get this all into shape asap or need to drop the patch
> again.
I have just shared a new patches for the changes suggested except for
igt and related
debugfs entry patches [ 9 and 10]. Working on the required changes for
igt and the
debugfs interface. But I hope the changes required for igt need not stop
other
patches [1 to 8 of 10 patches].
> -Daniel
--Ram
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 2/10] drm/i915: Initialize DRRS delayed work
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
2015-01-09 20:55 ` [PATCH 1/10] drm/i915: Modifying structures related to DRRS Vandana Kannan
@ 2015-01-09 20:55 ` Vandana Kannan
2015-01-11 12:52 ` Chris Wilson
2015-01-09 20:55 ` [PATCH 3/10] drm/i915: Enable/disable DRRS Vandana Kannan
` (7 subsequent siblings)
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Add DRRS work function to trigger a switch to low refresh rate when activity
is detected on screen.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 36 ++++++++++++++++++++++++++++--------
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 778dcd0..30b3aa1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4814,20 +4814,38 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
I915_WRITE(reg, val);
}
+ dev_priv->drrs.refresh_rate_type = index;
+
+ DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+}
+
+static void intel_edp_drrs_work(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), drrs.work.work);
+ struct intel_dp *intel_dp = dev_priv->drrs.dp;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ if (!intel_dp)
+ goto unlock;
+
/*
- * mutex taken to ensure that there is no race between differnt
- * drrs calls trying to update refresh rate. This scenario may occur
- * in future when idleness detection based DRRS in kernel and
- * possible calls from user space to set differnt RR are made.
+ * The delayed work can race with an invalidate hence we need to
+ * recheck.
*/
- mutex_lock(&dev_priv->drrs.mutex);
+ if (dev_priv->drrs.busy_frontbuffer_bits)
+ goto unlock;
- dev_priv->drrs.refresh_rate_type = index;
+ if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv->dev,
+ intel_dp->attached_connector->panel.
+ downclock_mode->vrefresh);
- mutex_unlock(&dev_priv->drrs.mutex);
+unlock:
- DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+ mutex_unlock(&dev_priv->drrs.mutex);
}
static struct drm_display_mode *
@@ -4857,6 +4875,8 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
return NULL;
}
+ INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_work);
+
mutex_init(&dev_priv->drrs.mutex);
dev_priv->drrs.type = dev_priv->vbt.drrs_type;
--
2.0.1
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 2/10] drm/i915: Initialize DRRS delayed work
2015-01-09 20:55 ` [PATCH 2/10] drm/i915: Initialize DRRS delayed work Vandana Kannan
@ 2015-01-11 12:52 ` Chris Wilson
2015-01-21 11:04 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Chris Wilson @ 2015-01-11 12:52 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi
On Sat, Jan 10, 2015 at 02:25:57AM +0530, Vandana Kannan wrote:
> Add DRRS work function to trigger a switch to low refresh rate when activity
> is detected on screen.
Where is this function used? How can I judge that it does the right
thing?
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 36 ++++++++++++++++++++++++++++--------
> 1 file changed, 28 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 778dcd0..30b3aa1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4814,20 +4814,38 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> I915_WRITE(reg, val);
> }
>
> + dev_priv->drrs.refresh_rate_type = index;
> +
> + DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> +}
> +
> +static void intel_edp_drrs_work(struct work_struct *work)
intel_edp_drrs_downclock_work() would be more self-descriptive
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(work, typeof(*dev_priv), drrs.work.work);
> + struct intel_dp *intel_dp = dev_priv->drrs.dp;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + if (!intel_dp)
> + goto unlock;
Does dev_priv->drrs.mutex not also protect dev_priv->drrs.dp?
> +
> /*
> - * mutex taken to ensure that there is no race between differnt
> - * drrs calls trying to update refresh rate. This scenario may occur
> - * in future when idleness detection based DRRS in kernel and
> - * possible calls from user space to set differnt RR are made.
> + * The delayed work can race with an invalidate hence we need to
> + * recheck.
> */
This comment no longer applies to all the other callers of
intel_dp_set_drrs_state()? Or did you miss adding the
lockdep_assert_held(&dev_priv->drrs.mutex)?
> - mutex_lock(&dev_priv->drrs.mutex);
> + if (dev_priv->drrs.busy_frontbuffer_bits)
> + goto unlock;
>
> - dev_priv->drrs.refresh_rate_type = index;
> + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv->dev,
Would it not be sensible for intel_dp_set_drrs_state() check for the
no-op itself?
> + intel_dp->attached_connector->panel.
> + downclock_mode->vrefresh);
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 2/10] drm/i915: Initialize DRRS delayed work
2015-01-11 12:52 ` Chris Wilson
@ 2015-01-21 11:04 ` Ramalingam C
2015-01-22 9:44 ` [PATCH] " Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 11:04 UTC (permalink / raw)
To: Chris Wilson, Vandana Kannan, intel-gfx, paulo.r.zanoni,
rodrigo.vivi
[-- Attachment #1.1: Type: text/plain, Size: 3688 bytes --]
Hi chris
On Sunday 11 January 2015 06:22 PM, Chris Wilson wrote:
> On Sat, Jan 10, 2015 at 02:25:57AM +0530, Vandana Kannan wrote:
>> Add DRRS work function to trigger a switch to low refresh rate when activity
>> is detected on screen.
> Where is this function used? How can I judge that it does the right
> thing?
Thanks for catching this. There is an error in the commit message. This
DRRS work function
will trigger a switch to low refresh rate, when there is no activity on
the screen for more than 1 sec.
And this function is set as a deferred work from intel_edp_drrs_flush().
Functionality of this function can be verified from the debug logs in
dmesg (lower refresh rate set
will be printed out). Addition to that I am working to enable a debugfs
to share the refreshrate
switch info also for the debugging/testing purpose.
>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 36 ++++++++++++++++++++++++++++--------
>> 1 file changed, 28 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 778dcd0..30b3aa1 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4814,20 +4814,38 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> I915_WRITE(reg, val);
>> }
>>
>> + dev_priv->drrs.refresh_rate_type = index;
>> +
>> + DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
>> +}
>> +
>> +static void intel_edp_drrs_work(struct work_struct *work)
> intel_edp_drrs_downclock_work() would be more self-descriptive
Agreed. I will rename it in next iteration
>
>> +{
>> + struct drm_i915_private *dev_priv =
>> + container_of(work, typeof(*dev_priv), drrs.work.work);
>> + struct intel_dp *intel_dp = dev_priv->drrs.dp;
>> +
>> + mutex_lock(&dev_priv->drrs.mutex);
>> +
>> + if (!intel_dp)
>> + goto unlock;
> Does dev_priv->drrs.mutex not also protect dev_priv->drrs.dp?
It should have protected. Will cover drrs.dp with drrs.mutex in next patch
>> +
>> /*
>> - * mutex taken to ensure that there is no race between differnt
>> - * drrs calls trying to update refresh rate. This scenario may occur
>> - * in future when idleness detection based DRRS in kernel and
>> - * possible calls from user space to set differnt RR are made.
>> + * The delayed work can race with an invalidate hence we need to
>> + * recheck.
>> */
> This comment no longer applies to all the other callers of
> intel_dp_set_drrs_state()? Or did you miss adding the
> lockdep_assert_held(&dev_priv->drrs.mutex)?
This comment was added considering the requests from userspace for new
refreshrates.
But a part of MIPI DRRS and media playback DRRS implementation
(currently in development),
I am addressing the possible race condition. So at this point in time
this comment is irrelevant,
hence vandana removed it.
>
>> - mutex_lock(&dev_priv->drrs.mutex);
>> + if (dev_priv->drrs.busy_frontbuffer_bits)
>> + goto unlock;
>>
>> - dev_priv->drrs.refresh_rate_type = index;
>> + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
>> + intel_dp_set_drrs_state(dev_priv->dev,
> Would it not be sensible for intel_dp_set_drrs_state() check for the
> no-op itself?
If refresh_rate_type is already LOW_RR then we should exit the work
function with no call to intel_dp_set_drrs_state().
Thats the reason the call is kept under the if condition.
intel_dp_set_drrs_state() already handles if the
requested vrefresh is same as the vrefresh of the current refresh_rate type.
>
>> + intel_dp->attached_connector->panel.
>> + downclock_mode->vrefresh);
> -Chris
>
-Ram
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^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915: Initialize DRRS delayed work
2015-01-21 11:04 ` Ramalingam C
@ 2015-01-22 9:44 ` Ramalingam C
2015-01-23 23:24 ` Rodrigo Vivi
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 9:44 UTC (permalink / raw)
To: intel-gfx, chris, paulo.r.zanoni, rodrigo.vivi
From: Vandana Kannan <vandana.kannan@intel.com>
Add DRRS work function to trigger a switch to low refresh rate,
when no activity is detected on screen till 1 sec duration.
v2: [By Ram]: drrs.dp also protected with drrs.mutex and worker function
is renamed to intel_edp_drrs_downclock_work [Rodrigo]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++--------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b38d737..c066560 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4815,20 +4815,40 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
I915_WRITE(reg, val);
}
+ dev_priv->drrs.refresh_rate_type = index;
+
+ DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+}
+
+static void intel_edp_drrs_downclock_work(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), drrs.work.work);
+ struct intel_dp *intel_dp;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+
+ intel_dp = dev_priv->drrs.dp;
+
+ if (!intel_dp)
+ goto unlock;
+
/*
- * mutex taken to ensure that there is no race between differnt
- * drrs calls trying to update refresh rate. This scenario may occur
- * in future when idleness detection based DRRS in kernel and
- * possible calls from user space to set differnt RR are made.
+ * The delayed work can race with an invalidate hence we need to
+ * recheck.
*/
- mutex_lock(&dev_priv->drrs.mutex);
+ if (dev_priv->drrs.busy_frontbuffer_bits)
+ goto unlock;
- dev_priv->drrs.refresh_rate_type = index;
+ if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv->dev,
+ intel_dp->attached_connector->panel.
+ downclock_mode->vrefresh);
- mutex_unlock(&dev_priv->drrs.mutex);
+unlock:
- DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+ mutex_unlock(&dev_priv->drrs.mutex);
}
static struct drm_display_mode *
@@ -4858,6 +4878,8 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
return NULL;
}
+ INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
+
mutex_init(&dev_priv->drrs.mutex);
dev_priv->drrs.type = dev_priv->vbt.drrs_type;
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Initialize DRRS delayed work
2015-01-22 9:44 ` [PATCH] " Ramalingam C
@ 2015-01-23 23:24 ` Rodrigo Vivi
0 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-23 23:24 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, Vivi, Rodrigo, Paulo Zanoni
On Thu, Jan 22, 2015 at 1:44 AM, Ramalingam C <ramalingam.c@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Add DRRS work function to trigger a switch to low refresh rate,
> when no activity is detected on screen till 1 sec duration.
>
> v2: [By Ram]: drrs.dp also protected with drrs.mutex and worker function
> is renamed to intel_edp_drrs_downclock_work [Rodrigo]
Actually comments accepted on v2 came from Chris, not from me.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++--------
> 1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b38d737..c066560 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4815,20 +4815,40 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> I915_WRITE(reg, val);
> }
>
> + dev_priv->drrs.refresh_rate_type = index;
> +
> + DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> +}
> +
> +static void intel_edp_drrs_downclock_work(struct work_struct *work)
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(work, typeof(*dev_priv), drrs.work.work);
> + struct intel_dp *intel_dp;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> +
> + intel_dp = dev_priv->drrs.dp;
> +
> + if (!intel_dp)
> + goto unlock;
> +
> /*
> - * mutex taken to ensure that there is no race between differnt
> - * drrs calls trying to update refresh rate. This scenario may occur
> - * in future when idleness detection based DRRS in kernel and
> - * possible calls from user space to set differnt RR are made.
> + * The delayed work can race with an invalidate hence we need to
> + * recheck.
> */
>
> - mutex_lock(&dev_priv->drrs.mutex);
> + if (dev_priv->drrs.busy_frontbuffer_bits)
> + goto unlock;
>
> - dev_priv->drrs.refresh_rate_type = index;
> + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv->dev,
> + intel_dp->attached_connector->panel.
> + downclock_mode->vrefresh);
>
> - mutex_unlock(&dev_priv->drrs.mutex);
> +unlock:
>
> - DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> + mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> static struct drm_display_mode *
> @@ -4858,6 +4878,8 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
> return NULL;
> }
>
> + INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
> +
> mutex_init(&dev_priv->drrs.mutex);
>
> dev_priv->drrs.type = dev_priv->vbt.drrs_type;
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Anyway seems ok to me now:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 3/10] drm/i915: Enable/disable DRRS
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
2015-01-09 20:55 ` [PATCH 1/10] drm/i915: Modifying structures related to DRRS Vandana Kannan
2015-01-09 20:55 ` [PATCH 2/10] drm/i915: Initialize DRRS delayed work Vandana Kannan
@ 2015-01-09 20:55 ` Vandana Kannan
2015-01-15 22:46 ` Rodrigo Vivi
2015-01-09 20:55 ` [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer Vandana Kannan
` (6 subsequent siblings)
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Calling enable/disable DRRS when enable/disable DDI are called.
These functions are responsible for setup of drrs data (in enable) and
reset of drrs (in disable).
has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
the VBT. A check has been added for has_drrs in these functions, to make
sure the functions go through only if DRRS will work on the platform with
the attached panel.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 54 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1c92ad4..c704434 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1605,6 +1605,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
intel_edp_backlight_on(intel_dp);
intel_psr_enable(intel_dp);
+ intel_edp_drrs_enable(intel_dp);
}
if (intel_crtc->config.has_audio) {
@@ -1630,6 +1631,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_drrs_disable(intel_dp);
intel_psr_disable(intel_dp);
intel_edp_backlight_off(intel_dp);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 30b3aa1..5e7dc7b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4819,6 +4819,60 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}
+void intel_edp_drrs_enable(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_crtc *crtc = dig_port->base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (!intel_crtc->config.has_drrs) {
+ DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
+ return;
+ }
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ if (dev_priv->drrs.dp) {
+ DRM_DEBUG_KMS("DRRS already enabled\n");
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ dev_priv->drrs.busy_frontbuffer_bits = 0;
+
+ dev_priv->drrs.dp = intel_dp;
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+void intel_edp_drrs_disable(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_crtc *crtc = dig_port->base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (!intel_crtc->config.has_drrs)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ if (!dev_priv->drrs.dp) {
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv->dev,
+ intel_dp->attached_connector->panel.
+ fixed_mode->vrefresh);
+
+ dev_priv->drrs.dp = NULL;
+ mutex_unlock(&dev_priv->drrs.mutex);
+
+ cancel_delayed_work_sync(&dev_priv->drrs.work);
+}
+
static void intel_edp_drrs_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2ba045d..6f3ad3b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1003,6 +1003,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
int intel_disable_plane(struct drm_plane *plane);
+void intel_edp_drrs_enable(struct intel_dp *intel_dp);
+void intel_edp_drrs_disable(struct intel_dp *intel_dp);
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
--
2.0.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 3/10] drm/i915: Enable/disable DRRS
2015-01-09 20:55 ` [PATCH 3/10] drm/i915: Enable/disable DRRS Vandana Kannan
@ 2015-01-15 22:46 ` Rodrigo Vivi
2015-01-21 11:15 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 22:46 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Fri, Jan 9, 2015 at 12:55 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> Calling enable/disable DRRS when enable/disable DDI are called.
> These functions are responsible for setup of drrs data (in enable) and
> reset of drrs (in disable).
> has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
> the VBT. A check has been added for has_drrs in these functions, to make
> sure the functions go through only if DRRS will work on the platform with
> the attached panel.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/intel_dp.c | 54 ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1c92ad4..c704434 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1605,6 +1605,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
>
> intel_edp_backlight_on(intel_dp);
> intel_psr_enable(intel_dp);
> + intel_edp_drrs_enable(intel_dp);
> }
>
> if (intel_crtc->config.has_audio) {
> @@ -1630,6 +1631,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> + intel_edp_drrs_disable(intel_dp);
> intel_psr_disable(intel_dp);
> intel_edp_backlight_off(intel_dp);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 30b3aa1..5e7dc7b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4819,6 +4819,60 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> }
>
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config.has_drrs) {
> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
> + return;
> + }
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (dev_priv->drrs.dp) {
> + DRM_DEBUG_KMS("DRRS already enabled\n");
Although I'm in favor of reducing WARNS I have to ask: should be a warn_on here?
> + mutex_unlock(&dev_priv->drrs.mutex);
goto unlock?
> + return;
> + }
> +
> + dev_priv->drrs.busy_frontbuffer_bits = 0;
> +
> + dev_priv->drrs.dp = intel_dp;
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config.has_drrs)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (!dev_priv->drrs.dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv->dev,
> + intel_dp->attached_connector->panel.
> + fixed_mode->vrefresh);
> +
> + dev_priv->drrs.dp = NULL;
> + mutex_unlock(&dev_priv->drrs.mutex);
> +
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> +}
> +
> static void intel_edp_drrs_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 2ba045d..6f3ad3b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1003,6 +1003,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> uint32_t src_x, uint32_t src_y,
> uint32_t src_w, uint32_t src_h);
> int intel_disable_plane(struct drm_plane *plane);
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp);
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp);
This causes conflict on nightly. There is a rebased version at:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=review-drrs
>
> /* intel_dp_mst.c */
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
with or without bikesheds in place feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
as
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 3/10] drm/i915: Enable/disable DRRS
2015-01-15 22:46 ` Rodrigo Vivi
@ 2015-01-21 11:15 ` Ramalingam C
2015-01-22 9:47 ` [PATCH] " Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 11:15 UTC (permalink / raw)
To: Rodrigo Vivi, Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
[-- Attachment #1.1: Type: text/plain, Size: 5661 bytes --]
On Friday 16 January 2015 04:16 AM, Rodrigo Vivi wrote:
> On Fri, Jan 9, 2015 at 12:55 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
>> Calling enable/disable DRRS when enable/disable DDI are called.
>> These functions are responsible for setup of drrs data (in enable) and
>> reset of drrs (in disable).
>> has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
>> the VBT. A check has been added for has_drrs in these functions, to make
>> sure the functions go through only if DRRS will work on the platform with
>> the attached panel.
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
>> drivers/gpu/drm/i915/intel_dp.c | 54 ++++++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 3 files changed, 58 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 1c92ad4..c704434 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1605,6 +1605,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
>>
>> intel_edp_backlight_on(intel_dp);
>> intel_psr_enable(intel_dp);
>> + intel_edp_drrs_enable(intel_dp);
>> }
>>
>> if (intel_crtc->config.has_audio) {
>> @@ -1630,6 +1631,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>> if (type == INTEL_OUTPUT_EDP) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> + intel_edp_drrs_disable(intel_dp);
>> intel_psr_disable(intel_dp);
>> intel_edp_backlight_off(intel_dp);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 30b3aa1..5e7dc7b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4819,6 +4819,60 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
>> }
>>
>> +void intel_edp_drrs_enable(struct intel_dp *intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_crtc *crtc = dig_port->base.base.crtc;
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> + if (!intel_crtc->config.has_drrs) {
>> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
>> + return;
>> + }
>> +
>> + mutex_lock(&dev_priv->drrs.mutex);
>> + if (dev_priv->drrs.dp) {
>> + DRM_DEBUG_KMS("DRRS already enabled\n");
> Although I'm in favor of reducing WARNS I have to ask: should be a warn_on here?
Yes, Thats correct. we should give a warning message for repeated enable
call.
>
>> + mutex_unlock(&dev_priv->drrs.mutex);
> goto unlock?
Could avoid the repeated mutex_unlock. We will go with that.
>> + return;
>> + }
>> +
>> + dev_priv->drrs.busy_frontbuffer_bits = 0;
>> +
>> + dev_priv->drrs.dp = intel_dp;
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> +}
>> +
>> +void intel_edp_drrs_disable(struct intel_dp *intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_crtc *crtc = dig_port->base.base.crtc;
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> + if (!intel_crtc->config.has_drrs)
>> + return;
>> +
>> + mutex_lock(&dev_priv->drrs.mutex);
>> + if (!dev_priv->drrs.dp) {
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> + return;
>> + }
>> +
>> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
>> + intel_dp_set_drrs_state(dev_priv->dev,
>> + intel_dp->attached_connector->panel.
>> + fixed_mode->vrefresh);
>> +
>> + dev_priv->drrs.dp = NULL;
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> +
>> + cancel_delayed_work_sync(&dev_priv->drrs.work);
>> +}
>> +
>> static void intel_edp_drrs_work(struct work_struct *work)
>> {
>> struct drm_i915_private *dev_priv =
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 2ba045d..6f3ad3b 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1003,6 +1003,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>> uint32_t src_x, uint32_t src_y,
>> uint32_t src_w, uint32_t src_h);
>> int intel_disable_plane(struct drm_plane *plane);
>> +void intel_edp_drrs_enable(struct intel_dp *intel_dp);
>> +void intel_edp_drrs_disable(struct intel_dp *intel_dp);
> This causes conflict on nightly. There is a rebased version at:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=review-drrs
>
>> /* intel_dp_mst.c */
>> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>> --
>> 2.0.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> with or without bikesheds in place feel free to use:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
[-- Attachment #1.2: Type: text/html, Size: 7083 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915: Enable/disable DRRS
2015-01-21 11:15 ` Ramalingam C
@ 2015-01-22 9:47 ` Ramalingam C
2015-01-23 23:25 ` Rodrigo Vivi
2015-01-26 7:31 ` Daniel Vetter
0 siblings, 2 replies; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 9:47 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
Calling enable/disable DRRS when enable/disable DDI are called.
These functions are responsible for setup of drrs data (in enable) and
reset of drrs (in disable).
has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
the VBT. A check has been added for has_drrs in these functions, to make
sure the functions go through only if DRRS will work on the platform with
the attached panel.
V2: [By Ram]: WARN_ON is used when intel_edp_drrs_enable() is called more than
once [Rodrigo]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f10ec26..ad8b73d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1610,6 +1610,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
intel_edp_backlight_on(intel_dp);
intel_psr_enable(intel_dp);
+ intel_edp_drrs_enable(intel_dp);
}
if (intel_crtc->config->has_audio) {
@@ -1635,6 +1636,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
if (type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_drrs_disable(intel_dp);
intel_psr_disable(intel_dp);
intel_edp_backlight_off(intel_dp);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c066560..f843fe0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4820,6 +4820,61 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}
+void intel_edp_drrs_enable(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_crtc *crtc = dig_port->base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (!intel_crtc->config->has_drrs) {
+ DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
+ return;
+ }
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ if (WARN_ON(dev_priv->drrs.dp)) {
+ DRM_ERROR("DRRS already enabled\n");
+ goto unlock;
+ }
+
+ dev_priv->drrs.busy_frontbuffer_bits = 0;
+
+ dev_priv->drrs.dp = intel_dp;
+
+unlock:
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+void intel_edp_drrs_disable(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_crtc *crtc = dig_port->base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (!intel_crtc->config->has_drrs)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ if (!dev_priv->drrs.dp) {
+ mutex_unlock(&dev_priv->drrs.mutex);
+ return;
+ }
+
+ if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ intel_dp_set_drrs_state(dev_priv->dev,
+ intel_dp->attached_connector->panel.
+ fixed_mode->vrefresh);
+
+ dev_priv->drrs.dp = NULL;
+ mutex_unlock(&dev_priv->drrs.mutex);
+
+ cancel_delayed_work_sync(&dev_priv->drrs.work);
+}
+
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e957d4d..5a14725 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1030,6 +1030,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_w, uint32_t src_h);
int intel_disable_plane(struct drm_plane *plane);
void intel_plane_destroy(struct drm_plane *plane);
+void intel_edp_drrs_enable(struct intel_dp *intel_dp);
+void intel_edp_drrs_disable(struct intel_dp *intel_dp);
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Enable/disable DRRS
2015-01-22 9:47 ` [PATCH] " Ramalingam C
@ 2015-01-23 23:25 ` Rodrigo Vivi
2015-01-26 7:31 ` Daniel Vetter
1 sibling, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-23 23:25 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
re Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Jan 22, 2015 at 1:47 AM, Ramalingam C <ramalingam.c@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Calling enable/disable DRRS when enable/disable DDI are called.
> These functions are responsible for setup of drrs data (in enable) and
> reset of drrs (in disable).
> has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
> the VBT. A check has been added for has_drrs in these functions, to make
> sure the functions go through only if DRRS will work on the platform with
> the attached panel.
>
> V2: [By Ram]: WARN_ON is used when intel_edp_drrs_enable() is called more than
> once [Rodrigo]
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 59 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f10ec26..ad8b73d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1610,6 +1610,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
>
> intel_edp_backlight_on(intel_dp);
> intel_psr_enable(intel_dp);
> + intel_edp_drrs_enable(intel_dp);
> }
>
> if (intel_crtc->config->has_audio) {
> @@ -1635,6 +1636,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> + intel_edp_drrs_disable(intel_dp);
> intel_psr_disable(intel_dp);
> intel_edp_backlight_off(intel_dp);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c066560..f843fe0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4820,6 +4820,61 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> }
>
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config->has_drrs) {
> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
> + return;
> + }
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (WARN_ON(dev_priv->drrs.dp)) {
> + DRM_ERROR("DRRS already enabled\n");
> + goto unlock;
> + }
> +
> + dev_priv->drrs.busy_frontbuffer_bits = 0;
> +
> + dev_priv->drrs.dp = intel_dp;
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config->has_drrs)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (!dev_priv->drrs.dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv->dev,
> + intel_dp->attached_connector->panel.
> + fixed_mode->vrefresh);
> +
> + dev_priv->drrs.dp = NULL;
> + mutex_unlock(&dev_priv->drrs.mutex);
> +
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> +}
> +
> static void intel_edp_drrs_downclock_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e957d4d..5a14725 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1030,6 +1030,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> uint32_t src_w, uint32_t src_h);
> int intel_disable_plane(struct drm_plane *plane);
> void intel_plane_destroy(struct drm_plane *plane);
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp);
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp);
>
> /* intel_dp_mst.c */
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Enable/disable DRRS
2015-01-22 9:47 ` [PATCH] " Ramalingam C
2015-01-23 23:25 ` Rodrigo Vivi
@ 2015-01-26 7:31 ` Daniel Vetter
2015-01-26 19:00 ` Rodrigo Vivi
1 sibling, 1 reply; 64+ messages in thread
From: Daniel Vetter @ 2015-01-26 7:31 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi
On Thu, Jan 22, 2015 at 03:17:40PM +0530, Ramalingam C wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Calling enable/disable DRRS when enable/disable DDI are called.
> These functions are responsible for setup of drrs data (in enable) and
> reset of drrs (in disable).
> has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
> the VBT. A check has been added for has_drrs in these functions, to make
> sure the functions go through only if DRRS will work on the platform with
> the attached panel.
>
> V2: [By Ram]: WARN_ON is used when intel_edp_drrs_enable() is called more than
> once [Rodrigo]
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Please be a bit more careful with adding sob lines - afaik Rodrigo did not
handle this patch. If you just want to get people's attention, please use
Cc: instead.
Fixed while applying.
-Daniel
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 59 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f10ec26..ad8b73d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1610,6 +1610,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
>
> intel_edp_backlight_on(intel_dp);
> intel_psr_enable(intel_dp);
> + intel_edp_drrs_enable(intel_dp);
> }
>
> if (intel_crtc->config->has_audio) {
> @@ -1635,6 +1636,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> + intel_edp_drrs_disable(intel_dp);
> intel_psr_disable(intel_dp);
> intel_edp_backlight_off(intel_dp);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c066560..f843fe0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4820,6 +4820,61 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> }
>
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config->has_drrs) {
> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
> + return;
> + }
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (WARN_ON(dev_priv->drrs.dp)) {
> + DRM_ERROR("DRRS already enabled\n");
> + goto unlock;
> + }
> +
> + dev_priv->drrs.busy_frontbuffer_bits = 0;
> +
> + dev_priv->drrs.dp = intel_dp;
> +
> +unlock:
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
> + if (!intel_crtc->config->has_drrs)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + if (!dev_priv->drrs.dp) {
> + mutex_unlock(&dev_priv->drrs.mutex);
> + return;
> + }
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
> + intel_dp_set_drrs_state(dev_priv->dev,
> + intel_dp->attached_connector->panel.
> + fixed_mode->vrefresh);
> +
> + dev_priv->drrs.dp = NULL;
> + mutex_unlock(&dev_priv->drrs.mutex);
> +
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> +}
> +
> static void intel_edp_drrs_downclock_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e957d4d..5a14725 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1030,6 +1030,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> uint32_t src_w, uint32_t src_h);
> int intel_disable_plane(struct drm_plane *plane);
> void intel_plane_destroy(struct drm_plane *plane);
> +void intel_edp_drrs_enable(struct intel_dp *intel_dp);
> +void intel_edp_drrs_disable(struct intel_dp *intel_dp);
>
> /* intel_dp_mst.c */
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Enable/disable DRRS
2015-01-26 7:31 ` Daniel Vetter
@ 2015-01-26 19:00 ` Rodrigo Vivi
0 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-26 19:00 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Sun, Jan 25, 2015 at 11:31 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Jan 22, 2015 at 03:17:40PM +0530, Ramalingam C wrote:
>> From: Vandana Kannan <vandana.kannan@intel.com>
>>
>> Calling enable/disable DRRS when enable/disable DDI are called.
>> These functions are responsible for setup of drrs data (in enable) and
>> reset of drrs (in disable).
>> has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
>> the VBT. A check has been added for has_drrs in these functions, to make
>> sure the functions go through only if DRRS will work on the platform with
>> the attached panel.
>>
>> V2: [By Ram]: WARN_ON is used when intel_edp_drrs_enable() is called more than
>> once [Rodrigo]
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Please be a bit more careful with adding sob lines - afaik Rodrigo did not
> handle this patch. If you just want to get people's attention, please use
> Cc: instead.
>
> Fixed while applying.
> -Daniel
that was actually my fault... I had fixed a rebase conflicted and
added to a drrs-review branch at cgit.
I signed-off but didn't increment the v2 explaining the rebase.
Thanks for merging.
>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 2 ++
>> drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 3 files changed, 59 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index f10ec26..ad8b73d 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1610,6 +1610,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
>>
>> intel_edp_backlight_on(intel_dp);
>> intel_psr_enable(intel_dp);
>> + intel_edp_drrs_enable(intel_dp);
>> }
>>
>> if (intel_crtc->config->has_audio) {
>> @@ -1635,6 +1636,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>> if (type == INTEL_OUTPUT_EDP) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> + intel_edp_drrs_disable(intel_dp);
>> intel_psr_disable(intel_dp);
>> intel_edp_backlight_off(intel_dp);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index c066560..f843fe0 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4820,6 +4820,61 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
>> }
>>
>> +void intel_edp_drrs_enable(struct intel_dp *intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_crtc *crtc = dig_port->base.base.crtc;
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> + if (!intel_crtc->config->has_drrs) {
>> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
>> + return;
>> + }
>> +
>> + mutex_lock(&dev_priv->drrs.mutex);
>> + if (WARN_ON(dev_priv->drrs.dp)) {
>> + DRM_ERROR("DRRS already enabled\n");
>> + goto unlock;
>> + }
>> +
>> + dev_priv->drrs.busy_frontbuffer_bits = 0;
>> +
>> + dev_priv->drrs.dp = intel_dp;
>> +
>> +unlock:
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> +}
>> +
>> +void intel_edp_drrs_disable(struct intel_dp *intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_crtc *crtc = dig_port->base.base.crtc;
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +
>> + if (!intel_crtc->config->has_drrs)
>> + return;
>> +
>> + mutex_lock(&dev_priv->drrs.mutex);
>> + if (!dev_priv->drrs.dp) {
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> + return;
>> + }
>> +
>> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
>> + intel_dp_set_drrs_state(dev_priv->dev,
>> + intel_dp->attached_connector->panel.
>> + fixed_mode->vrefresh);
>> +
>> + dev_priv->drrs.dp = NULL;
>> + mutex_unlock(&dev_priv->drrs.mutex);
>> +
>> + cancel_delayed_work_sync(&dev_priv->drrs.work);
>> +}
>> +
>> static void intel_edp_drrs_downclock_work(struct work_struct *work)
>> {
>> struct drm_i915_private *dev_priv =
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index e957d4d..5a14725 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1030,6 +1030,8 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>> uint32_t src_w, uint32_t src_h);
>> int intel_disable_plane(struct drm_plane *plane);
>> void intel_plane_destroy(struct drm_plane *plane);
>> +void intel_edp_drrs_enable(struct intel_dp *intel_dp);
>> +void intel_edp_drrs_disable(struct intel_dp *intel_dp);
>>
>> /* intel_dp_mst.c */
>> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (2 preceding siblings ...)
2015-01-09 20:55 ` [PATCH 3/10] drm/i915: Enable/disable DRRS Vandana Kannan
@ 2015-01-09 20:55 ` Vandana Kannan
2015-01-15 22:49 ` Rodrigo Vivi
2015-02-11 12:43 ` [PATCH 1/6] drm/i915: Add support for DRRS in intel_dp_set_m_n Ramalingam C
2015-01-09 20:56 ` [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
` (5 subsequent siblings)
9 siblings, 2 replies; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
called as part of frontbuffer tracking.
Apart from calls as a result of GEM tracking to fb invalidate/flush, a
call has been added to invalidate fb obj from crtc_page_flip as well. This
is to track busyness through flip calls.
The call to fb_obj_invalidate (in flip) is placed before queuing flip for this
obj.
drrs_invalidate() and drrs_flush() check for drrs.dp which would be NULL if
it was setup in drrs_enable(). This covers for the condition when DRRS is
not supported.
v2: Removing the call to invalidate_drrs from page_flip.
This has not been tested on Android yet, but, in case DRRS transtions do not
work as expected, check by adding back this call in page_flip.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 51 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_frontbuffer.c | 2 ++
3 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e7dc7b..ca89e59 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4902,6 +4902,57 @@ unlock:
mutex_unlock(&dev_priv->drrs.mutex);
}
+void intel_edp_drrs_invalidate(struct drm_device *dev,
+ unsigned frontbuffer_bits)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ enum pipe pipe;
+
+ if (!dev_priv->drrs.dp)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
+ pipe = to_intel_crtc(crtc)->pipe;
+
+ if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
+ cancel_delayed_work_sync(&dev_priv->drrs.work);
+ intel_dp_set_drrs_state(dev_priv->dev,
+ dev_priv->drrs.dp->attached_connector->panel.
+ fixed_mode->vrefresh);
+ }
+
+ frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
+
+ dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
+void intel_edp_drrs_flush(struct drm_device *dev,
+ unsigned frontbuffer_bits)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ enum pipe pipe;
+
+ if (!dev_priv->drrs.dp)
+ return;
+
+ mutex_lock(&dev_priv->drrs.mutex);
+ crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
+ pipe = to_intel_crtc(crtc)->pipe;
+ dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
+
+ cancel_delayed_work_sync(&dev_priv->drrs.work);
+
+ if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
+ !dev_priv->drrs.busy_frontbuffer_bits)
+ schedule_delayed_work(&dev_priv->drrs.work,
+ msecs_to_jiffies(1000));
+ mutex_unlock(&dev_priv->drrs.mutex);
+}
+
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_connector *intel_connector,
struct drm_display_mode *fixed_mode)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f3ad3b..17f168a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1005,6 +1005,9 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
int intel_disable_plane(struct drm_plane *plane);
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
+void intel_edp_drrs_invalidate(struct drm_device *dev,
+ unsigned frontbuffer_bits);
+void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 79f6d72..73cb6e0 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -157,6 +157,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
intel_psr_invalidate(dev, obj->frontbuffer_bits);
+ intel_edp_drrs_invalidate(dev, obj->frontbuffer_bits);
}
/**
@@ -182,6 +183,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
+ intel_edp_drrs_flush(dev, frontbuffer_bits);
intel_psr_flush(dev, frontbuffer_bits);
/*
--
2.0.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer
2015-01-09 20:55 ` [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer Vandana Kannan
@ 2015-01-15 22:49 ` Rodrigo Vivi
2015-01-26 7:44 ` Daniel Vetter
2015-02-11 12:43 ` [PATCH 1/6] drm/i915: Add support for DRRS in intel_dp_set_m_n Ramalingam C
1 sibling, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 22:49 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
looks ok for me...
you will also have conflict so a rebased version is at:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=review-drrs
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Jan 9, 2015 at 12:55 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
> called as part of frontbuffer tracking.
> Apart from calls as a result of GEM tracking to fb invalidate/flush, a
> call has been added to invalidate fb obj from crtc_page_flip as well. This
> is to track busyness through flip calls.
> The call to fb_obj_invalidate (in flip) is placed before queuing flip for this
> obj.
>
> drrs_invalidate() and drrs_flush() check for drrs.dp which would be NULL if
> it was setup in drrs_enable(). This covers for the condition when DRRS is
> not supported.
>
> v2: Removing the call to invalidate_drrs from page_flip.
> This has not been tested on Android yet, but, in case DRRS transtions do not
> work as expected, check by adding back this call in page_flip.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 51 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> drivers/gpu/drm/i915/intel_frontbuffer.c | 2 ++
> 3 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5e7dc7b..ca89e59 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4902,6 +4902,57 @@ unlock:
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +void intel_edp_drrs_invalidate(struct drm_device *dev,
> + unsigned frontbuffer_bits)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (!dev_priv->drrs.dp)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> +
> + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> + intel_dp_set_drrs_state(dev_priv->dev,
> + dev_priv->drrs.dp->attached_connector->panel.
> + fixed_mode->vrefresh);
> + }
> +
> + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> +
> + dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> +void intel_edp_drrs_flush(struct drm_device *dev,
> + unsigned frontbuffer_bits)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_crtc *crtc;
> + enum pipe pipe;
> +
> + if (!dev_priv->drrs.dp)
> + return;
> +
> + mutex_lock(&dev_priv->drrs.mutex);
> + crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> + pipe = to_intel_crtc(crtc)->pipe;
> + dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> +
> + cancel_delayed_work_sync(&dev_priv->drrs.work);
> +
> + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
> + !dev_priv->drrs.busy_frontbuffer_bits)
> + schedule_delayed_work(&dev_priv->drrs.work,
> + msecs_to_jiffies(1000));
> + mutex_unlock(&dev_priv->drrs.mutex);
> +}
> +
> static struct drm_display_mode *
> intel_dp_drrs_init(struct intel_connector *intel_connector,
> struct drm_display_mode *fixed_mode)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6f3ad3b..17f168a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1005,6 +1005,9 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> int intel_disable_plane(struct drm_plane *plane);
> void intel_edp_drrs_enable(struct intel_dp *intel_dp);
> void intel_edp_drrs_disable(struct intel_dp *intel_dp);
> +void intel_edp_drrs_invalidate(struct drm_device *dev,
> + unsigned frontbuffer_bits);
> +void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
>
> /* intel_dp_mst.c */
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
> index 79f6d72..73cb6e0 100644
> --- a/drivers/gpu/drm/i915/intel_frontbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
> @@ -157,6 +157,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
> intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
>
> intel_psr_invalidate(dev, obj->frontbuffer_bits);
> + intel_edp_drrs_invalidate(dev, obj->frontbuffer_bits);
> }
>
> /**
> @@ -182,6 +183,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
>
> intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
>
> + intel_edp_drrs_flush(dev, frontbuffer_bits);
> intel_psr_flush(dev, frontbuffer_bits);
>
> /*
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer
2015-01-15 22:49 ` Rodrigo Vivi
@ 2015-01-26 7:44 ` Daniel Vetter
0 siblings, 0 replies; 64+ messages in thread
From: Daniel Vetter @ 2015-01-26 7:44 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Vivi, Rodrigo, Paulo Zanoni
On Thu, Jan 15, 2015 at 02:49:55PM -0800, Rodrigo Vivi wrote:
> looks ok for me...
> you will also have conflict so a rebased version is at:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=review-drrs
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Merged up to this one, thanks for patches&review.
-Daniel
>
> On Fri, Jan 9, 2015 at 12:55 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
> > Calls have been added to invalidate/flush DRRS whenever invalidate/flush is
> > called as part of frontbuffer tracking.
> > Apart from calls as a result of GEM tracking to fb invalidate/flush, a
> > call has been added to invalidate fb obj from crtc_page_flip as well. This
> > is to track busyness through flip calls.
> > The call to fb_obj_invalidate (in flip) is placed before queuing flip for this
> > obj.
> >
> > drrs_invalidate() and drrs_flush() check for drrs.dp which would be NULL if
> > it was setup in drrs_enable(). This covers for the condition when DRRS is
> > not supported.
> >
> > v2: Removing the call to invalidate_drrs from page_flip.
> > This has not been tested on Android yet, but, in case DRRS transtions do not
> > work as expected, check by adding back this call in page_flip.
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 51 ++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 3 ++
> > drivers/gpu/drm/i915/intel_frontbuffer.c | 2 ++
> > 3 files changed, 56 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 5e7dc7b..ca89e59 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4902,6 +4902,57 @@ unlock:
> > mutex_unlock(&dev_priv->drrs.mutex);
> > }
> >
> > +void intel_edp_drrs_invalidate(struct drm_device *dev,
> > + unsigned frontbuffer_bits)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct drm_crtc *crtc;
> > + enum pipe pipe;
> > +
> > + if (!dev_priv->drrs.dp)
> > + return;
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > + crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> > + pipe = to_intel_crtc(crtc)->pipe;
> > +
> > + if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
> > + cancel_delayed_work_sync(&dev_priv->drrs.work);
> > + intel_dp_set_drrs_state(dev_priv->dev,
> > + dev_priv->drrs.dp->attached_connector->panel.
> > + fixed_mode->vrefresh);
> > + }
> > +
> > + frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
> > +
> > + dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > +void intel_edp_drrs_flush(struct drm_device *dev,
> > + unsigned frontbuffer_bits)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct drm_crtc *crtc;
> > + enum pipe pipe;
> > +
> > + if (!dev_priv->drrs.dp)
> > + return;
> > +
> > + mutex_lock(&dev_priv->drrs.mutex);
> > + crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> > + pipe = to_intel_crtc(crtc)->pipe;
> > + dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
> > +
> > + cancel_delayed_work_sync(&dev_priv->drrs.work);
> > +
> > + if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
> > + !dev_priv->drrs.busy_frontbuffer_bits)
> > + schedule_delayed_work(&dev_priv->drrs.work,
> > + msecs_to_jiffies(1000));
> > + mutex_unlock(&dev_priv->drrs.mutex);
> > +}
> > +
> > static struct drm_display_mode *
> > intel_dp_drrs_init(struct intel_connector *intel_connector,
> > struct drm_display_mode *fixed_mode)
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 6f3ad3b..17f168a 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1005,6 +1005,9 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> > int intel_disable_plane(struct drm_plane *plane);
> > void intel_edp_drrs_enable(struct intel_dp *intel_dp);
> > void intel_edp_drrs_disable(struct intel_dp *intel_dp);
> > +void intel_edp_drrs_invalidate(struct drm_device *dev,
> > + unsigned frontbuffer_bits);
> > +void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
> >
> > /* intel_dp_mst.c */
> > int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> > diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
> > index 79f6d72..73cb6e0 100644
> > --- a/drivers/gpu/drm/i915/intel_frontbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
> > @@ -157,6 +157,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
> > intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
> >
> > intel_psr_invalidate(dev, obj->frontbuffer_bits);
> > + intel_edp_drrs_invalidate(dev, obj->frontbuffer_bits);
> > }
> >
> > /**
> > @@ -182,6 +183,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
> >
> > intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
> >
> > + intel_edp_drrs_flush(dev, frontbuffer_bits);
> > intel_psr_flush(dev, frontbuffer_bits);
> >
> > /*
> > --
> > 2.0.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 1/6] drm/i915: Add support for DRRS in intel_dp_set_m_n
2015-01-09 20:55 ` [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer Vandana Kannan
2015-01-15 22:49 ` Rodrigo Vivi
@ 2015-02-11 12:43 ` Ramalingam C
2015-02-11 12:58 ` Ramalingam C
1 sibling, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-02-11 12:43 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
Till Gen 7 we have two sets of M_N registers, but Gen 8 onwards
we have only one M_N register set. To support DRRS on both scenarios
a input parameter to intel_dp_set_m_n is added.
In case of DRRS, When platform provides two set of M_N registers for dp,
we can program them with two different dividers and switch between them.
But when only one such register set is provided, we have to program
the required divider M_N value on that registers itself.
Two enum members M1_N1 and M2_N2 are defined to represent the above
scenarios.
M1_N1 : Program dp_m_n on M1_N1 registers
dp_m2_n2 on M2_N2 registers (If supported)
M2_N2 : Program dp_m2_n2 on M1_N1 registers
M2_N2 registers are not supported
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_drv.h | 22 +++++++++++++++++++++-
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..ced049a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4316,7 +4316,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_prepare_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -4424,7 +4424,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_enable_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5038,7 +5038,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
}
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5114,7 +5114,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_set_pll_dividers(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5889,13 +5889,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
}
}
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
{
+ struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+
+ if (m_n == M1_N1) {
+ dp_m_n = &crtc->config->dp_m_n;
+ dp_m2_n2 = &crtc->config->dp_m2_n2;
+ } else if (m_n == M2_N2) {
+
+ /*
+ * M2_N2 registers are not supported. Hence m2_n2 divider value
+ * needs to be programmed into M1_N1.
+ */
+ dp_m_n = &crtc->config->dp_m2_n2;
+ } else {
+ DRM_ERROR("Unsupported divider value\n");
+ return;
+ }
+
if (crtc->config->has_pch_encoder)
intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
else
- intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
- &crtc->config->dp_m2_n2);
+ intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
}
static void vlv_update_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 76b3c20..e05de19 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -593,6 +593,26 @@ struct intel_hdmi {
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS 0x10
+/*
+ * enum link_m_n_set:
+ * When platform provides two set of M_N registers for dp, we can
+ * program them and switch between them incase of DRRS.
+ * But When only one such register is provided, we have to program the
+ * required divider value on that registers itself based on the DRRS state.
+ *
+ * M1_N1 : Program dp_m_n on M1_N1 registers
+ * dp_m2_n2 on M2_N2 registers (If supported)
+ *
+ * M2_N2 : Program dp_m2_n2 on M1_N1 registers
+ * M2_N2 registers are not supported
+ */
+
+enum link_m_n_set {
+ /* Sets the m1_n1 and m2_n2 */
+ M1_N1 = 0,
+ M2_N2
+};
+
struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -994,7 +1014,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
--
1.7.9.5
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 1/6] drm/i915: Add support for DRRS in intel_dp_set_m_n
2015-02-11 12:43 ` [PATCH 1/6] drm/i915: Add support for DRRS in intel_dp_set_m_n Ramalingam C
@ 2015-02-11 12:58 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-02-11 12:58 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
Hi,
This is preparation patch for "[PATCH] drm/i915/bdw: Add support for
DRRS to switch RR".
My bad that I have misplaced this in the thread.
On Wednesday 11 February 2015 06:13 PM, Ramalingam C wrote:
> Till Gen 7 we have two sets of M_N registers, but Gen 8 onwards
> we have only one M_N register set. To support DRRS on both scenarios
> a input parameter to intel_dp_set_m_n is added.
>
> In case of DRRS, When platform provides two set of M_N registers for dp,
> we can program them with two different dividers and switch between them.
> But when only one such register set is provided, we have to program
> the required divider M_N value on that registers itself.
>
> Two enum members M1_N1 and M2_N2 are defined to represent the above
> scenarios.
>
> M1_N1 : Program dp_m_n on M1_N1 registers
> dp_m2_n2 on M2_N2 registers (If supported)
>
> M2_N2 : Program dp_m2_n2 on M1_N1 registers
> M2_N2 registers are not supported
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++-------
> drivers/gpu/drm/i915/intel_drv.h | 22 +++++++++++++++++++++-
> 2 files changed, 44 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3fe9598..ced049a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4316,7 +4316,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> intel_prepare_shared_dpll(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -4424,7 +4424,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_enable_shared_dpll(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5038,7 +5038,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> }
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5114,7 +5114,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> i9xx_set_pll_dividers(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5889,13 +5889,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> }
> }
>
> -void intel_dp_set_m_n(struct intel_crtc *crtc)
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
> {
> + struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
> +
> + if (m_n == M1_N1) {
> + dp_m_n = &crtc->config->dp_m_n;
> + dp_m2_n2 = &crtc->config->dp_m2_n2;
> + } else if (m_n == M2_N2) {
> +
> + /*
> + * M2_N2 registers are not supported. Hence m2_n2 divider value
> + * needs to be programmed into M1_N1.
> + */
> + dp_m_n = &crtc->config->dp_m2_n2;
> + } else {
> + DRM_ERROR("Unsupported divider value\n");
> + return;
> + }
> +
> if (crtc->config->has_pch_encoder)
> intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
> else
> - intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
> - &crtc->config->dp_m2_n2);
> + intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
> }
>
> static void vlv_update_pll(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 76b3c20..e05de19 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -593,6 +593,26 @@ struct intel_hdmi {
> struct intel_dp_mst_encoder;
> #define DP_MAX_DOWNSTREAM_PORTS 0x10
>
> +/*
> + * enum link_m_n_set:
> + * When platform provides two set of M_N registers for dp, we can
> + * program them and switch between them incase of DRRS.
> + * But When only one such register is provided, we have to program the
> + * required divider value on that registers itself based on the DRRS state.
> + *
> + * M1_N1 : Program dp_m_n on M1_N1 registers
> + * dp_m2_n2 on M2_N2 registers (If supported)
> + *
> + * M2_N2 : Program dp_m2_n2 on M1_N1 registers
> + * M2_N2 registers are not supported
> + */
> +
> +enum link_m_n_set {
> + /* Sets the m1_n1 and m2_n2 */
> + M1_N1 = 0,
> + M2_N2
> +};
> +
> struct intel_dp {
> uint32_t output_reg;
> uint32_t aux_ch_ctl_reg;
> @@ -994,7 +1014,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> -void intel_dp_set_m_n(struct intel_crtc *crtc);
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
--
Ram
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (3 preceding siblings ...)
2015-01-09 20:55 ` [PATCH 4/10] drm/i915: DRRS calls based on frontbuffer Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-15 23:00 ` Rodrigo Vivi
2015-01-09 20:56 ` [PATCH 6/10] drm/i915: Support for RR switching on VLV Vandana Kannan
` (4 subsequent siblings)
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 9 +++------
drivers/gpu/drm/i915/intel_dp.c | 15 ++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a03955d..25596ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_i915_gem_object *obj);
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2);
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -5795,9 +5792,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca89e59..85a029e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4802,7 +4802,20 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch(index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m_n(intel_crtc);
+ break;
+ case DRRS_LOW_RR:
+ intel_cpu_transcoder_set_m_n(intel_crtc,
+ &intel_crtc->config.dp_m2_n2, NULL);
+ break;
+ case DRRS_MAX_RR:
+ default:
+ break;
+ }
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17f168a..f5846cf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -953,6 +953,9 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
--
2.0.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-09 20:56 ` [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
@ 2015-01-15 23:00 ` Rodrigo Vivi
2015-01-21 11:19 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:00 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +++------
> drivers/gpu/drm/i915/intel_dp.c | 15 ++++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a03955d..25596ca 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
> struct drm_i915_gem_object *obj);
> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> - struct intel_link_m_n *m_n,
> - struct intel_link_m_n *m2_n2);
> static void ironlake_set_pipeconf(struct drm_crtc *crtc);
> static void haswell_set_pipeconf(struct drm_crtc *crtc);
> static void intel_set_pipe_csc(struct drm_crtc *crtc);
> @@ -5795,9 +5792,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
> }
>
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> - struct intel_link_m_n *m_n,
> - struct intel_link_m_n *m2_n2)
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> + struct intel_link_m_n *m_n,
> + struct intel_link_m_n *m2_n2)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ca89e59..85a029e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4802,7 +4802,20 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> return;
> }
>
> - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_INFO(dev)->gen >= 8) {
> + switch(index) {
> + case DRRS_HIGH_RR:
> + intel_dp_set_m_n(intel_crtc);
> + break;
> + case DRRS_LOW_RR:
> + intel_cpu_transcoder_set_m_n(intel_crtc,
I didn't like this mix of intel_dp_set and intel_cpu set when
intel_dp_set calls cpu set only when it doesn't have pch...
It seems at least strange.
Maybe change intel_dp_set_m_n to support different sets...
> + &intel_crtc->config.dp_m2_n2, NULL);
Also didn't understand why sending m2_n2 on m1_n1 and NULL on m2_n2.
Is there a way to change that function to support different ways
instead of doing this?
> + break;
> + case DRRS_MAX_RR:
> + default:
> + break;
> + }
> + } else if (INTEL_INFO(dev)->gen > 6) {
> reg = PIPECONF(intel_crtc->config.cpu_transcoder);
> val = I915_READ(reg);
> if (index > DRRS_HIGH_RR) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 17f168a..f5846cf 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -953,6 +953,9 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config);
> void intel_dp_set_m_n(struct intel_crtc *crtc);
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> + struct intel_link_m_n *m_n,
> + struct intel_link_m_n *m2_n2);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-15 23:00 ` Rodrigo Vivi
@ 2015-01-21 11:19 ` Ramalingam C
2015-01-22 9:50 ` [PATCH] " Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 11:19 UTC (permalink / raw)
To: Rodrigo Vivi, Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
[-- Attachment #1.1: Type: text/plain, Size: 5094 bytes --]
On Friday 16 January 2015 04:30 AM, Rodrigo Vivi wrote:
> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
>> For Broadwell, there is one instance of Transcoder MN values per transcoder.
>> For dynamic switching between multiple refreshr rates, M/N values may be
>> reprogrammed on the fly. Link N programming triggers update of all data and
>> link M & N registers and the new M/N values will be used in the next frame
>> that is output.
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 9 +++------
>> drivers/gpu/drm/i915/intel_dp.c | 15 ++++++++++++++-
>> drivers/gpu/drm/i915/intel_drv.h | 3 +++
>> 3 files changed, 20 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a03955d..25596ca 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
>> struct drm_i915_gem_object *obj);
>> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
>> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
>> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>> - struct intel_link_m_n *m_n,
>> - struct intel_link_m_n *m2_n2);
>> static void ironlake_set_pipeconf(struct drm_crtc *crtc);
>> static void haswell_set_pipeconf(struct drm_crtc *crtc);
>> static void intel_set_pipe_csc(struct drm_crtc *crtc);
>> @@ -5795,9 +5792,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
>> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
>> }
>>
>> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>> - struct intel_link_m_n *m_n,
>> - struct intel_link_m_n *m2_n2)
>> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>> + struct intel_link_m_n *m_n,
>> + struct intel_link_m_n *m2_n2)
>> {
>> struct drm_device *dev = crtc->base.dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index ca89e59..85a029e 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4802,7 +4802,20 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> return;
>> }
>>
>> - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
>> + if (INTEL_INFO(dev)->gen >= 8) {
>> + switch(index) {
>> + case DRRS_HIGH_RR:
>> + intel_dp_set_m_n(intel_crtc);
>> + break;
>> + case DRRS_LOW_RR:
>> + intel_cpu_transcoder_set_m_n(intel_crtc,
> I didn't like this mix of intel_dp_set and intel_cpu set when
> intel_dp_set calls cpu set only when it doesn't have pch...
> It seems at least strange.
>
> Maybe change intel_dp_set_m_n to support different sets...
>
>> + &intel_crtc->config.dp_m2_n2, NULL);
> Also didn't understand why sending m2_n2 on m1_n1 and NULL on m2_n2.
>
> Is there a way to change that function to support different ways
> instead of doing this?
Agreed. I will rewrite the intel_dp_set_m_n to handle all different sets.
>
>> + break;
>> + case DRRS_MAX_RR:
>> + default:
>> + break;
>> + }
>> + } else if (INTEL_INFO(dev)->gen > 6) {
>> reg = PIPECONF(intel_crtc->config.cpu_transcoder);
>> val = I915_READ(reg);
>> if (index > DRRS_HIGH_RR) {
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 17f168a..f5846cf 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -953,6 +953,9 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc *crtc,
>> struct intel_crtc_config *pipe_config);
>> void intel_dp_set_m_n(struct intel_crtc *crtc);
>> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>> + struct intel_link_m_n *m_n,
>> + struct intel_link_m_n *m2_n2);
>> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>> void
>> ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
>> --
>> 2.0.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
--Ram
[-- Attachment #1.2: Type: text/html, Size: 6162 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-21 11:19 ` Ramalingam C
@ 2015-01-22 9:50 ` Ramalingam C
2015-01-22 16:40 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 9:50 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
gen >= 8 [Rodrigo]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++------------
drivers/gpu/drm/i915/intel_dp.c | 16 +++++++++++++--
drivers/gpu/drm/i915/intel_drv.h | 11 ++++++++++-
3 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01dc80b..5712686 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_i915_gem_object *obj);
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2);
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -4289,7 +4286,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_prepare_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -4397,7 +4394,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_enable_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5011,7 +5008,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
}
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5087,7 +5084,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_set_pll_dividers(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5828,9 +5825,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5862,13 +5859,26 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
}
}
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
{
+ struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+
+ if (m_n == M1_N1) {
+ dp_m_n = &crtc->config->dp_m_n;
+ dp_m2_n2 = &crtc->config->dp_m2_n2;
+ } else if (m_n == M2_N2) {
+ /* Only one register programming is supported. And m_n value
+ * corresponding to downclock mode needs to be programmed */
+ dp_m_n = &crtc->config->dp_m2_n2;
+ } else {
+ DRM_ERROR("Unsupported divider value\n");
+ return;
+ }
+
if (crtc->config->has_pch_encoder)
intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
else
- intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
- &crtc->config->dp_m2_n2);
+ intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
}
static void vlv_update_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 955aca3..592ca3d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4803,12 +4803,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch(index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m_n(intel_crtc, M1_N1);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m_n(intel_crtc, M2_N2);
+ break;
+ case DRRS_MAX_RR:
+ default:
+ DRM_ERROR("Unsupported refreshrate type\n");
+ }
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config->cpu_transcoder);
val = I915_READ(reg);
+
if (index > DRRS_HIGH_RR) {
val |= PIPECONF_EDP_RR_MODE_SWITCH;
- intel_dp_set_m_n(intel_crtc);
} else {
val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a31dc103..193ccda 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -587,6 +587,12 @@ struct intel_hdmi {
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS 0x10
+/* enum to indicate the m_n value from calculated list */
+enum link_m_n_set {
+ M1_N1 = 0,
+ M2_N2
+};
+
struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -979,7 +985,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-22 9:50 ` [PATCH] " Ramalingam C
@ 2015-01-22 16:40 ` Ramalingam C
2015-01-24 0:00 ` Rodrigo Vivi
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 16:40 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
gen >= 8 [Rodrigo]
V3: Coding style correction [Ram]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++------------
drivers/gpu/drm/i915/intel_dp.c | 16 +++++++++++++--
drivers/gpu/drm/i915/intel_drv.h | 11 ++++++++++-
3 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01dc80b..5712686 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_i915_gem_object *obj);
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2);
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -4289,7 +4286,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_prepare_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -4397,7 +4394,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_enable_shared_dpll(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5011,7 +5008,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
}
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5087,7 +5084,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
i9xx_set_pll_dividers(intel_crtc);
if (intel_crtc->config->has_dp_encoder)
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
intel_set_pipe_timings(intel_crtc);
@@ -5828,9 +5825,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
- struct intel_link_m_n *m_n,
- struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5862,13 +5859,26 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
}
}
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
{
+ struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+
+ if (m_n == M1_N1) {
+ dp_m_n = &crtc->config->dp_m_n;
+ dp_m2_n2 = &crtc->config->dp_m2_n2;
+ } else if (m_n == M2_N2) {
+ /* Only one register programming is supported. And m_n value
+ * corresponding to downclock mode needs to be programmed */
+ dp_m_n = &crtc->config->dp_m2_n2;
+ } else {
+ DRM_ERROR("Unsupported divider value\n");
+ return;
+ }
+
if (crtc->config->has_pch_encoder)
intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
else
- intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
- &crtc->config->dp_m2_n2);
+ intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
}
static void vlv_update_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 955aca3..27ff0d4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4803,12 +4803,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m_n(intel_crtc, M1_N1);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m_n(intel_crtc, M2_N2);
+ break;
+ case DRRS_MAX_RR:
+ default:
+ DRM_ERROR("Unsupported refreshrate type\n");
+ }
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config->cpu_transcoder);
val = I915_READ(reg);
+
if (index > DRRS_HIGH_RR) {
val |= PIPECONF_EDP_RR_MODE_SWITCH;
- intel_dp_set_m_n(intel_crtc);
} else {
val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a31dc103..193ccda 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -587,6 +587,12 @@ struct intel_hdmi {
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS 0x10
+/* enum to indicate the m_n value from calculated list */
+enum link_m_n_set {
+ M1_N1 = 0,
+ M2_N2
+};
+
struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -979,7 +985,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n,
+ struct intel_link_m_n *m2_n2);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-22 16:40 ` Ramalingam C
@ 2015-01-24 0:00 ` Rodrigo Vivi
2015-02-11 12:48 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-24 0:00 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Thu, Jan 22, 2015 at 8:40 AM, Ramalingam C <ramalingam.c@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> For Broadwell, there is one instance of Transcoder MN values per transcoder.
> For dynamic switching between multiple refreshr rates, M/N values may be
> reprogrammed on the fly. Link N programming triggers update of all data and
> link M & N registers and the new M/N values will be used in the next frame
> that is output.
>
> V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
> gen >= 8 [Rodrigo]
> V3: Coding style correction [Ram]
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++------------
> drivers/gpu/drm/i915/intel_dp.c | 16 +++++++++++++--
> drivers/gpu/drm/i915/intel_drv.h | 11 ++++++++++-
> 3 files changed, 47 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 01dc80b..5712686 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -88,9 +88,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
> struct drm_i915_gem_object *obj);
> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> - struct intel_link_m_n *m_n,
> - struct intel_link_m_n *m2_n2);
I believe all this set_m_n changes should be in a separated
preparation patch....
> static void ironlake_set_pipeconf(struct drm_crtc *crtc);
> static void haswell_set_pipeconf(struct drm_crtc *crtc);
> static void intel_set_pipe_csc(struct drm_crtc *crtc);
> @@ -4289,7 +4286,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> intel_prepare_shared_dpll(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -4397,7 +4394,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_enable_shared_dpll(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5011,7 +5008,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> }
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5087,7 +5084,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> i9xx_set_pll_dividers(intel_crtc);
>
> if (intel_crtc->config->has_dp_encoder)
> - intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc, M1_N1);
>
> intel_set_pipe_timings(intel_crtc);
>
> @@ -5828,9 +5825,9 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
> I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
> }
>
> -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> - struct intel_link_m_n *m_n,
> - struct intel_link_m_n *m2_n2)
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> + struct intel_link_m_n *m_n,
> + struct intel_link_m_n *m2_n2)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5862,13 +5859,26 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> }
> }
>
> -void intel_dp_set_m_n(struct intel_crtc *crtc)
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
> {
> + struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
> +
> + if (m_n == M1_N1) {
> + dp_m_n = &crtc->config->dp_m_n;
> + dp_m2_n2 = &crtc->config->dp_m2_n2;
> + } else if (m_n == M2_N2) {
> + /* Only one register programming is supported. And m_n value
> + * corresponding to downclock mode needs to be programmed */
> + dp_m_n = &crtc->config->dp_m2_n2;
> + } else {
> + DRM_ERROR("Unsupported divider value\n");
> + return;
> + }
> +
> if (crtc->config->has_pch_encoder)
> intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
> else
> - intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
> - &crtc->config->dp_m2_n2);
> + intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
> }
>
> static void vlv_update_pll(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 955aca3..27ff0d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4803,12 +4803,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> return;
> }
>
> - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_INFO(dev)->gen >= 8) {
> + switch (index) {
> + case DRRS_HIGH_RR:
> + intel_dp_set_m_n(intel_crtc, M1_N1);
> + break;
> + case DRRS_LOW_RR:
> + intel_dp_set_m_n(intel_crtc, M2_N2);
> + break;
> + case DRRS_MAX_RR:
> + default:
> + DRM_ERROR("Unsupported refreshrate type\n");
> + }
> + } else if (INTEL_INFO(dev)->gen > 6) {
> reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> val = I915_READ(reg);
> +
Then, only this block really related to drrs as in commit message
should stay on this commit.
> if (index > DRRS_HIGH_RR) {
> val |= PIPECONF_EDP_RR_MODE_SWITCH;
> - intel_dp_set_m_n(intel_crtc);
> } else {
> val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a31dc103..193ccda 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -587,6 +587,12 @@ struct intel_hdmi {
> struct intel_dp_mst_encoder;
> #define DP_MAX_DOWNSTREAM_PORTS 0x10
>
> +/* enum to indicate the m_n value from calculated list */
> +enum link_m_n_set {
> + M1_N1 = 0,
> + M2_N2
> +};
> +
> struct intel_dp {
> uint32_t output_reg;
> uint32_t aux_ch_ctl_reg;
> @@ -979,7 +985,10 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> -void intel_dp_set_m_n(struct intel_crtc *crtc);
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
> +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> + struct intel_link_m_n *m_n,
> + struct intel_link_m_n *m2_n2);
> int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
but I don't want to block progress here....
I'll let this desicion to author and maintainer and in any case feel free to
use my:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915/bdw: Add support for DRRS to switch RR
2015-01-24 0:00 ` Rodrigo Vivi
@ 2015-02-11 12:48 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-02-11 12:48 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
gen >= 8 [Rodrigo]
V3: Coding style correction [Ram]
V4: [By Ram] intel_dp_set_m_n modifications are moved into a
separate patch, retaining only DRRS related changes here [Rodrigo]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eea9e36..d29d669 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4808,12 +4808,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m_n(intel_crtc, M1_N1);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m_n(intel_crtc, M2_N2);
+ break;
+ case DRRS_MAX_RR:
+ default:
+ DRM_ERROR("Unsupported refreshrate type\n");
+ }
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config->cpu_transcoder);
val = I915_READ(reg);
+
if (index > DRRS_HIGH_RR) {
val |= PIPECONF_EDP_RR_MODE_SWITCH;
- intel_dp_set_m_n(intel_crtc);
} else {
val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
--
1.7.9.5
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 6/10] drm/i915: Support for RR switching on VLV
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (4 preceding siblings ...)
2015-01-09 20:56 ` [PATCH 5/10] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-15 23:06 ` Rodrigo Vivi
2015-01-09 20:56 ` [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV Vandana Kannan
` (3 subsequent siblings)
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40ca873..63a3fca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum punit_power_well {
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK (0x7 << 5)
#define PIPECONF_8BPC (0<<5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 85a029e..3362d93 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4819,10 +4819,16 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val |= PIPECONF_EDP_RR_MODE_SWITCH;
intel_dp_set_m_n(intel_crtc);
} else {
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
I915_WRITE(reg, val);
}
--
2.0.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 6/10] drm/i915: Support for RR switching on VLV
2015-01-09 20:56 ` [PATCH 6/10] drm/i915: Support for RR switching on VLV Vandana Kannan
@ 2015-01-15 23:06 ` Rodrigo Vivi
0 siblings, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:06 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> Definition of VLV RR switch bit and corresponding toggling in
> set_drrs function.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 40ca873..63a3fca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3840,6 +3840,7 @@ enum punit_power_well {
> #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
> #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
> #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
> +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
> #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
> #define PIPECONF_BPC_MASK (0x7 << 5)
> #define PIPECONF_8BPC (0<<5)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 85a029e..3362d93 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4819,10 +4819,16 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> reg = PIPECONF(intel_crtc->config.cpu_transcoder);
> val = I915_READ(reg);
> if (index > DRRS_HIGH_RR) {
> - val |= PIPECONF_EDP_RR_MODE_SWITCH;
> + if (IS_VALLEYVIEW(dev))
> + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val |= PIPECONF_EDP_RR_MODE_SWITCH;
> intel_dp_set_m_n(intel_crtc);
> } else {
> - val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> + if (IS_VALLEYVIEW(dev))
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> }
> I915_WRITE(reg, val);
> }
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (5 preceding siblings ...)
2015-01-09 20:56 ` [PATCH 6/10] drm/i915: Support for RR switching on VLV Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-15 23:11 ` Rodrigo Vivi
2015-01-24 0:05 ` Rodrigo Vivi
2015-01-09 20:56 ` [PATCH 8/10] Documentation/drm: DocBook integration for DRRS Vandana Kannan
` (2 subsequent siblings)
9 siblings, 2 replies; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: rodrigo.vivi, paulo.r.zanoni
From: Durgadoss R <durgadoss.r@intel.com>
This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.
[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 25596ca..bb44fb9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
* for gen < 8) and if DRRS is supported (to make sure the
* registers are not unnecessarily accessed).
*/
- if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
- crtc->config.has_drrs) {
+ if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
+ && crtc->config.has_drrs) {
I915_WRITE(PIPE_DATA_M2(transcoder),
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3362d93..42195fe 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
switch(index) {
case DRRS_HIGH_RR:
intel_dp_set_m_n(intel_crtc);
--
2.0.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-09 20:56 ` [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV Vandana Kannan
@ 2015-01-15 23:11 ` Rodrigo Vivi
2015-01-21 12:13 ` Ramalingam C
2015-01-24 0:05 ` Rodrigo Vivi
1 sibling, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:11 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> From: Durgadoss R <durgadoss.r@intel.com>
>
> This patch enables eDP DRRS for CHV by adding the
> required IS_CHERRYVIEW() checks.
> CHV uses the same register bit as VLV.
>
> [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
> path as gen < 8. Added CHV check in dp_set_m_n()
>
> Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 25596ca..bb44fb9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> * for gen < 8) and if DRRS is supported (to make sure the
> * registers are not unnecessarily accessed).
> */
> - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> - crtc->config.has_drrs) {
> + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
> + && crtc->config.has_drrs) {
This change here doesn't seem safe. As I told on previous comment I'd
prefer changing intel_dp_set_m_n instead of re-using this intel_cpu
one...
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3362d93..42195fe 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> return;
> }
>
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
> switch(index) {
> case DRRS_HIGH_RR:
> intel_dp_set_m_n(intel_crtc);
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-15 23:11 ` Rodrigo Vivi
@ 2015-01-21 12:13 ` Ramalingam C
2015-01-21 15:03 ` Rodrigo Vivi
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 12:13 UTC (permalink / raw)
To: Rodrigo Vivi, Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
[-- Attachment #1.1: Type: text/plain, Size: 6738 bytes --]
Hi
On Friday 16 January 2015 04:41 AM, Rodrigo Vivi wrote:
> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
>> From: Durgadoss R <durgadoss.r@intel.com>
>>
>> This patch enables eDP DRRS for CHV by adding the
>> required IS_CHERRYVIEW() checks.
>> CHV uses the same register bit as VLV.
>>
>> [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
>> path as gen < 8. Added CHV check in dp_set_m_n()
>>
>> Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 4 ++--
>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 25596ca..bb44fb9 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>> * for gen < 8) and if DRRS is supported (to make sure the
>> * registers are not unnecessarily accessed).
>> */
>> - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
>> - crtc->config.has_drrs) {
>> + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
>> + && crtc->config.has_drrs) {
> This change here doesn't seem safe. As I told on previous comment I'd
> prefer changing intel_dp_set_m_n instead of re-using this intel_cpu
> one...
Though I am rewriting the intel_dp_set_m_n() that will reuse
intel_cpu_transcoder_set_m_n() within.
But as a result, i am going to avoid the parallel usage of
intel_cpu_transcoder_set_m_n() and intel_dp_set_m_n().
So I am afraid this check for inclusion of cherryview for m2_n2
programming will be part of the newer code also.
Appending the RFC for the newer intel_dp_set_m_n() implementation below.
Please review.
RFC starts here:
drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++---
drivers/gpu/drm/i915/intel_dp.c | 6 ++----
drivers/gpu/drm/i915/intel_drv.h | 8 +++++++-
3 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 061a253..59cc87f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5829,13 +5829,26 @@ void intel_cpu_transcoder_set_m_n(struct
intel_crtc *crtc,
}
}
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set =
M1_N1)
{
+ struct intel_link_m_n *dp_m_n, *dp_m2_n2;
+
+ if (set == M1_N1) {
+ dp_m_n = &crtc->config.dp_m_n;
+ dp_m2_n2 = &crtc->config.dp_m2_n2;
+ } else if (set == M2_N2) {
+ /* Only one register programming is supported */
+ dp_m_n = &crtc->config.dp_m_n;
+ dp_m2_n2 = NULL;
+ } else {
+ DRM_ERROR("Unsupported divider value\n");
+ return;
+ }
+
if (crtc->config.has_pch_encoder)
intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
else
- intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
- &crtc->config.dp_m2_n2);
+ intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
}
static void vlv_update_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index b315292..784b8dd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4817,11 +4817,10 @@ static void intel_dp_set_drrs_state(struct
drm_device *dev, int refresh_rate)
if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
switch(index) {
case DRRS_HIGH_RR:
- intel_dp_set_m_n(intel_crtc);
+ intel_dp_set_m_n(intel_crtc, M1_N1);
break;
case DRRS_LOW_RR:
- intel_cpu_transcoder_set_m_n(intel_crtc,
- &intel_crtc->config.dp_m2_n2, NULL);
+ intel_dp_set_m_n(intel_crtc, M2_N2);
break;
case DRRS_MAX_RR:
default:
@@ -4835,7 +4834,6 @@ static void intel_dp_set_drrs_state(struct
drm_device *dev, int refresh_rate)
val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
else
val |= PIPECONF_EDP_RR_MODE_SWITCH;
- intel_dp_set_m_n(intel_crtc);
} else {
if (IS_VALLEYVIEW(dev))
val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index 86d31f2..910e613 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,6 +595,12 @@ struct intel_hdmi {
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS 0x10
+enum link_m_n_set {
+ M1_N1 = 0,
+ M2_N2,
+ DIVIDER_MAX
+};
+
struct intel_dp {
uint32_t output_reg;
uint32_t aux_ch_ctl_reg;
@@ -983,7 +989,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set =
M1_N1);
void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n,
struct intel_link_m_n *m2_n2);
--
1.7.9.5
>
>> I915_WRITE(PIPE_DATA_M2(transcoder),
>> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
>> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 3362d93..42195fe 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> return;
>> }
>>
>> - if (INTEL_INFO(dev)->gen >= 8) {
>> + if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
>> switch(index) {
>> case DRRS_HIGH_RR:
>> intel_dp_set_m_n(intel_crtc);
>> --
>> 2.0.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
--Ram
[-- Attachment #1.2: Type: text/html, Size: 17909 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-21 12:13 ` Ramalingam C
@ 2015-01-21 15:03 ` Rodrigo Vivi
2015-01-22 10:54 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-21 15:03 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, Paulo Zanoni
On Wed, 2015-01-21 at 17:43 +0530, Ramalingam C wrote:
> Hi
>
> On Friday 16 January 2015 04:41 AM, Rodrigo Vivi wrote:
>
> > On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> > <vandana.kannan@intel.com> wrote:
> > > From: Durgadoss R <durgadoss.r@intel.com>
> > >
> > > This patch enables eDP DRRS for CHV by adding the
> > > required IS_CHERRYVIEW() checks.
> > > CHV uses the same register bit as VLV.
> > >
> > > [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
> > > path as gen < 8. Added CHV check in dp_set_m_n()
> > >
> > > Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
> > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 4 ++--
> > > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > > 2 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 25596ca..bb44fb9 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> > > * for gen < 8) and if DRRS is supported (to make sure the
> > > * registers are not unnecessarily accessed).
> > > */
> > > - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> > > - crtc->config.has_drrs) {
> > > + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
> > > + && crtc->config.has_drrs) {
> > This change here doesn't seem safe. As I told on previous comment I'd
> > prefer changing intel_dp_set_m_n instead of re-using this intel_cpu
> > one...
> Though I am rewriting the intel_dp_set_m_n() that will reuse
> intel_cpu_transcoder_set_m_n() within.
> But as a result, i am going to avoid the parallel usage of
> intel_cpu_transcoder_set_m_n() and intel_dp_set_m_n().
> So I am afraid this check for inclusion of cherryview for m2_n2
> programming will be part of the newer code also.
>
> Appending the RFC for the newer intel_dp_set_m_n() implementation
> below. Please review.
>
> RFC starts here:
>
> drivers/gpu/drm/i915/intel_display.c | 19
> ++++++++++++++++---
> drivers/gpu/drm/i915/intel_dp.c | 6
> ++----
> drivers/gpu/drm/i915/intel_drv.h | 8
> +++++++-
> 3 files changed, 25 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 061a253..59cc87f
> 100644
> ---
> a/drivers/gpu/drm/i915/intel_display.c
> +++
> b/drivers/gpu/drm/i915/intel_display.c
> @@ -5829,13 +5829,26 @@ void intel_cpu_transcoder_set_m_n(struct
> intel_crtc *crtc,
> }
> }
>
> -void intel_dp_set_m_n(struct intel_crtc
> *crtc)
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set
> = M1_N1)
> {
> + struct intel_link_m_n *dp_m_n,
> *dp_m2_n2;
> +
> + if (set == M1_N1)
> {
> + dp_m_n =
> &crtc->config.dp_m_n;
> + dp_m2_n2 =
> &crtc->config.dp_m2_n2;
> + } else if (set == M2_N2)
> {
> + /* Only one register programming is supported
> */
> + dp_m_n =
> &crtc->config.dp_m_n;
> + dp_m2_n2 =
> NULL;
> + } else
> {
> + DRM_ERROR("Unsupported divider value
> \n");
> +
> return;
> + }
> +
> if
> (crtc->config.has_pch_encoder)
> intel_pch_transcoder_set_m_n(crtc,
> &crtc->config.dp_m_n);
>
> else
> - intel_cpu_transcoder_set_m_n(crtc,
> &crtc->config.dp_m_n,
> -
> &crtc->config.dp_m2_n2);
> + intel_cpu_transcoder_set_m_n(crtc, dp_m_n,
> dp_m2_n2);
> }
>
> static void vlv_update_pll(struct intel_crtc
> *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index b315292..784b8dd
> 100644
> ---
> a/drivers/gpu/drm/i915/intel_dp.c
> +++
> b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4817,11 +4817,10 @@ static void intel_dp_set_drrs_state(struct
> drm_device *dev, int refresh_rate)
> if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))
> {
> switch(index)
> {
> case
> DRRS_HIGH_RR:
> -
> intel_dp_set_m_n(intel_crtc);
> + intel_dp_set_m_n(intel_crtc,
> M1_N1);
>
> break;
> case
> DRRS_LOW_RR:
> -
> intel_cpu_transcoder_set_m_n(intel_crtc,
> - &intel_crtc->config.dp_m2_n2,
> NULL);
> + intel_dp_set_m_n(intel_crtc,
> M2_N2);
>
> break;
> case
> DRRS_MAX_RR:
>
> default:
> @@ -4835,7 +4834,6 @@ static void intel_dp_set_drrs_state(struct
> drm_device *dev, int refresh_rate)
> val |=
> PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>
> else
> val |=
> PIPECONF_EDP_RR_MODE_SWITCH;
> -
> intel_dp_set_m_n(intel_crtc);
> } else
> {
> if
> (IS_VALLEYVIEW(dev))
> val &=
> ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 86d31f2..910e613
> 100644
> ---
> a/drivers/gpu/drm/i915/intel_drv.h
> +++
> b/drivers/gpu/drm/i915/intel_drv.h
> @@ -595,6 +595,12 @@ struct intel_hdmi
> {
> struct
> intel_dp_mst_encoder;
> #define DP_MAX_DOWNSTREAM_PORTS
> 0x10
>
> +enum link_m_n_set
> {
> + M1_N1 =
> 0,
> +
> M2_N2,
> +
> DIVIDER_MAX
do we need this divider_max here?
> +};
> +
> struct intel_dp
> {
> uint32_t
> output_reg;
> uint32_t
> aux_ch_ctl_reg;
> @@ -983,7 +989,7 @@ void hsw_enable_pc8(struct drm_i915_private
> *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private
> *dev_priv);
> void intel_dp_get_m_n(struct intel_crtc
> *crtc,
> struct intel_crtc_config
> *pipe_config);
> -void intel_dp_set_m_n(struct intel_crtc
> *crtc);
> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set
> = M1_N1);
> void intel_cpu_transcoder_set_m_n(struct intel_crtc
> *crtc,
> struct intel_link_m_n
> *m_n,
> struct intel_link_m_n
> *m2_n2);
> --
> 1.7.9.5
> >
> > > I915_WRITE(PIPE_DATA_M2(transcoder),
> > > TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> > > I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 3362d93..42195fe 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> > > return;
> > > }
> > >
> > > - if (INTEL_INFO(dev)->gen >= 8) {
> > > + if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
> > > switch(index) {
> > > case DRRS_HIGH_RR:
> > > intel_dp_set_m_n(intel_crtc);
> > > --
> > > 2.0.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> --Ram
But overall it is better and much more clear than previous version.
Thanks
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-21 15:03 ` Rodrigo Vivi
@ 2015-01-22 10:54 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 10:54 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni
[-- Attachment #1.1: Type: text/plain, Size: 8113 bytes --]
On Wednesday 21 January 2015 08:33 PM, Rodrigo Vivi wrote:
> On Wed, 2015-01-21 at 17:43 +0530, Ramalingam C wrote:
>> Hi
>>
>> On Friday 16 January 2015 04:41 AM, Rodrigo Vivi wrote:
>>
>>> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
>>> <vandana.kannan@intel.com> wrote:
>>>> From: Durgadoss R <durgadoss.r@intel.com>
>>>>
>>>> This patch enables eDP DRRS for CHV by adding the
>>>> required IS_CHERRYVIEW() checks.
>>>> CHV uses the same register bit as VLV.
>>>>
>>>> [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
>>>> path as gen < 8. Added CHV check in dp_set_m_n()
>>>>
>>>> Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
>>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/intel_display.c | 4 ++--
>>>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>>>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>> index 25596ca..bb44fb9 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>>>> * for gen < 8) and if DRRS is supported (to make sure the
>>>> * registers are not unnecessarily accessed).
>>>> */
>>>> - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
>>>> - crtc->config.has_drrs) {
>>>> + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
>>>> + && crtc->config.has_drrs) {
>>> This change here doesn't seem safe. As I told on previous comment I'd
>>> prefer changing intel_dp_set_m_n instead of re-using this intel_cpu
>>> one...
>> Though I am rewriting the intel_dp_set_m_n() that will reuse
>> intel_cpu_transcoder_set_m_n() within.
>> But as a result, i am going to avoid the parallel usage of
>> intel_cpu_transcoder_set_m_n() and intel_dp_set_m_n().
>> So I am afraid this check for inclusion of cherryview for m2_n2
>> programming will be part of the newer code also.
>>
>> Appending the RFC for the newer intel_dp_set_m_n() implementation
>> below. Please review.
>>
>> RFC starts here:
>>
>> drivers/gpu/drm/i915/intel_display.c | 19
>> ++++++++++++++++---
>> drivers/gpu/drm/i915/intel_dp.c | 6
>> ++----
>> drivers/gpu/drm/i915/intel_drv.h | 8
>> +++++++-
>> 3 files changed, 25 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 061a253..59cc87f
>> 100644
>> ---
>> a/drivers/gpu/drm/i915/intel_display.c
>> +++
>> b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5829,13 +5829,26 @@ void intel_cpu_transcoder_set_m_n(struct
>> intel_crtc *crtc,
>> }
>> }
>>
>> -void intel_dp_set_m_n(struct intel_crtc
>> *crtc)
>> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set
>> = M1_N1)
>> {
>> + struct intel_link_m_n *dp_m_n,
>> *dp_m2_n2;
>> +
>> + if (set == M1_N1)
>> {
>> + dp_m_n =
>> &crtc->config.dp_m_n;
>> + dp_m2_n2 =
>> &crtc->config.dp_m2_n2;
>> + } else if (set == M2_N2)
>> {
>> + /* Only one register programming is supported
>> */
>> + dp_m_n =
>> &crtc->config.dp_m_n;
>> + dp_m2_n2 =
>> NULL;
>> + } else
>> {
>> + DRM_ERROR("Unsupported divider value
>> \n");
>> +
>> return;
>> + }
>> +
>> if
>> (crtc->config.has_pch_encoder)
>> intel_pch_transcoder_set_m_n(crtc,
>> &crtc->config.dp_m_n);
>>
>> else
>> - intel_cpu_transcoder_set_m_n(crtc,
>> &crtc->config.dp_m_n,
>> -
>> &crtc->config.dp_m2_n2);
>> + intel_cpu_transcoder_set_m_n(crtc, dp_m_n,
>> dp_m2_n2);
>> }
>>
>> static void vlv_update_pll(struct intel_crtc
>> *crtc,
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index b315292..784b8dd
>> 100644
>> ---
>> a/drivers/gpu/drm/i915/intel_dp.c
>> +++
>> b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4817,11 +4817,10 @@ static void intel_dp_set_drrs_state(struct
>> drm_device *dev, int refresh_rate)
>> if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))
>> {
>> switch(index)
>> {
>> case
>> DRRS_HIGH_RR:
>> -
>> intel_dp_set_m_n(intel_crtc);
>> + intel_dp_set_m_n(intel_crtc,
>> M1_N1);
>>
>> break;
>> case
>> DRRS_LOW_RR:
>> -
>> intel_cpu_transcoder_set_m_n(intel_crtc,
>> - &intel_crtc->config.dp_m2_n2,
>> NULL);
>> + intel_dp_set_m_n(intel_crtc,
>> M2_N2);
>>
>> break;
>> case
>> DRRS_MAX_RR:
>>
>> default:
>> @@ -4835,7 +4834,6 @@ static void intel_dp_set_drrs_state(struct
>> drm_device *dev, int refresh_rate)
>> val |=
>> PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>>
>> else
>> val |=
>> PIPECONF_EDP_RR_MODE_SWITCH;
>> -
>> intel_dp_set_m_n(intel_crtc);
>> } else
>> {
>> if
>> (IS_VALLEYVIEW(dev))
>> val &=
>> ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 86d31f2..910e613
>> 100644
>> ---
>> a/drivers/gpu/drm/i915/intel_drv.h
>> +++
>> b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -595,6 +595,12 @@ struct intel_hdmi
>> {
>> struct
>> intel_dp_mst_encoder;
>> #define DP_MAX_DOWNSTREAM_PORTS
>> 0x10
>>
>> +enum link_m_n_set
>> {
>> + M1_N1 =
>> 0,
>> +
>> M2_N2,
>> +
>> DIVIDER_MAX
> do we need this divider_max here?
We dont need this. Removed it in the original patch.
>
>> +};
>> +
>> struct intel_dp
>> {
>> uint32_t
>> output_reg;
>> uint32_t
>> aux_ch_ctl_reg;
>> @@ -983,7 +989,7 @@ void hsw_enable_pc8(struct drm_i915_private
>> *dev_priv);
>> void hsw_disable_pc8(struct drm_i915_private
>> *dev_priv);
>> void intel_dp_get_m_n(struct intel_crtc
>> *crtc,
>> struct intel_crtc_config
>> *pipe_config);
>> -void intel_dp_set_m_n(struct intel_crtc
>> *crtc);
>> +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set set
>> = M1_N1);
>> void intel_cpu_transcoder_set_m_n(struct intel_crtc
>> *crtc,
>> struct intel_link_m_n
>> *m_n,
>> struct intel_link_m_n
>> *m2_n2);
>> --
>> 1.7.9.5
>>>> I915_WRITE(PIPE_DATA_M2(transcoder),
>>>> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
>>>> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>>> index 3362d93..42195fe 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>>> @@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>>>> return;
>>>> }
>>>>
>>>> - if (INTEL_INFO(dev)->gen >= 8) {
>>>> + if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
>>>> switch(index) {
>>>> case DRRS_HIGH_RR:
>>>> intel_dp_set_m_n(intel_crtc);
>>>> --
>>>> 2.0.1
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>> --Ram
>
> But overall it is better and much more clear than previous version.
I have submitted this change for the intel_dp_set_m_n() as V2 of patch
set 5/10. So this patch [7/10] doesn't have any change.
> Thanks
>
--Ram
[-- Attachment #1.2: Type: text/html, Size: 12545 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV
2015-01-09 20:56 ` [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV Vandana Kannan
2015-01-15 23:11 ` Rodrigo Vivi
@ 2015-01-24 0:05 ` Rodrigo Vivi
1 sibling, 0 replies; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-24 0:05 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> From: Durgadoss R <durgadoss.r@intel.com>
>
> This patch enables eDP DRRS for CHV by adding the
> required IS_CHERRYVIEW() checks.
> CHV uses the same register bit as VLV.
>
> [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
> path as gen < 8. Added CHV check in dp_set_m_n()
>
> Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 25596ca..bb44fb9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5810,8 +5810,8 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> * for gen < 8) and if DRRS is supported (to make sure the
> * registers are not unnecessarily accessed).
> */
> - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> - crtc->config.has_drrs) {
> + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8)
> + && crtc->config.has_drrs) {
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3362d93..42195fe 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4802,7 +4802,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> return;
> }
>
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
> switch(index) {
> case DRRS_HIGH_RR:
> intel_dp_set_m_n(intel_crtc);
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 8/10] Documentation/drm: DocBook integration for DRRS
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (6 preceding siblings ...)
2015-01-09 20:56 ` [PATCH 7/10] drm/i915: Enable eDP DRRS for CHV Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-15 23:16 ` Rodrigo Vivi
2015-01-09 20:56 ` [PATCH 9/10] drm/i915: Add debugfs entry " Vandana Kannan
2015-01-09 20:56 ` [PATCH 10/10] kms_drrs: Test DRRS entry and exit Vandana Kannan
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Adding an overview of DRRS in general and the implementation for eDP DRRS.
Also, describing the functions related to eDP DRRS.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
Documentation/DocBook/drm.tmpl | 11 +++++
drivers/gpu/drm/i915/intel_dp.c | 95 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 106 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 3b2571e..8c844b4 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4042,6 +4042,17 @@ int num_ioctls;</synopsis>
!Idrivers/gpu/drm/i915/intel_fbc.c
</sect2>
<sect2>
+ <title>Display Refresh Rate Switching (DRRS)</title>
+!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init
+
+ </sect2>
+ <sect2>
<title>DPIO</title>
!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
<table id="dpiox2">
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 42195fe..eda90d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4745,6 +4745,18 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_READ(pp_div_reg));
}
+/**
+ * intel_dp_set_drrs_state - program registers for RR switch to take effect
+ * @dev: DRM device
+ * @refresh_rate: RR to be programmed
+ *
+ * This function gets called when refresh rate (RR) has to be changed from
+ * one frequency to another. Switches can be between high and low RR
+ * supported by the panel or to any other RR based on media playback (in
+ * this case, RR value needs to be passed from user space).
+ *
+ * The caller of this function needs to take a lock on dev_priv->drrs.
+ */
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4838,6 +4850,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}
+/**
+ * intel_edp_drrs_enable - init drrs struct if supported
+ * @intel_dp: DP struct
+ *
+ * Initializes frontbuffer_bits and drrs.dp
+ */
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -4864,6 +4882,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
mutex_unlock(&dev_priv->drrs.mutex);
}
+/**
+ * intel_edp_drrs_disable - Disable DRRS
+ * @intel_dp: DP struct
+ *
+ */
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -4921,6 +4944,17 @@ unlock:
mutex_unlock(&dev_priv->drrs.mutex);
}
+/**
+ * intel_edp_drrs_invalidate - Invalidate DRRS
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * When there is a disturbance on screen (due to cursor movement/time
+ * update etc), DRRS needs to be invalidated, i.e. need to switch to
+ * high RR.
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
void intel_edp_drrs_invalidate(struct drm_device *dev,
unsigned frontbuffer_bits)
{
@@ -4948,6 +4982,17 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
mutex_unlock(&dev_priv->drrs.mutex);
}
+/**
+ * intel_edp_drrs_flush - Flush DRRS
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * When there is no movement on screen, DRRS work can be scheduled.
+ * This DRRS work is responsible for setting relevant registers after a
+ * timeout of 1 second.
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
void intel_edp_drrs_flush(struct drm_device *dev,
unsigned frontbuffer_bits)
{
@@ -4972,6 +5017,56 @@ void intel_edp_drrs_flush(struct drm_device *dev,
mutex_unlock(&dev_priv->drrs.mutex);
}
+/**
+ * DOC: Display Refresh Rate Switching (DRRS)
+ *
+ * Display Refresh Rate Switching (DRRS) is a power conservation feature
+ * which enables swtching between low and high refresh rates,
+ * dynamically, based on the usage scenario. This feature is applicable
+ * for internal panels.
+ *
+ * Indication that the panel supports DRRS is given by the panel EDID, which
+ * would list multiple refresh rates for one resolution.
+ *
+ * DRRS is of 2 types - static and seamless.
+ * Static DRRS involves changing refresh rate (RR) by doing a full modeset
+ * (may appear as a blink on screen) and is used in dock-undock scenario.
+ * Seamless DRRS involves changing RR without any visual effect to the user
+ * and can be used during normal system usage. This is done by programming
+ * certain registers.
+ *
+ * Support for static/seamless DRRS may be indicated in the VBT based on
+ * inputs from the panel spec.
+ *
+ * DRRS saves power by switching to low RR based on usage scenarios.
+ *
+ * eDP DRRS:-
+ * The implementation is based on frontbuffer tracking implementation.
+ * When there is a disturbance on the screen triggered by user activity or a
+ * periodic system activity, DRRS is disabled (RR is changed to high RR).
+ * When there is no movement on screen, after a timeout of 1 second, a switch
+ * to low RR is made.
+ * For integration with frontbuffer tracking code,
+ * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
+ *
+ * DRRS can be further extended to support other internal panels and also
+ * the scenario of video playback wherein RR is set based on the rate
+ * requested by userspace.
+ */
+
+/**
+ * intel_dp_drrs_init - Init basic DRRS work and mutex.
+ * @intel_connector: eDP connector
+ * @fixed_mode: preferred mode of panel
+ *
+ * This function is called only once at driver load to initialize basic
+ * DRRS stuff.
+ *
+ * Returns:
+ * Downclock mode if panel supports it, else return NULL.
+ * DRRS support is determined by the presence of downclock mode (apart
+ * from VBT setting).
+ */
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_connector *intel_connector,
struct drm_display_mode *fixed_mode)
--
2.0.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 8/10] Documentation/drm: DocBook integration for DRRS
2015-01-09 20:56 ` [PATCH 8/10] Documentation/drm: DocBook integration for DRRS Vandana Kannan
@ 2015-01-15 23:16 ` Rodrigo Vivi
2015-01-20 9:12 ` Daniel Vetter
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:16 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
Great!
Although I'd prefer at intel_drrs.c.. ;)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> Adding an overview of DRRS in general and the implementation for eDP DRRS.
> Also, describing the functions related to eDP DRRS.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> Documentation/DocBook/drm.tmpl | 11 +++++
> drivers/gpu/drm/i915/intel_dp.c | 95 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 106 insertions(+)
>
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index 3b2571e..8c844b4 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4042,6 +4042,17 @@ int num_ioctls;</synopsis>
> !Idrivers/gpu/drm/i915/intel_fbc.c
> </sect2>
> <sect2>
> + <title>Display Refresh Rate Switching (DRRS)</title>
> +!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush
> +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init
> +
> + </sect2>
> + <sect2>
> <title>DPIO</title>
> !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
> <table id="dpiox2">
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 42195fe..eda90d6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4745,6 +4745,18 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> I915_READ(pp_div_reg));
> }
>
> +/**
> + * intel_dp_set_drrs_state - program registers for RR switch to take effect
> + * @dev: DRM device
> + * @refresh_rate: RR to be programmed
> + *
> + * This function gets called when refresh rate (RR) has to be changed from
> + * one frequency to another. Switches can be between high and low RR
> + * supported by the panel or to any other RR based on media playback (in
> + * this case, RR value needs to be passed from user space).
> + *
> + * The caller of this function needs to take a lock on dev_priv->drrs.
> + */
> static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4838,6 +4850,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> }
>
> +/**
> + * intel_edp_drrs_enable - init drrs struct if supported
> + * @intel_dp: DP struct
> + *
> + * Initializes frontbuffer_bits and drrs.dp
> + */
> void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> @@ -4864,6 +4882,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +/**
> + * intel_edp_drrs_disable - Disable DRRS
> + * @intel_dp: DP struct
> + *
> + */
> void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> @@ -4921,6 +4944,17 @@ unlock:
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +/**
> + * intel_edp_drrs_invalidate - Invalidate DRRS
> + * @dev: DRM device
> + * @frontbuffer_bits: frontbuffer plane tracking bits
> + *
> + * When there is a disturbance on screen (due to cursor movement/time
> + * update etc), DRRS needs to be invalidated, i.e. need to switch to
> + * high RR.
> + *
> + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> + */
> void intel_edp_drrs_invalidate(struct drm_device *dev,
> unsigned frontbuffer_bits)
> {
> @@ -4948,6 +4982,17 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +/**
> + * intel_edp_drrs_flush - Flush DRRS
> + * @dev: DRM device
> + * @frontbuffer_bits: frontbuffer plane tracking bits
> + *
> + * When there is no movement on screen, DRRS work can be scheduled.
> + * This DRRS work is responsible for setting relevant registers after a
> + * timeout of 1 second.
> + *
> + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> + */
> void intel_edp_drrs_flush(struct drm_device *dev,
> unsigned frontbuffer_bits)
> {
> @@ -4972,6 +5017,56 @@ void intel_edp_drrs_flush(struct drm_device *dev,
> mutex_unlock(&dev_priv->drrs.mutex);
> }
>
> +/**
> + * DOC: Display Refresh Rate Switching (DRRS)
> + *
> + * Display Refresh Rate Switching (DRRS) is a power conservation feature
> + * which enables swtching between low and high refresh rates,
> + * dynamically, based on the usage scenario. This feature is applicable
> + * for internal panels.
> + *
> + * Indication that the panel supports DRRS is given by the panel EDID, which
> + * would list multiple refresh rates for one resolution.
> + *
> + * DRRS is of 2 types - static and seamless.
> + * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> + * (may appear as a blink on screen) and is used in dock-undock scenario.
> + * Seamless DRRS involves changing RR without any visual effect to the user
> + * and can be used during normal system usage. This is done by programming
> + * certain registers.
> + *
> + * Support for static/seamless DRRS may be indicated in the VBT based on
> + * inputs from the panel spec.
> + *
> + * DRRS saves power by switching to low RR based on usage scenarios.
> + *
> + * eDP DRRS:-
> + * The implementation is based on frontbuffer tracking implementation.
> + * When there is a disturbance on the screen triggered by user activity or a
> + * periodic system activity, DRRS is disabled (RR is changed to high RR).
> + * When there is no movement on screen, after a timeout of 1 second, a switch
> + * to low RR is made.
> + * For integration with frontbuffer tracking code,
> + * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
> + *
> + * DRRS can be further extended to support other internal panels and also
> + * the scenario of video playback wherein RR is set based on the rate
> + * requested by userspace.
> + */
> +
> +/**
> + * intel_dp_drrs_init - Init basic DRRS work and mutex.
> + * @intel_connector: eDP connector
> + * @fixed_mode: preferred mode of panel
> + *
> + * This function is called only once at driver load to initialize basic
> + * DRRS stuff.
> + *
> + * Returns:
> + * Downclock mode if panel supports it, else return NULL.
> + * DRRS support is determined by the presence of downclock mode (apart
> + * from VBT setting).
> + */
> static struct drm_display_mode *
> intel_dp_drrs_init(struct intel_connector *intel_connector,
> struct drm_display_mode *fixed_mode)
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 8/10] Documentation/drm: DocBook integration for DRRS
2015-01-15 23:16 ` Rodrigo Vivi
@ 2015-01-20 9:12 ` Daniel Vetter
0 siblings, 0 replies; 64+ messages in thread
From: Daniel Vetter @ 2015-01-20 9:12 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Vivi, Rodrigo, Paulo Zanoni
On Thu, Jan 15, 2015 at 03:16:35PM -0800, Rodrigo Vivi wrote:
> Great!
>
> Although I'd prefer at intel_drrs.c.. ;)
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
> > Adding an overview of DRRS in general and the implementation for eDP DRRS.
> > Also, describing the functions related to eDP DRRS.
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > ---
> > Documentation/DocBook/drm.tmpl | 11 +++++
> > drivers/gpu/drm/i915/intel_dp.c | 95 +++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 106 insertions(+)
> >
> > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> > index 3b2571e..8c844b4 100644
> > --- a/Documentation/DocBook/drm.tmpl
> > +++ b/Documentation/DocBook/drm.tmpl
> > @@ -4042,6 +4042,17 @@ int num_ioctls;</synopsis>
> > !Idrivers/gpu/drm/i915/intel_fbc.c
> > </sect2>
> > <sect2>
> > + <title>Display Refresh Rate Switching (DRRS)</title>
> > +!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush
> > +!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init
Yeah extracting intel_drrs.c would be better since then we could just
slurp in everything from that file. But better to do that once the patches
have all been merged.
Wrt the series I've merged the first patch, for the others there seems to
still be some review comments (and a bit of rebasing) pending.
-Daniel
> > +
> > + </sect2>
> > + <sect2>
> > <title>DPIO</title>
> > !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
> > <table id="dpiox2">
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 42195fe..eda90d6 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4745,6 +4745,18 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > I915_READ(pp_div_reg));
> > }
> >
> > +/**
> > + * intel_dp_set_drrs_state - program registers for RR switch to take effect
> > + * @dev: DRM device
> > + * @refresh_rate: RR to be programmed
> > + *
> > + * This function gets called when refresh rate (RR) has to be changed from
> > + * one frequency to another. Switches can be between high and low RR
> > + * supported by the panel or to any other RR based on media playback (in
> > + * this case, RR value needs to be passed from user space).
> > + *
> > + * The caller of this function needs to take a lock on dev_priv->drrs.
> > + */
> > static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4838,6 +4850,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> > DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> > }
> >
> > +/**
> > + * intel_edp_drrs_enable - init drrs struct if supported
> > + * @intel_dp: DP struct
> > + *
> > + * Initializes frontbuffer_bits and drrs.dp
> > + */
> > void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> > {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > @@ -4864,6 +4882,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> > mutex_unlock(&dev_priv->drrs.mutex);
> > }
> >
> > +/**
> > + * intel_edp_drrs_disable - Disable DRRS
> > + * @intel_dp: DP struct
> > + *
> > + */
> > void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> > {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > @@ -4921,6 +4944,17 @@ unlock:
> > mutex_unlock(&dev_priv->drrs.mutex);
> > }
> >
> > +/**
> > + * intel_edp_drrs_invalidate - Invalidate DRRS
> > + * @dev: DRM device
> > + * @frontbuffer_bits: frontbuffer plane tracking bits
> > + *
> > + * When there is a disturbance on screen (due to cursor movement/time
> > + * update etc), DRRS needs to be invalidated, i.e. need to switch to
> > + * high RR.
> > + *
> > + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > + */
> > void intel_edp_drrs_invalidate(struct drm_device *dev,
> > unsigned frontbuffer_bits)
> > {
> > @@ -4948,6 +4982,17 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
> > mutex_unlock(&dev_priv->drrs.mutex);
> > }
> >
> > +/**
> > + * intel_edp_drrs_flush - Flush DRRS
> > + * @dev: DRM device
> > + * @frontbuffer_bits: frontbuffer plane tracking bits
> > + *
> > + * When there is no movement on screen, DRRS work can be scheduled.
> > + * This DRRS work is responsible for setting relevant registers after a
> > + * timeout of 1 second.
> > + *
> > + * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
> > + */
> > void intel_edp_drrs_flush(struct drm_device *dev,
> > unsigned frontbuffer_bits)
> > {
> > @@ -4972,6 +5017,56 @@ void intel_edp_drrs_flush(struct drm_device *dev,
> > mutex_unlock(&dev_priv->drrs.mutex);
> > }
> >
> > +/**
> > + * DOC: Display Refresh Rate Switching (DRRS)
> > + *
> > + * Display Refresh Rate Switching (DRRS) is a power conservation feature
> > + * which enables swtching between low and high refresh rates,
> > + * dynamically, based on the usage scenario. This feature is applicable
> > + * for internal panels.
> > + *
> > + * Indication that the panel supports DRRS is given by the panel EDID, which
> > + * would list multiple refresh rates for one resolution.
> > + *
> > + * DRRS is of 2 types - static and seamless.
> > + * Static DRRS involves changing refresh rate (RR) by doing a full modeset
> > + * (may appear as a blink on screen) and is used in dock-undock scenario.
> > + * Seamless DRRS involves changing RR without any visual effect to the user
> > + * and can be used during normal system usage. This is done by programming
> > + * certain registers.
> > + *
> > + * Support for static/seamless DRRS may be indicated in the VBT based on
> > + * inputs from the panel spec.
> > + *
> > + * DRRS saves power by switching to low RR based on usage scenarios.
> > + *
> > + * eDP DRRS:-
> > + * The implementation is based on frontbuffer tracking implementation.
> > + * When there is a disturbance on the screen triggered by user activity or a
> > + * periodic system activity, DRRS is disabled (RR is changed to high RR).
> > + * When there is no movement on screen, after a timeout of 1 second, a switch
> > + * to low RR is made.
> > + * For integration with frontbuffer tracking code,
> > + * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
> > + *
> > + * DRRS can be further extended to support other internal panels and also
> > + * the scenario of video playback wherein RR is set based on the rate
> > + * requested by userspace.
> > + */
> > +
> > +/**
> > + * intel_dp_drrs_init - Init basic DRRS work and mutex.
> > + * @intel_connector: eDP connector
> > + * @fixed_mode: preferred mode of panel
> > + *
> > + * This function is called only once at driver load to initialize basic
> > + * DRRS stuff.
> > + *
> > + * Returns:
> > + * Downclock mode if panel supports it, else return NULL.
> > + * DRRS support is determined by the presence of downclock mode (apart
> > + * from VBT setting).
> > + */
> > static struct drm_display_mode *
> > intel_dp_drrs_init(struct intel_connector *intel_connector,
> > struct drm_display_mode *fixed_mode)
> > --
> > 2.0.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 9/10] drm/i915: Add debugfs entry for DRRS
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (7 preceding siblings ...)
2015-01-09 20:56 ` [PATCH 8/10] Documentation/drm: DocBook integration for DRRS Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-11 12:40 ` Chris Wilson
2015-01-09 20:56 ` [PATCH 10/10] kms_drrs: Test DRRS entry and exit Vandana Kannan
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
Adding a debugfs entry to determine if DRRS is supported or not
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e515aad..544b4c3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2825,6 +2825,23 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_drrs_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(dev, crtc) {
+ if (crtc->active) {
+ if (crtc->config.has_drrs)
+ seq_puts(m, "DRRS enabled");
+ else
+ seq_puts(m, "DRRS disabled");
+ }
+ }
+ return 0;
+}
+
struct pipe_crc_info {
const char *name;
struct drm_device *dev;
@@ -4437,6 +4454,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
{"i915_ddb_info", i915_ddb_info, 0},
+ {"i915_drrs_status", i915_drrs_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
2.0.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 9/10] drm/i915: Add debugfs entry for DRRS
2015-01-09 20:56 ` [PATCH 9/10] drm/i915: Add debugfs entry " Vandana Kannan
@ 2015-01-11 12:40 ` Chris Wilson
2015-01-15 23:18 ` Rodrigo Vivi
0 siblings, 1 reply; 64+ messages in thread
From: Chris Wilson @ 2015-01-11 12:40 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi
On Sat, Jan 10, 2015 at 02:26:04AM +0530, Vandana Kannan wrote:
> Adding a debugfs entry to determine if DRRS is supported or not
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e515aad..544b4c3 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2825,6 +2825,23 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static int i915_drrs_status(struct seq_file *m, void *unused)
> +{
> + struct drm_info_node *node = m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(dev, crtc) {
> + if (crtc->active) {
Don't you want to know which CRTC this is? Would this not be better
extending display_info with the extra CRTC status?
> + if (crtc->config.has_drrs)
> + seq_puts(m, "DRRS enabled");
> + else
> + seq_puts(m, "DRRS disabled");
> + }
> + }
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 9/10] drm/i915: Add debugfs entry for DRRS
2015-01-11 12:40 ` Chris Wilson
@ 2015-01-15 23:18 ` Rodrigo Vivi
2015-01-21 12:26 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:18 UTC (permalink / raw)
To: Chris Wilson, Vandana Kannan, intel-gfx, Paulo Zanoni,
Vivi, Rodrigo
On Sun, Jan 11, 2015 at 4:40 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Sat, Jan 10, 2015 at 02:26:04AM +0530, Vandana Kannan wrote:
>> Adding a debugfs entry to determine if DRRS is supported or not
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index e515aad..544b4c3 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2825,6 +2825,23 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>> return 0;
>> }
>>
>> +static int i915_drrs_status(struct seq_file *m, void *unused)
>> +{
>> + struct drm_info_node *node = m->private;
>> + struct drm_device *dev = node->minor->dev;
>> + struct intel_crtc *crtc;
>> +
>> + for_each_intel_crtc(dev, crtc) {
>> + if (crtc->active) {
>
> Don't you want to know which CRTC this is? Would this not be better
> extending display_info with the extra CRTC status?
>
>> + if (crtc->config.has_drrs)
Also it just shows if panel supports drrs, not if it is enabled...
>> + seq_puts(m, "DRRS enabled");
>> + else
>> + seq_puts(m, "DRRS disabled");
>> + }
>> + }
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 9/10] drm/i915: Add debugfs entry for DRRS
2015-01-15 23:18 ` Rodrigo Vivi
@ 2015-01-21 12:26 ` Ramalingam C
2015-01-22 16:45 ` [PATCH] " Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 12:26 UTC (permalink / raw)
To: Rodrigo Vivi, Chris Wilson, Vandana Kannan, intel-gfx,
Paulo Zanoni, Vivi, Rodrigo
[-- Attachment #1.1: Type: text/plain, Size: 1937 bytes --]
Hi
On Friday 16 January 2015 04:48 AM, Rodrigo Vivi wrote:
> On Sun, Jan 11, 2015 at 4:40 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> On Sat, Jan 10, 2015 at 02:26:04AM +0530, Vandana Kannan wrote:
>>> Adding a debugfs entry to determine if DRRS is supported or not
>>>
>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>> index e515aad..544b4c3 100644
>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>> @@ -2825,6 +2825,23 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>>> return 0;
>>> }
>>>
>>> +static int i915_drrs_status(struct seq_file *m, void *unused)
>>> +{
>>> + struct drm_info_node *node = m->private;
>>> + struct drm_device *dev = node->minor->dev;
>>> + struct intel_crtc *crtc;
>>> +
>>> + for_each_intel_crtc(dev, crtc) {
>>> + if (crtc->active) {
>> Don't you want to know which CRTC this is? Would this not be better
>> extending display_info with the extra CRTC status?
>>
>>> + if (crtc->config.has_drrs)
> Also it just shows if panel supports drrs, not if it is enabled...
Yes. We need to provide information on the platform's DRRS capability, crtc
and the current DRRS state (LOW_RR/HIGH_RR). I am working on the same.
>
>>> + seq_puts(m, "DRRS enabled");
>>> + else
>>> + seq_puts(m, "DRRS disabled");
>>> + }
>>> + }
>> -Chris
>>
>> --
>> Chris Wilson, Intel Open Source Technology Centre
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
--Ram
[-- Attachment #1.2: Type: text/html, Size: 3231 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-21 12:26 ` Ramalingam C
@ 2015-01-22 16:45 ` Ramalingam C
2015-01-23 16:03 ` Daniel Vetter
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-22 16:45 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi, chris; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 93 +++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ad4c48..47f1f65 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2819,6 +2819,98 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_drrs_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_drrs *drrs = &dev_priv->drrs;
+ struct intel_crtc *intel_crtc;
+ struct intel_encoder *intel_encoder;
+ int active_crtc_cnt = 0, vrefresh = 0;
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ if (intel_crtc->active) {
+ active_crtc_cnt++;
+ seq_puts(m, "CRTC");
+ seq_put_decimal_ull(m, ' ', active_crtc_cnt);
+ seq_puts(m, ": ");
+ for_each_encoder_on_crtc(dev, &intel_crtc->base,
+ intel_encoder) {
+ /* Encoder connected on this CRTC */
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ seq_puts(m, "Output: eDP, ");
+ break;
+ case INTEL_OUTPUT_DSI:
+ seq_puts(m, "Output: DSI, ");
+ break;
+ case INTEL_OUTPUT_HDMI:
+ seq_puts(m, "Output: HDMI, ");
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ seq_puts(m, "Output: DP, ");
+ break;
+ default:
+ seq_puts(m, "Output: Others (id");
+ seq_put_decimal_ull(m, '=',
+ intel_encoder->type);
+ seq_puts(m, "), ");
+ }
+ }
+
+ if (intel_crtc->config->has_drrs) {
+ struct intel_panel *panel;
+
+ panel = &drrs->dp->attached_connector->panel;
+ /* DRRS Supported */
+ seq_puts(m,
+ "DRRS Supported: Yes (Seamless), ");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ seq_puts(m,
+ "DRRS_State: DRRS_HIGH_RR, ");
+ vrefresh = panel->fixed_mode->vrefresh;
+ } else if (drrs->refresh_rate_type ==
+ DRRS_LOW_RR) {
+ seq_puts(m,
+ "DRRS_State: DRRS_LOW_RR, ");
+ vrefresh =
+ panel->downclock_mode->vrefresh;
+ } else {
+ seq_puts(m, "DRRS_State: Unknown");
+ seq_put_decimal_ull(m, '(',
+ drrs->refresh_rate_type);
+ seq_puts(m, "), ");
+ }
+ seq_puts(m, "Vrefresh:");
+ seq_put_decimal_ull(m, ' ', vrefresh);
+
+ } else {
+ /* DRRS not supported. Print the VBT parameter*/
+ seq_puts(m, "DRRS Supported : No, ");
+ if (dev_priv->vbt.drrs_type ==
+ STATIC_DRRS_SUPPORT) {
+ seq_puts(m,
+ "VBT DRRS_type: Static");
+ } else if (dev_priv->vbt.drrs_type ==
+ SEAMLESS_DRRS_SUPPORT) {
+ seq_puts(m,
+ "VBT DRRS_type: Seamless");
+ } else if (dev_priv->vbt.drrs_type ==
+ DRRS_NOT_SUPPORTED) {
+ seq_puts(m, "VBT DRRS_type: None");
+ }
+ }
+ seq_puts(m, "\n");
+ }
+ }
+
+ if (!active_crtc_cnt)
+ seq_puts(m, "No active crtc found\n");
+
+ return 0;
+}
+
struct pipe_crc_info {
const char *name;
struct drm_device *dev;
@@ -4433,6 +4525,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
{"i915_ddb_info", i915_ddb_info, 0},
+ {"i915_drrs_status", i915_drrs_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
1.7.9.5
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-22 16:45 ` [PATCH] " Ramalingam C
@ 2015-01-23 16:03 ` Daniel Vetter
2015-01-23 17:47 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Daniel Vetter @ 2015-01-23 16:03 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi
On Thu, Jan 22, 2015 at 10:15:21PM +0530, Ramalingam C wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Adding a debugfs entry to determine if DRRS is supported or not
>
> V2: [By Ram]: Following details about the active crtc will be filled
> in seq-file of the debugfs
> 1. Encoder output type
> 2. DRRS Support on this CRTC
> 3. DRRS current state
> 4. Current Vrefresh
> Format is as follows:
>
> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 93 +++++++++++++++++++++++++++++++++++
> 1 file changed, 93 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2ad4c48..47f1f65 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2819,6 +2819,98 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static int i915_drrs_status(struct seq_file *m, void *unused)
> +{
> + struct drm_info_node *node = m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct i915_drrs *drrs = &dev_priv->drrs;
> + struct intel_crtc *intel_crtc;
> + struct intel_encoder *intel_encoder;
> + int active_crtc_cnt = 0, vrefresh = 0;
> +
> + for_each_intel_crtc(dev, intel_crtc) {
> + if (intel_crtc->active) {
> + active_crtc_cnt++;
> + seq_puts(m, "CRTC");
> + seq_put_decimal_ull(m, ' ', active_crtc_cnt);
> + seq_puts(m, ": ");
> + for_each_encoder_on_crtc(dev, &intel_crtc->base,
> + intel_encoder) {
> + /* Encoder connected on this CRTC */
> + switch (intel_encoder->type) {
> + case INTEL_OUTPUT_EDP:
> + seq_puts(m, "Output: eDP, ");
> + break;
> + case INTEL_OUTPUT_DSI:
> + seq_puts(m, "Output: DSI, ");
> + break;
> + case INTEL_OUTPUT_HDMI:
> + seq_puts(m, "Output: HDMI, ");
> + break;
> + case INTEL_OUTPUT_DISPLAYPORT:
> + seq_puts(m, "Output: DP, ");
> + break;
> + default:
> + seq_puts(m, "Output: Others (id");
> + seq_put_decimal_ull(m, '=',
> + intel_encoder->type);
> + seq_puts(m, "), ");
> + }
> + }
> +
> + if (intel_crtc->config->has_drrs) {
> + struct intel_panel *panel;
> +
> + panel = &drrs->dp->attached_connector->panel;
> + /* DRRS Supported */
> + seq_puts(m,
> + "DRRS Supported: Yes (Seamless), ");
> + if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
> + seq_puts(m,
> + "DRRS_State: DRRS_HIGH_RR, ");
> + vrefresh = panel->fixed_mode->vrefresh;
> + } else if (drrs->refresh_rate_type ==
> + DRRS_LOW_RR) {
> + seq_puts(m,
> + "DRRS_State: DRRS_LOW_RR, ");
> + vrefresh =
> + panel->downclock_mode->vrefresh;
> + } else {
> + seq_puts(m, "DRRS_State: Unknown");
> + seq_put_decimal_ull(m, '(',
> + drrs->refresh_rate_type);
> + seq_puts(m, "), ");
> + }
> + seq_puts(m, "Vrefresh:");
> + seq_put_decimal_ull(m, ' ', vrefresh);
> +
> + } else {
> + /* DRRS not supported. Print the VBT parameter*/
> + seq_puts(m, "DRRS Supported : No, ");
> + if (dev_priv->vbt.drrs_type ==
> + STATIC_DRRS_SUPPORT) {
> + seq_puts(m,
> + "VBT DRRS_type: Static");
> + } else if (dev_priv->vbt.drrs_type ==
> + SEAMLESS_DRRS_SUPPORT) {
> + seq_puts(m,
> + "VBT DRRS_type: Seamless");
> + } else if (dev_priv->vbt.drrs_type ==
> + DRRS_NOT_SUPPORTED) {
> + seq_puts(m, "VBT DRRS_type: None");
> + }
> + }
This is an example of were strictly following checkpatch warnings and
pedantically breaking lines results in rather hard to read code:
The function is really long, and has about 6 indent levels. Imo it would
greatly benefit from extracting some helper functions to do the
inner-level printing. There's piles of examples in i915_debugfs where we
loop over a bunch of objects and punt all the real output to a small
helper function.
-Daniel
> + seq_puts(m, "\n");
> + }
> + }
> +
> + if (!active_crtc_cnt)
> + seq_puts(m, "No active crtc found\n");
> +
> + return 0;
> +}
> +
> struct pipe_crc_info {
> const char *name;
> struct drm_device *dev;
> @@ -4433,6 +4525,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
> {"i915_dp_mst_info", i915_dp_mst_info, 0},
> {"i915_wa_registers", i915_wa_registers, 0},
> {"i915_ddb_info", i915_ddb_info, 0},
> + {"i915_drrs_status", i915_drrs_status, 0},
> };
> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-23 16:03 ` Daniel Vetter
@ 2015-01-23 17:47 ` Ramalingam C
2015-01-23 17:52 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-23 17:47 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi
[-- Attachment #1.1: Type: text/plain, Size: 5385 bytes --]
On Friday 23 January 2015 09:33 PM, Daniel Vetter wrote:
> On Thu, Jan 22, 2015 at 10:15:21PM +0530, Ramalingam C wrote:
>> From: Vandana Kannan <vandana.kannan@intel.com>
>>
>> Adding a debugfs entry to determine if DRRS is supported or not
>>
>> V2: [By Ram]: Following details about the active crtc will be filled
>> in seq-file of the debugfs
>> 1. Encoder output type
>> 2. DRRS Support on this CRTC
>> 3. DRRS current state
>> 4. Current Vrefresh
>> Format is as follows:
>>
>> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
>> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
>> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
>> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 93 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 93 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 2ad4c48..47f1f65 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2819,6 +2819,98 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>> return 0;
>> }
>>
>> +static int i915_drrs_status(struct seq_file *m, void *unused)
>> +{
>> + struct drm_info_node *node = m->private;
>> + struct drm_device *dev = node->minor->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct i915_drrs *drrs = &dev_priv->drrs;
>> + struct intel_crtc *intel_crtc;
>> + struct intel_encoder *intel_encoder;
>> + int active_crtc_cnt = 0, vrefresh = 0;
>> +
>> + for_each_intel_crtc(dev, intel_crtc) {
>> + if (intel_crtc->active) {
>> + active_crtc_cnt++;
>> + seq_puts(m, "CRTC");
>> + seq_put_decimal_ull(m, ' ', active_crtc_cnt);
>> + seq_puts(m, ": ");
>> + for_each_encoder_on_crtc(dev, &intel_crtc->base,
>> + intel_encoder) {
>> + /* Encoder connected on this CRTC */
>> + switch (intel_encoder->type) {
>> + case INTEL_OUTPUT_EDP:
>> + seq_puts(m, "Output: eDP, ");
>> + break;
>> + case INTEL_OUTPUT_DSI:
>> + seq_puts(m, "Output: DSI, ");
>> + break;
>> + case INTEL_OUTPUT_HDMI:
>> + seq_puts(m, "Output: HDMI, ");
>> + break;
>> + case INTEL_OUTPUT_DISPLAYPORT:
>> + seq_puts(m, "Output: DP, ");
>> + break;
>> + default:
>> + seq_puts(m, "Output: Others (id");
>> + seq_put_decimal_ull(m, '=',
>> + intel_encoder->type);
>> + seq_puts(m, "), ");
>> + }
>> + }
>> +
>> + if (intel_crtc->config->has_drrs) {
>> + struct intel_panel *panel;
>> +
>> + panel = &drrs->dp->attached_connector->panel;
>> + /* DRRS Supported */
>> + seq_puts(m,
>> + "DRRS Supported: Yes (Seamless), ");
>> + if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
>> + seq_puts(m,
>> + "DRRS_State: DRRS_HIGH_RR, ");
>> + vrefresh = panel->fixed_mode->vrefresh;
>> + } else if (drrs->refresh_rate_type ==
>> + DRRS_LOW_RR) {
>> + seq_puts(m,
>> + "DRRS_State: DRRS_LOW_RR, ");
>> + vrefresh =
>> + panel->downclock_mode->vrefresh;
>> + } else {
>> + seq_puts(m, "DRRS_State: Unknown");
>> + seq_put_decimal_ull(m, '(',
>> + drrs->refresh_rate_type);
>> + seq_puts(m, "), ");
>> + }
>> + seq_puts(m, "Vrefresh:");
>> + seq_put_decimal_ull(m, ' ', vrefresh);
>> +
>> + } else {
>> + /* DRRS not supported. Print the VBT parameter*/
>> + seq_puts(m, "DRRS Supported : No, ");
>> + if (dev_priv->vbt.drrs_type ==
>> + STATIC_DRRS_SUPPORT) {
>> + seq_puts(m,
>> + "VBT DRRS_type: Static");
>> + } else if (dev_priv->vbt.drrs_type ==
>> + SEAMLESS_DRRS_SUPPORT) {
>> + seq_puts(m,
>> + "VBT DRRS_type: Seamless");
>> + } else if (dev_priv->vbt.drrs_type ==
>> + DRRS_NOT_SUPPORTED) {
>> + seq_puts(m, "VBT DRRS_type: None");
>> + }
>> + }
> This is an example of were strictly following checkpatch warnings and
> pedantically breaking lines results in rather hard to read code:
> The function is really long, and has about 6 indent levels. Imo it would
> greatly benefit from extracting some helper functions to do the
> inner-level printing. There's piles of examples in i915_debugfs where we
> loop over a bunch of objects and punt all the real output to a small
> helper function.
> -Daniel
Thanks Daniel. Submitting a patch in few mins. --Ram
>> + seq_puts(m, "\n");
>> + }
>> + }
>> +
>> + if (!active_crtc_cnt)
>> + seq_puts(m, "No active crtc found\n");
>> +
>> + return 0;
>> +}
>> +
>> struct pipe_crc_info {
>> const char *name;
>> struct drm_device *dev;
>> @@ -4433,6 +4525,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>> {"i915_dp_mst_info", i915_dp_mst_info, 0},
>> {"i915_wa_registers", i915_wa_registers, 0},
>> {"i915_ddb_info", i915_ddb_info, 0},
>> + {"i915_drrs_status", i915_drrs_status, 0},
>> };
>> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>>
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[-- Attachment #1.2: Type: text/html, Size: 6160 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-23 17:47 ` Ramalingam C
@ 2015-01-23 17:52 ` Ramalingam C
2015-01-24 0:13 ` Rodrigo Vivi
0 siblings, 1 reply; 64+ messages in thread
From: Ramalingam C @ 2015-01-23 17:52 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi, chris, daniel; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 85 +++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ad4c48..45beb32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2819,6 +2819,90 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
return 0;
}
+static void drrs_status_per_crtc(struct seq_file *m,
+ struct drm_device *dev, struct intel_crtc *intel_crtc)
+{
+ struct intel_encoder *intel_encoder;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_drrs *drrs = &dev_priv->drrs;
+ int vrefresh = 0;
+
+ for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
+ /* Encoder connected on this CRTC */
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ seq_puts(m, "Output: eDP, ");
+ break;
+ case INTEL_OUTPUT_DSI:
+ seq_puts(m, "Output: DSI, ");
+ break;
+ case INTEL_OUTPUT_HDMI:
+ seq_puts(m, "Output: HDMI, ");
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ seq_puts(m, "Output: DP, ");
+ break;
+ default:
+ seq_printf(m, "Output: Others (id=%d), ",
+ intel_encoder->type);
+ }
+ }
+
+ if (intel_crtc->config->has_drrs) {
+ struct intel_panel *panel;
+
+ panel = &drrs->dp->attached_connector->panel;
+ /* DRRS Supported */
+ seq_puts(m, "DRRS Supported: Yes (Seamless), ");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ seq_puts(m, "DRRS_State: DRRS_HIGH_RR, ");
+ vrefresh = panel->fixed_mode->vrefresh;
+ } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
+ seq_puts(m, "DRRS_State: DRRS_LOW_RR, ");
+ vrefresh = panel->downclock_mode->vrefresh;
+ } else {
+ seq_printf(m, "DRRS_State: Unknown(%d), ",
+ drrs->refresh_rate_type);
+ }
+ seq_printf(m, "Vrefresh: %d", vrefresh);
+
+ } else {
+ /* DRRS not supported. Print the VBT parameter*/
+ seq_puts(m, "DRRS Supported : No, ");
+ if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
+ seq_puts(m, "VBT DRRS_type: Static");
+ else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
+ seq_puts(m, "VBT DRRS_type: Seamless");
+ else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
+ seq_puts(m, "VBT DRRS_type: None");
+ else
+ seq_puts(m, "VBT DRRS_type: Unrecognized Value");
+ }
+ seq_puts(m, "\n");
+}
+
+static int i915_drrs_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct intel_crtc *intel_crtc;
+ int active_crtc_cnt = 0;
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ if (intel_crtc->active) {
+ active_crtc_cnt++;
+ seq_printf(m, "CRTC %d: ", active_crtc_cnt);
+
+ drrs_status_per_crtc(m, dev, intel_crtc);
+ }
+ }
+
+ if (!active_crtc_cnt)
+ seq_puts(m, "No active crtc found\n");
+
+ return 0;
+}
+
struct pipe_crc_info {
const char *name;
struct drm_device *dev;
@@ -4433,6 +4517,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
{"i915_ddb_info", i915_ddb_info, 0},
+ {"i915_drrs_status", i915_drrs_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
1.7.9.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-23 17:52 ` Ramalingam C
@ 2015-01-24 0:13 ` Rodrigo Vivi
2015-02-11 12:52 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-24 0:13 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
On Fri, Jan 23, 2015 at 9:52 AM, Ramalingam C <ramalingam.c@intel.com> wrote:
> From: Vandana Kannan <vandana.kannan@intel.com>
>
> Adding a debugfs entry to determine if DRRS is supported or not
>
> V2: [By Ram]: Following details about the active crtc will be filled
> in seq-file of the debugfs
> 1. Encoder output type
> 2. DRRS Support on this CRTC
> 3. DRRS current state
> 4. Current Vrefresh
> Format is as follows:
> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
> CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
> CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
>
> V3: [By Ram]: Readability is improved.
> Another error case is covered [Daniel]
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 85 +++++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2ad4c48..45beb32 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2819,6 +2819,90 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static void drrs_status_per_crtc(struct seq_file *m,
> + struct drm_device *dev, struct intel_crtc *intel_crtc)
> +{
> + struct intel_encoder *intel_encoder;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct i915_drrs *drrs = &dev_priv->drrs;
> + int vrefresh = 0;
> +
> + for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
> + /* Encoder connected on this CRTC */
> + switch (intel_encoder->type) {
> + case INTEL_OUTPUT_EDP:
> + seq_puts(m, "Output: eDP, ");
> + break;
> + case INTEL_OUTPUT_DSI:
> + seq_puts(m, "Output: DSI, ");
> + break;
> + case INTEL_OUTPUT_HDMI:
> + seq_puts(m, "Output: HDMI, ");
> + break;
> + case INTEL_OUTPUT_DISPLAYPORT:
> + seq_puts(m, "Output: DP, ");
> + break;
> + default:
> + seq_printf(m, "Output: Others (id=%d), ",
> + intel_encoder->type);
> + }
> + }
> +
> + if (intel_crtc->config->has_drrs) {
> + struct intel_panel *panel;
> +
> + panel = &drrs->dp->attached_connector->panel;
> + /* DRRS Supported */
> + seq_puts(m, "DRRS Supported: Yes (Seamless), ");
> + if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
> + seq_puts(m, "DRRS_State: DRRS_HIGH_RR, ");
> + vrefresh = panel->fixed_mode->vrefresh;
> + } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
> + seq_puts(m, "DRRS_State: DRRS_LOW_RR, ");
> + vrefresh = panel->downclock_mode->vrefresh;
> + } else {
> + seq_printf(m, "DRRS_State: Unknown(%d), ",
> + drrs->refresh_rate_type);
> + }
> + seq_printf(m, "Vrefresh: %d", vrefresh);
> +
> + } else {
> + /* DRRS not supported. Print the VBT parameter*/
> + seq_puts(m, "DRRS Supported : No, ");
> + if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
> + seq_puts(m, "VBT DRRS_type: Static");
> + else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
> + seq_puts(m, "VBT DRRS_type: Seamless");
> + else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
> + seq_puts(m, "VBT DRRS_type: None");
> + else
> + seq_puts(m, "VBT DRRS_type: Unrecognized Value");
> + }
> + seq_puts(m, "\n");
> +}
> +
> +static int i915_drrs_status(struct seq_file *m, void *unused)
> +{
> + struct drm_info_node *node = m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct intel_crtc *intel_crtc;
> + int active_crtc_cnt = 0;
> +
> + for_each_intel_crtc(dev, intel_crtc) {
> + if (intel_crtc->active) {
> + active_crtc_cnt++;
> + seq_printf(m, "CRTC %d: ", active_crtc_cnt);
> +
> + drrs_status_per_crtc(m, dev, intel_crtc);
> + }
> + }
> +
> + if (!active_crtc_cnt)
> + seq_puts(m, "No active crtc found\n");
> +
> + return 0;
> +}
> +
> struct pipe_crc_info {
> const char *name;
> struct drm_device *dev;
> @@ -4433,6 +4517,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
> {"i915_dp_mst_info", i915_dp_mst_info, 0},
> {"i915_wa_registers", i915_wa_registers, 0},
> {"i915_ddb_info", i915_ddb_info, 0},
> + {"i915_drrs_status", i915_drrs_status, 0},
> };
> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Debug still don't show current enabled/disabled drrs status.
it also could have frontbuffer bits...
Anyway this one looks ok and better than first version so feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH] drm/i915: Add debugfs entry for DRRS
2015-01-24 0:13 ` Rodrigo Vivi
@ 2015-02-11 12:52 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-02-11 12:52 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: paulo.r.zanoni
From: Vandana Kannan <vandana.kannan@intel.com>
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 99 +++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9af17fb..a2f702a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2855,6 +2855,104 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
return 0;
}
+static void drrs_status_per_crtc(struct seq_file *m,
+ struct drm_device *dev, struct intel_crtc *intel_crtc)
+{
+ struct intel_encoder *intel_encoder;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_drrs *drrs = &dev_priv->drrs;
+ int vrefresh = 0;
+
+ for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
+ /* Encoder connected on this CRTC */
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ seq_puts(m, "Output: eDP, ");
+ break;
+ case INTEL_OUTPUT_DSI:
+ seq_puts(m, "Output: DSI, ");
+ break;
+ case INTEL_OUTPUT_HDMI:
+ seq_puts(m, "Output: HDMI, ");
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ seq_puts(m, "Output: DP, ");
+ break;
+ default:
+ seq_printf(m, "Output: Others (id=%d), ",
+ intel_encoder->type);
+ }
+ }
+
+ if (intel_crtc->config->has_drrs) {
+ struct intel_panel *panel;
+
+ panel = &drrs->dp->attached_connector->panel;
+ /* DRRS Supported */
+ seq_puts(m, "DRRS Supported: Yes (Seamless), ");
+ seq_printf(m, "busy_frontbuffer_bits: 0x%X,\n\t",
+ drrs->busy_frontbuffer_bits);
+
+ if (drrs->busy_frontbuffer_bits) {
+ seq_puts(m, "Front buffer: busy, ");
+ seq_puts(m, "Idleness Timer: Suspended, ");
+ } else {
+ seq_puts(m, "Front buffer: Idle, ");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR)
+ seq_puts(m, "Idleness Timer: Ticking, ");
+ else
+ seq_puts(m, "Idleness Timer: Suspended, ");
+ }
+
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ seq_puts(m, "DRRS_State: DRRS_HIGH_RR, ");
+ vrefresh = panel->fixed_mode->vrefresh;
+ } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
+ seq_puts(m, "DRRS_State: DRRS_LOW_RR, ");
+ vrefresh = panel->downclock_mode->vrefresh;
+ } else {
+ seq_printf(m, "DRRS_State: Unknown(%d), ",
+ drrs->refresh_rate_type);
+ }
+ seq_printf(m, "Vrefresh: %d", vrefresh);
+
+ } else {
+ /* DRRS not supported. Print the VBT parameter*/
+ seq_puts(m, "DRRS Supported : No, ");
+ if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
+ seq_puts(m, "VBT DRRS_type: Static");
+ else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
+ seq_puts(m, "VBT DRRS_type: Seamless");
+ else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
+ seq_puts(m, "VBT DRRS_type: None");
+ else
+ seq_puts(m, "VBT DRRS_type: Unrecognized Value");
+ }
+ seq_puts(m, "\n");
+}
+
+static int i915_drrs_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct intel_crtc *intel_crtc;
+ int active_crtc_cnt = 0;
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ if (intel_crtc->active) {
+ active_crtc_cnt++;
+ seq_printf(m, "CRTC %d: ", active_crtc_cnt);
+
+ drrs_status_per_crtc(m, dev, intel_crtc);
+ }
+ }
+
+ if (!active_crtc_cnt)
+ seq_puts(m, "No active crtc found\n");
+
+ return 0;
+}
+
struct pipe_crc_info {
const char *name;
struct drm_device *dev;
@@ -4469,6 +4567,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
{"i915_ddb_info", i915_ddb_info, 0},
+ {"i915_drrs_status", i915_drrs_status, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
--
1.7.9.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 10/10] kms_drrs: Test DRRS entry and exit
2015-01-09 20:55 [PATCH v3 0/10] eDP DRRS based on frontbuffer tracking Vandana Kannan
` (8 preceding siblings ...)
2015-01-09 20:56 ` [PATCH 9/10] drm/i915: Add debugfs entry " Vandana Kannan
@ 2015-01-09 20:56 ` Vandana Kannan
2015-01-15 23:24 ` Rodrigo Vivi
9 siblings, 1 reply; 64+ messages in thread
From: Vandana Kannan @ 2015-01-09 20:56 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi
This test just display a frame on screen, waits for 1 second to enter DRRS
and displays another frame to exit DRRS.
TODO:- Notify the user about which refresh rate was used at different stages.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
tests/Makefile.sources | 1 +
tests/kms_drrs.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 226 insertions(+)
mode change 100644 => 100755 tests/Makefile.sources
create mode 100644 tests/kms_drrs.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
old mode 100644
new mode 100755
index 967dc8f..fbc0977
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -64,6 +64,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb \
kms_cursor_crc \
+ kms_drrs \
kms_fbc_crc \
kms_flip \
kms_flip_event_leak \
diff --git a/tests/kms_drrs.c b/tests/kms_drrs.c
new file mode 100644
index 0000000..5a360f3
--- /dev/null
+++ b/tests/kms_drrs.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "intel_chipset.h"
+#include "intel_batchbuffer.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION(
+"Performs write operations and then waits for DRRS to be enabled and then "
+"disturbs the contents of the screen once again to disable DRRS.");
+
+typedef struct {
+ int drm_fd;
+ uint32_t devid;
+ uint32_t handle[2];
+ igt_display_t display;
+ igt_output_t *output;
+ enum pipe pipe;
+ igt_plane_t *primary;
+ struct igt_fb fb[2];
+ uint32_t fb_id[2];
+} data_t;
+
+static bool drrs_enabled(data_t *data)
+{
+ FILE *status;
+ char str[64] = {};
+
+ status = igt_debugfs_fopen("i915_drrs_status", "r");
+ igt_assert(status);
+
+ fread(str, sizeof(str) - 1, 1, status);
+ fclose(status);
+ return strstr(str, "DRRS enabled") != NULL;
+}
+
+static bool prepare_crtc(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ igt_output_t *output = data->output;
+
+ /* select the pipe we want to use */
+ igt_output_set_pipe(output, data->pipe);
+ igt_display_commit(display);
+
+ if (!output->valid) {
+ igt_output_set_pipe(output, PIPE_ANY);
+ igt_display_commit(display);
+ return false;
+ }
+
+ return true;
+}
+
+static bool prepare_test(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ igt_output_t *output = data->output;
+ drmModeModeInfo *mode;
+
+ data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
+ mode = igt_output_get_mode(data->output);
+
+ data->fb_id[0] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ I915_TILING_X,
+ 0.0, 0.0, 0.0, &data->fb[0]);
+ igt_assert(data->fb_id[0]);
+ data->fb_id[1] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ I915_TILING_X,
+ 0.1, 0.1, 0.1,
+ &data->fb[1]);
+ igt_assert(data->fb_id[1]);
+
+ data->handle[0] = data->fb[0].gem_handle;
+ data->handle[1] = data->fb[1].gem_handle;
+
+ /* scanout = fb[1] */
+ igt_plane_set_fb(data->primary, &data->fb[1]);
+ igt_display_commit(display);
+ usleep(1000000);
+
+ if (!drrs_enabled(data)) {
+ igt_info("DRRS not enabled\n");
+
+ igt_plane_set_fb(data->primary, NULL);
+ igt_output_set_pipe(output, PIPE_ANY);
+ igt_display_commit(display);
+
+ igt_remove_fb(data->drm_fd, &data->fb[0]);
+ igt_remove_fb(data->drm_fd, &data->fb[1]);
+ return false;
+ }
+
+ igt_wait_for_vblank(data->drm_fd, data->pipe);
+
+ /* scanout = fb[0] */
+ igt_plane_set_fb(data->primary, &data->fb[0]);
+ igt_display_commit(display);
+ usleep(100000);
+
+ igt_wait_for_vblank(data->drm_fd, data->pipe);
+
+ return true;
+}
+
+static void finish_crtc(data_t *data)
+{
+ igt_plane_set_fb(data->primary, NULL);
+ igt_output_set_pipe(data->output, PIPE_ANY);
+ igt_display_commit(&data->display);
+
+ igt_remove_fb(data->drm_fd, &data->fb[0]);
+ igt_remove_fb(data->drm_fd, &data->fb[1]);
+}
+
+static void reset_display(data_t *data)
+{
+ igt_display_t *display = &data->display;
+
+ for_each_connected_output(display, data->output) {
+ if (data->output->valid) {
+ data->primary = igt_output_get_plane(data->output,
+ IGT_PLANE_PRIMARY);
+ igt_plane_set_fb(data->primary, NULL);
+ }
+ igt_output_set_pipe(data->output, PIPE_ANY);
+ }
+}
+
+static void run_test(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ int valid_tests = 0;
+
+ reset_display(data);
+
+ for_each_connected_output(display, data->output) {
+ for_each_pipe(display, data->pipe) {
+ if (!prepare_crtc(data))
+ continue;
+
+ igt_info("Beginning %s on pipe %s, connector %s\n",
+ igt_subtest_name(),
+ kmstest_pipe_name(data->pipe),
+ igt_output_name(data->output));
+
+ if (!prepare_test(data)) {
+ igt_info("%s on pipe %s, connector %s: SKIPPED\n",
+ igt_subtest_name(),
+ kmstest_pipe_name(data->pipe),
+ igt_output_name(data->output));
+ continue;
+ }
+
+ valid_tests++;
+
+ igt_info("%s on pipe %s, connector %s: PASSED\n",
+ igt_subtest_name(),
+ kmstest_pipe_name(data->pipe),
+ igt_output_name(data->output));
+
+ finish_crtc(data);
+ }
+ }
+
+ igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
+}
+
+igt_main
+{
+ data_t data = {};
+
+ igt_skip_on_simulation();
+
+ igt_fixture {
+ char buf[64];
+ FILE *status;
+
+ data.drm_fd = drm_open_any_master();
+
+ data.devid = intel_get_drm_devid(data.drm_fd);
+
+ status = igt_debugfs_fopen("i915_drrs_status", "r");
+ igt_require_f(status, "No i915_drrs_status found\n");
+ fread(buf, sizeof(buf), 1, status);
+ fclose(status);
+ buf[sizeof(buf) - 1] = '\0';
+ igt_require_f(!strstr(buf, "disabled"),
+ "DRRS not supported:check VBT/panel caps\n");
+
+ igt_display_init(&data.display, data.drm_fd);
+ }
+
+ run_test(&data);
+
+ igt_fixture {
+ igt_display_fini(&data.display);
+ }
+}
--
2.0.1
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 10/10] kms_drrs: Test DRRS entry and exit
2015-01-09 20:56 ` [PATCH 10/10] kms_drrs: Test DRRS entry and exit Vandana Kannan
@ 2015-01-15 23:24 ` Rodrigo Vivi
2015-01-20 9:11 ` Daniel Vetter
0 siblings, 1 reply; 64+ messages in thread
From: Rodrigo Vivi @ 2015-01-15 23:24 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
I didn't get how it shows different rates if the i915_drrs_status only
shows if panel supports or not.
Maybe the debugfs file could contain more info for each crtc connect,
crtc info, if panel connected there supports, if it is enabled and
also current freq.. then parse all here properly.
But one thing I don't know how to cover but it would be good is to
check for flickers...
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
> This test just display a frame on screen, waits for 1 second to enter DRRS
> and displays another frame to exit DRRS.
> TODO:- Notify the user about which refresh rate was used at different stages.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> tests/Makefile.sources | 1 +
> tests/kms_drrs.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 226 insertions(+)
> mode change 100644 => 100755 tests/Makefile.sources
> create mode 100644 tests/kms_drrs.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> old mode 100644
> new mode 100755
> index 967dc8f..fbc0977
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -64,6 +64,7 @@ TESTS_progs_M = \
> gem_write_read_ring_switch \
> kms_addfb \
> kms_cursor_crc \
> + kms_drrs \
> kms_fbc_crc \
> kms_flip \
> kms_flip_event_leak \
> diff --git a/tests/kms_drrs.c b/tests/kms_drrs.c
> new file mode 100644
> index 0000000..5a360f3
> --- /dev/null
> +++ b/tests/kms_drrs.c
> @@ -0,0 +1,225 @@
> +/*
> + * Copyright © 2013 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_kms.h"
> +#include "intel_chipset.h"
> +#include "intel_batchbuffer.h"
> +#include "ioctl_wrappers.h"
> +
> +IGT_TEST_DESCRIPTION(
> +"Performs write operations and then waits for DRRS to be enabled and then "
> +"disturbs the contents of the screen once again to disable DRRS.");
> +
> +typedef struct {
> + int drm_fd;
> + uint32_t devid;
> + uint32_t handle[2];
> + igt_display_t display;
> + igt_output_t *output;
> + enum pipe pipe;
> + igt_plane_t *primary;
> + struct igt_fb fb[2];
> + uint32_t fb_id[2];
> +} data_t;
> +
> +static bool drrs_enabled(data_t *data)
> +{
> + FILE *status;
> + char str[64] = {};
> +
> + status = igt_debugfs_fopen("i915_drrs_status", "r");
> + igt_assert(status);
> +
> + fread(str, sizeof(str) - 1, 1, status);
> + fclose(status);
> + return strstr(str, "DRRS enabled") != NULL;
> +}
> +
> +static bool prepare_crtc(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> + igt_output_t *output = data->output;
> +
> + /* select the pipe we want to use */
> + igt_output_set_pipe(output, data->pipe);
> + igt_display_commit(display);
> +
> + if (!output->valid) {
> + igt_output_set_pipe(output, PIPE_ANY);
> + igt_display_commit(display);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool prepare_test(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> + igt_output_t *output = data->output;
> + drmModeModeInfo *mode;
> +
> + data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
> + mode = igt_output_get_mode(data->output);
> +
> + data->fb_id[0] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + I915_TILING_X,
> + 0.0, 0.0, 0.0, &data->fb[0]);
> + igt_assert(data->fb_id[0]);
> + data->fb_id[1] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB8888,
> + I915_TILING_X,
> + 0.1, 0.1, 0.1,
> + &data->fb[1]);
> + igt_assert(data->fb_id[1]);
> +
> + data->handle[0] = data->fb[0].gem_handle;
> + data->handle[1] = data->fb[1].gem_handle;
> +
> + /* scanout = fb[1] */
> + igt_plane_set_fb(data->primary, &data->fb[1]);
> + igt_display_commit(display);
> + usleep(1000000);
> +
> + if (!drrs_enabled(data)) {
> + igt_info("DRRS not enabled\n");
> +
> + igt_plane_set_fb(data->primary, NULL);
> + igt_output_set_pipe(output, PIPE_ANY);
> + igt_display_commit(display);
> +
> + igt_remove_fb(data->drm_fd, &data->fb[0]);
> + igt_remove_fb(data->drm_fd, &data->fb[1]);
> + return false;
> + }
> +
> + igt_wait_for_vblank(data->drm_fd, data->pipe);
> +
> + /* scanout = fb[0] */
> + igt_plane_set_fb(data->primary, &data->fb[0]);
> + igt_display_commit(display);
> + usleep(100000);
> +
> + igt_wait_for_vblank(data->drm_fd, data->pipe);
> +
> + return true;
> +}
> +
> +static void finish_crtc(data_t *data)
> +{
> + igt_plane_set_fb(data->primary, NULL);
> + igt_output_set_pipe(data->output, PIPE_ANY);
> + igt_display_commit(&data->display);
> +
> + igt_remove_fb(data->drm_fd, &data->fb[0]);
> + igt_remove_fb(data->drm_fd, &data->fb[1]);
> +}
> +
> +static void reset_display(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> +
> + for_each_connected_output(display, data->output) {
> + if (data->output->valid) {
> + data->primary = igt_output_get_plane(data->output,
> + IGT_PLANE_PRIMARY);
> + igt_plane_set_fb(data->primary, NULL);
> + }
> + igt_output_set_pipe(data->output, PIPE_ANY);
> + }
> +}
> +
> +static void run_test(data_t *data)
> +{
> + igt_display_t *display = &data->display;
> + int valid_tests = 0;
> +
> + reset_display(data);
> +
> + for_each_connected_output(display, data->output) {
> + for_each_pipe(display, data->pipe) {
> + if (!prepare_crtc(data))
> + continue;
> +
> + igt_info("Beginning %s on pipe %s, connector %s\n",
> + igt_subtest_name(),
> + kmstest_pipe_name(data->pipe),
> + igt_output_name(data->output));
> +
> + if (!prepare_test(data)) {
> + igt_info("%s on pipe %s, connector %s: SKIPPED\n",
> + igt_subtest_name(),
> + kmstest_pipe_name(data->pipe),
> + igt_output_name(data->output));
> + continue;
> + }
> +
> + valid_tests++;
> +
> + igt_info("%s on pipe %s, connector %s: PASSED\n",
> + igt_subtest_name(),
> + kmstest_pipe_name(data->pipe),
> + igt_output_name(data->output));
> +
> + finish_crtc(data);
> + }
> + }
> +
> + igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
> +}
> +
> +igt_main
> +{
> + data_t data = {};
> +
> + igt_skip_on_simulation();
> +
> + igt_fixture {
> + char buf[64];
> + FILE *status;
> +
> + data.drm_fd = drm_open_any_master();
> +
> + data.devid = intel_get_drm_devid(data.drm_fd);
> +
> + status = igt_debugfs_fopen("i915_drrs_status", "r");
> + igt_require_f(status, "No i915_drrs_status found\n");
> + fread(buf, sizeof(buf), 1, status);
> + fclose(status);
> + buf[sizeof(buf) - 1] = '\0';
> + igt_require_f(!strstr(buf, "disabled"),
> + "DRRS not supported:check VBT/panel caps\n");
> +
> + igt_display_init(&data.display, data.drm_fd);
> + }
> +
> + run_test(&data);
> +
> + igt_fixture {
> + igt_display_fini(&data.display);
> + }
> +}
> --
> 2.0.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 10/10] kms_drrs: Test DRRS entry and exit
2015-01-15 23:24 ` Rodrigo Vivi
@ 2015-01-20 9:11 ` Daniel Vetter
2015-01-21 12:31 ` Ramalingam C
0 siblings, 1 reply; 64+ messages in thread
From: Daniel Vetter @ 2015-01-20 9:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Vivi, Rodrigo, Paulo Zanoni
On Thu, Jan 15, 2015 at 03:24:04PM -0800, Rodrigo Vivi wrote:
> I didn't get how it shows different rates if the i915_drrs_status only
> shows if panel supports or not.
>
> Maybe the debugfs file could contain more info for each crtc connect,
> crtc info, if panel connected there supports, if it is enabled and
> also current freq.. then parse all here properly.
Yeah, giving the testcase minimal functional testing by making sure the
kernel goes into low-RR mode when it should would be good. I think with
fbc/psr tests we're more than covered on the functional side for testing
that we don't miss updates.
> But one thing I don't know how to cover but it would be good is to
> check for flickers...
I don't think that's possible unfortunately :( We just have to wait for
random bug reports. Also this time around we do respect the various vbt
and panel settings, so hopefully this works better than the old lvds drrs
code we have merged already.
-Daniel
> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
> <vandana.kannan@intel.com> wrote:
> > This test just display a frame on screen, waits for 1 second to enter DRRS
> > and displays another frame to exit DRRS.
> > TODO:- Notify the user about which refresh rate was used at different stages.
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > ---
> > tests/Makefile.sources | 1 +
> > tests/kms_drrs.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 226 insertions(+)
> > mode change 100644 => 100755 tests/Makefile.sources
> > create mode 100644 tests/kms_drrs.c
> >
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > old mode 100644
> > new mode 100755
> > index 967dc8f..fbc0977
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -64,6 +64,7 @@ TESTS_progs_M = \
> > gem_write_read_ring_switch \
> > kms_addfb \
> > kms_cursor_crc \
> > + kms_drrs \
> > kms_fbc_crc \
> > kms_flip \
> > kms_flip_event_leak \
> > diff --git a/tests/kms_drrs.c b/tests/kms_drrs.c
> > new file mode 100644
> > index 0000000..5a360f3
> > --- /dev/null
> > +++ b/tests/kms_drrs.c
> > @@ -0,0 +1,225 @@
> > +/*
> > + * Copyright © 2013 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "drmtest.h"
> > +#include "igt_debugfs.h"
> > +#include "igt_kms.h"
> > +#include "intel_chipset.h"
> > +#include "intel_batchbuffer.h"
> > +#include "ioctl_wrappers.h"
> > +
> > +IGT_TEST_DESCRIPTION(
> > +"Performs write operations and then waits for DRRS to be enabled and then "
> > +"disturbs the contents of the screen once again to disable DRRS.");
> > +
> > +typedef struct {
> > + int drm_fd;
> > + uint32_t devid;
> > + uint32_t handle[2];
> > + igt_display_t display;
> > + igt_output_t *output;
> > + enum pipe pipe;
> > + igt_plane_t *primary;
> > + struct igt_fb fb[2];
> > + uint32_t fb_id[2];
> > +} data_t;
> > +
> > +static bool drrs_enabled(data_t *data)
> > +{
> > + FILE *status;
> > + char str[64] = {};
> > +
> > + status = igt_debugfs_fopen("i915_drrs_status", "r");
> > + igt_assert(status);
> > +
> > + fread(str, sizeof(str) - 1, 1, status);
> > + fclose(status);
> > + return strstr(str, "DRRS enabled") != NULL;
> > +}
> > +
> > +static bool prepare_crtc(data_t *data)
> > +{
> > + igt_display_t *display = &data->display;
> > + igt_output_t *output = data->output;
> > +
> > + /* select the pipe we want to use */
> > + igt_output_set_pipe(output, data->pipe);
> > + igt_display_commit(display);
> > +
> > + if (!output->valid) {
> > + igt_output_set_pipe(output, PIPE_ANY);
> > + igt_display_commit(display);
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool prepare_test(data_t *data)
> > +{
> > + igt_display_t *display = &data->display;
> > + igt_output_t *output = data->output;
> > + drmModeModeInfo *mode;
> > +
> > + data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
> > + mode = igt_output_get_mode(data->output);
> > +
> > + data->fb_id[0] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB8888,
> > + I915_TILING_X,
> > + 0.0, 0.0, 0.0, &data->fb[0]);
> > + igt_assert(data->fb_id[0]);
> > + data->fb_id[1] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> > + DRM_FORMAT_XRGB8888,
> > + I915_TILING_X,
> > + 0.1, 0.1, 0.1,
> > + &data->fb[1]);
> > + igt_assert(data->fb_id[1]);
> > +
> > + data->handle[0] = data->fb[0].gem_handle;
> > + data->handle[1] = data->fb[1].gem_handle;
> > +
> > + /* scanout = fb[1] */
> > + igt_plane_set_fb(data->primary, &data->fb[1]);
> > + igt_display_commit(display);
> > + usleep(1000000);
> > +
> > + if (!drrs_enabled(data)) {
> > + igt_info("DRRS not enabled\n");
> > +
> > + igt_plane_set_fb(data->primary, NULL);
> > + igt_output_set_pipe(output, PIPE_ANY);
> > + igt_display_commit(display);
> > +
> > + igt_remove_fb(data->drm_fd, &data->fb[0]);
> > + igt_remove_fb(data->drm_fd, &data->fb[1]);
> > + return false;
> > + }
> > +
> > + igt_wait_for_vblank(data->drm_fd, data->pipe);
> > +
> > + /* scanout = fb[0] */
> > + igt_plane_set_fb(data->primary, &data->fb[0]);
> > + igt_display_commit(display);
> > + usleep(100000);
> > +
> > + igt_wait_for_vblank(data->drm_fd, data->pipe);
> > +
> > + return true;
> > +}
> > +
> > +static void finish_crtc(data_t *data)
> > +{
> > + igt_plane_set_fb(data->primary, NULL);
> > + igt_output_set_pipe(data->output, PIPE_ANY);
> > + igt_display_commit(&data->display);
> > +
> > + igt_remove_fb(data->drm_fd, &data->fb[0]);
> > + igt_remove_fb(data->drm_fd, &data->fb[1]);
> > +}
> > +
> > +static void reset_display(data_t *data)
> > +{
> > + igt_display_t *display = &data->display;
> > +
> > + for_each_connected_output(display, data->output) {
> > + if (data->output->valid) {
> > + data->primary = igt_output_get_plane(data->output,
> > + IGT_PLANE_PRIMARY);
> > + igt_plane_set_fb(data->primary, NULL);
> > + }
> > + igt_output_set_pipe(data->output, PIPE_ANY);
> > + }
> > +}
> > +
> > +static void run_test(data_t *data)
> > +{
> > + igt_display_t *display = &data->display;
> > + int valid_tests = 0;
> > +
> > + reset_display(data);
> > +
> > + for_each_connected_output(display, data->output) {
> > + for_each_pipe(display, data->pipe) {
> > + if (!prepare_crtc(data))
> > + continue;
> > +
> > + igt_info("Beginning %s on pipe %s, connector %s\n",
> > + igt_subtest_name(),
> > + kmstest_pipe_name(data->pipe),
> > + igt_output_name(data->output));
> > +
> > + if (!prepare_test(data)) {
> > + igt_info("%s on pipe %s, connector %s: SKIPPED\n",
> > + igt_subtest_name(),
> > + kmstest_pipe_name(data->pipe),
> > + igt_output_name(data->output));
> > + continue;
> > + }
> > +
> > + valid_tests++;
> > +
> > + igt_info("%s on pipe %s, connector %s: PASSED\n",
> > + igt_subtest_name(),
> > + kmstest_pipe_name(data->pipe),
> > + igt_output_name(data->output));
> > +
> > + finish_crtc(data);
> > + }
> > + }
> > +
> > + igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
> > +}
> > +
> > +igt_main
> > +{
> > + data_t data = {};
> > +
> > + igt_skip_on_simulation();
> > +
> > + igt_fixture {
> > + char buf[64];
> > + FILE *status;
> > +
> > + data.drm_fd = drm_open_any_master();
> > +
> > + data.devid = intel_get_drm_devid(data.drm_fd);
> > +
> > + status = igt_debugfs_fopen("i915_drrs_status", "r");
> > + igt_require_f(status, "No i915_drrs_status found\n");
> > + fread(buf, sizeof(buf), 1, status);
> > + fclose(status);
> > + buf[sizeof(buf) - 1] = '\0';
> > + igt_require_f(!strstr(buf, "disabled"),
> > + "DRRS not supported:check VBT/panel caps\n");
> > +
> > + igt_display_init(&data.display, data.drm_fd);
> > + }
> > +
> > + run_test(&data);
> > +
> > + igt_fixture {
> > + igt_display_fini(&data.display);
> > + }
> > +}
> > --
> > 2.0.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 10/10] kms_drrs: Test DRRS entry and exit
2015-01-20 9:11 ` Daniel Vetter
@ 2015-01-21 12:31 ` Ramalingam C
0 siblings, 0 replies; 64+ messages in thread
From: Ramalingam C @ 2015-01-21 12:31 UTC (permalink / raw)
To: Daniel Vetter, Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni, Vivi, Rodrigo
[-- Attachment #1.1: Type: text/plain, Size: 11647 bytes --]
hi,
On Tuesday 20 January 2015 02:41 PM, Daniel Vetter wrote:
> On Thu, Jan 15, 2015 at 03:24:04PM -0800, Rodrigo Vivi wrote:
>> I didn't get how it shows different rates if the i915_drrs_status only
>> shows if panel supports or not.
>>
>> Maybe the debugfs file could contain more info for each crtc connect,
>> crtc info, if panel connected there supports, if it is enabled and
>> also current freq.. then parse all here properly.
> Yeah, giving the testcase minimal functional testing by making sure the
> kernel goes into low-RR mode when it should would be good. I think with
> fbc/psr tests we're more than covered on the functional side for testing
> that we don't miss updates.
working on providing more details from debugfs and parsing the same at igt.
I will submit a patch once it is completed.
>> But one thing I don't know how to cover but it would be good is to
>> check for flickers...
> I don't think that's possible unfortunately :( We just have to wait for
> random bug reports. Also this time around we do respect the various vbt
> and panel settings, so hopefully this works better than the old lvds drrs
> code we have merged already.
> -Daniel
>
>> On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
>> <vandana.kannan@intel.com> wrote:
>>> This test just display a frame on screen, waits for 1 second to enter DRRS
>>> and displays another frame to exit DRRS.
>>> TODO:- Notify the user about which refresh rate was used at different stages.
>>>
>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>>> ---
>>> tests/Makefile.sources | 1 +
>>> tests/kms_drrs.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 226 insertions(+)
>>> mode change 100644 => 100755 tests/Makefile.sources
>>> create mode 100644 tests/kms_drrs.c
>>>
>>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>>> old mode 100644
>>> new mode 100755
>>> index 967dc8f..fbc0977
>>> --- a/tests/Makefile.sources
>>> +++ b/tests/Makefile.sources
>>> @@ -64,6 +64,7 @@ TESTS_progs_M = \
>>> gem_write_read_ring_switch \
>>> kms_addfb \
>>> kms_cursor_crc \
>>> + kms_drrs \
>>> kms_fbc_crc \
>>> kms_flip \
>>> kms_flip_event_leak \
>>> diff --git a/tests/kms_drrs.c b/tests/kms_drrs.c
>>> new file mode 100644
>>> index 0000000..5a360f3
>>> --- /dev/null
>>> +++ b/tests/kms_drrs.c
>>> @@ -0,0 +1,225 @@
>>> +/*
>>> + * Copyright © 2013 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the "Software"),
>>> + * to deal in the Software without restriction, including without limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the next
>>> + * paragraph) shall be included in all copies or substantial portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#include "drmtest.h"
>>> +#include "igt_debugfs.h"
>>> +#include "igt_kms.h"
>>> +#include "intel_chipset.h"
>>> +#include "intel_batchbuffer.h"
>>> +#include "ioctl_wrappers.h"
>>> +
>>> +IGT_TEST_DESCRIPTION(
>>> +"Performs write operations and then waits for DRRS to be enabled and then "
>>> +"disturbs the contents of the screen once again to disable DRRS.");
>>> +
>>> +typedef struct {
>>> + int drm_fd;
>>> + uint32_t devid;
>>> + uint32_t handle[2];
>>> + igt_display_t display;
>>> + igt_output_t *output;
>>> + enum pipe pipe;
>>> + igt_plane_t *primary;
>>> + struct igt_fb fb[2];
>>> + uint32_t fb_id[2];
>>> +} data_t;
>>> +
>>> +static bool drrs_enabled(data_t *data)
>>> +{
>>> + FILE *status;
>>> + char str[64] = {};
>>> +
>>> + status = igt_debugfs_fopen("i915_drrs_status", "r");
>>> + igt_assert(status);
>>> +
>>> + fread(str, sizeof(str) - 1, 1, status);
>>> + fclose(status);
>>> + return strstr(str, "DRRS enabled") != NULL;
>>> +}
>>> +
>>> +static bool prepare_crtc(data_t *data)
>>> +{
>>> + igt_display_t *display = &data->display;
>>> + igt_output_t *output = data->output;
>>> +
>>> + /* select the pipe we want to use */
>>> + igt_output_set_pipe(output, data->pipe);
>>> + igt_display_commit(display);
>>> +
>>> + if (!output->valid) {
>>> + igt_output_set_pipe(output, PIPE_ANY);
>>> + igt_display_commit(display);
>>> + return false;
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static bool prepare_test(data_t *data)
>>> +{
>>> + igt_display_t *display = &data->display;
>>> + igt_output_t *output = data->output;
>>> + drmModeModeInfo *mode;
>>> +
>>> + data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
>>> + mode = igt_output_get_mode(data->output);
>>> +
>>> + data->fb_id[0] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
>>> + DRM_FORMAT_XRGB8888,
>>> + I915_TILING_X,
>>> + 0.0, 0.0, 0.0, &data->fb[0]);
>>> + igt_assert(data->fb_id[0]);
>>> + data->fb_id[1] = igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
>>> + DRM_FORMAT_XRGB8888,
>>> + I915_TILING_X,
>>> + 0.1, 0.1, 0.1,
>>> + &data->fb[1]);
>>> + igt_assert(data->fb_id[1]);
>>> +
>>> + data->handle[0] = data->fb[0].gem_handle;
>>> + data->handle[1] = data->fb[1].gem_handle;
>>> +
>>> + /* scanout = fb[1] */
>>> + igt_plane_set_fb(data->primary, &data->fb[1]);
>>> + igt_display_commit(display);
>>> + usleep(1000000);
>>> +
>>> + if (!drrs_enabled(data)) {
>>> + igt_info("DRRS not enabled\n");
>>> +
>>> + igt_plane_set_fb(data->primary, NULL);
>>> + igt_output_set_pipe(output, PIPE_ANY);
>>> + igt_display_commit(display);
>>> +
>>> + igt_remove_fb(data->drm_fd, &data->fb[0]);
>>> + igt_remove_fb(data->drm_fd, &data->fb[1]);
>>> + return false;
>>> + }
>>> +
>>> + igt_wait_for_vblank(data->drm_fd, data->pipe);
>>> +
>>> + /* scanout = fb[0] */
>>> + igt_plane_set_fb(data->primary, &data->fb[0]);
>>> + igt_display_commit(display);
>>> + usleep(100000);
>>> +
>>> + igt_wait_for_vblank(data->drm_fd, data->pipe);
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static void finish_crtc(data_t *data)
>>> +{
>>> + igt_plane_set_fb(data->primary, NULL);
>>> + igt_output_set_pipe(data->output, PIPE_ANY);
>>> + igt_display_commit(&data->display);
>>> +
>>> + igt_remove_fb(data->drm_fd, &data->fb[0]);
>>> + igt_remove_fb(data->drm_fd, &data->fb[1]);
>>> +}
>>> +
>>> +static void reset_display(data_t *data)
>>> +{
>>> + igt_display_t *display = &data->display;
>>> +
>>> + for_each_connected_output(display, data->output) {
>>> + if (data->output->valid) {
>>> + data->primary = igt_output_get_plane(data->output,
>>> + IGT_PLANE_PRIMARY);
>>> + igt_plane_set_fb(data->primary, NULL);
>>> + }
>>> + igt_output_set_pipe(data->output, PIPE_ANY);
>>> + }
>>> +}
>>> +
>>> +static void run_test(data_t *data)
>>> +{
>>> + igt_display_t *display = &data->display;
>>> + int valid_tests = 0;
>>> +
>>> + reset_display(data);
>>> +
>>> + for_each_connected_output(display, data->output) {
>>> + for_each_pipe(display, data->pipe) {
>>> + if (!prepare_crtc(data))
>>> + continue;
>>> +
>>> + igt_info("Beginning %s on pipe %s, connector %s\n",
>>> + igt_subtest_name(),
>>> + kmstest_pipe_name(data->pipe),
>>> + igt_output_name(data->output));
>>> +
>>> + if (!prepare_test(data)) {
>>> + igt_info("%s on pipe %s, connector %s: SKIPPED\n",
>>> + igt_subtest_name(),
>>> + kmstest_pipe_name(data->pipe),
>>> + igt_output_name(data->output));
>>> + continue;
>>> + }
>>> +
>>> + valid_tests++;
>>> +
>>> + igt_info("%s on pipe %s, connector %s: PASSED\n",
>>> + igt_subtest_name(),
>>> + kmstest_pipe_name(data->pipe),
>>> + igt_output_name(data->output));
>>> +
>>> + finish_crtc(data);
>>> + }
>>> + }
>>> +
>>> + igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
>>> +}
>>> +
>>> +igt_main
>>> +{
>>> + data_t data = {};
>>> +
>>> + igt_skip_on_simulation();
>>> +
>>> + igt_fixture {
>>> + char buf[64];
>>> + FILE *status;
>>> +
>>> + data.drm_fd = drm_open_any_master();
>>> +
>>> + data.devid = intel_get_drm_devid(data.drm_fd);
>>> +
>>> + status = igt_debugfs_fopen("i915_drrs_status", "r");
>>> + igt_require_f(status, "No i915_drrs_status found\n");
>>> + fread(buf, sizeof(buf), 1, status);
>>> + fclose(status);
>>> + buf[sizeof(buf) - 1] = '\0';
>>> + igt_require_f(!strstr(buf, "disabled"),
>>> + "DRRS not supported:check VBT/panel caps\n");
>>> +
>>> + igt_display_init(&data.display, data.drm_fd);
>>> + }
>>> +
>>> + run_test(&data);
>>> +
>>> + igt_fixture {
>>> + igt_display_fini(&data.display);
>>> + }
>>> +}
>>> --
>>> 2.0.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--Ram
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