[RFC 0/6] Use framebuffer modifiers for tiled display

[RFC 0/6] Use framebuffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Instead of using driver private set tiling ioctl, use the proposed addfb2 ioctl
extension to tell the driver about display buffer special formatting.

Lightly tested only with a hacked up igt/testdisplay. Sending out early so
people can comment on the overall approach over the weekend.

Rob Clark (1):
  RFC: drm: add support for tiled/compressed/etc modifier in addfb2

Tvrtko Ursulin (5):
  drm/i915: Add tiled framebuffer modifiers
  drm/i915: Set up fb modifier on initial takeover
  drm/i915: Use framebuffer tiling mode for display purposes
  drm/i915: Allow fb modifier to set framebuffer tiling
  drm/i915: Announce support for framebuffer modifiers

 drivers/gpu/drm/drm_crtc.c           | 14 +++++-
 drivers/gpu/drm/drm_crtc_helper.c    |  1 +
 drivers/gpu/drm/drm_ioctl.c          |  3 ++
 drivers/gpu/drm/i915/intel_display.c | 91 +++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +
 drivers/gpu/drm/i915/intel_pm.c      |  7 ++-
 drivers/gpu/drm/i915/intel_sprite.c  | 26 ++++++-----
 include/drm/drm_crtc.h               |  4 ++
 include/uapi/drm/drm.h               |  1 +
 include/uapi/drm/drm_fourcc.h        | 32 +++++++++++++
 include/uapi/drm/drm_mode.h          |  9 ++++
 include/uapi/drm/i915_drm.h          | 13 ++++++
 12 files changed, 160 insertions(+), 43 deletions(-)

-- 
2.2.2

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[RFC 1/6] RFC: drm: add support for tiled/compressed/etc modifier in addfb2

[Tvrtko Ursulin]

From: Rob Clark <robdclark@gmail.com>

In DRM/KMS we are lacking a good way to deal with tiled/compressed
formats.  Especially in the case of dmabuf/prime buffer sharing, where
we cannot always rely on under-the-hood flags passed to driver specific
gem-create ioctl to pass around these extra flags.

The proposal is to add a per-plane format modifier.  This allows to, if
necessary, use different tiling patters for sub-sampled planes, etc.
The format modifiers are added at the end of the ioctl struct, so for
legacy userspace it will be zero padded.

v1: original
v1.5: increase modifier to 64b

v2: Incorporate review comments from the big thread, plus a few more.

- Add a getcap so that userspace doesn't have to jump through hoops.
- Allow modifiers only when a flag is set. That way drivers know when
  they're dealing with old userspace and need to fish out e.g. tiling
  from other information.
- After rolling out checks for ->modifier to all drivers I've decided
  that this is way too fragile and needs an explicit opt-in flag. So
  do that instead.
- Add a define (just for documentation really) for the "NONE"
  modifier. Imo we don't need to add mask #defines since drivers
  really should only do exact matches against values defined with
  fourcc_mod_code.
- Drop the Samsung tiling modifier on Rob's request since he's not yet
  sure whether that one is accurate.

v3:
- Also add a new ->modifier[] array to struct drm_framebuffer and fill
  it in drm_helper_mode_fill_fb_struct. Requested by Tvrtko Uruslin.
- Remove TODO in comment and add code comment that modifiers should be
  properly documented, requested by Rob.

v4: Balance parens, spotted by Tvrtko.

Cc: Rob Clark <robdclark@gmail.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Rob Clark <robdclark@gmail.com> (v1.5)
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/drm_crtc.c        | 14 +++++++++++++-
 drivers/gpu/drm/drm_crtc_helper.c |  1 +
 drivers/gpu/drm/drm_ioctl.c       |  3 +++
 include/drm/drm_crtc.h            |  4 ++++
 include/uapi/drm/drm.h            |  1 +
 include/uapi/drm/drm_fourcc.h     | 32 ++++++++++++++++++++++++++++++++
 include/uapi/drm/drm_mode.h       |  9 +++++++++
 7 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6b00173..e6e2de3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3261,6 +3261,12 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
 			DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i);
 			return -EINVAL;
 		}
+
+		if (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) {
+			DRM_DEBUG_KMS("bad fb modifier %llu for plane %d\n",
+				      r->modifier[i], i);
+			return -EINVAL;
+		}
 	}
 
 	return 0;
@@ -3274,7 +3280,7 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 	struct drm_framebuffer *fb;
 	int ret;
 
-	if (r->flags & ~DRM_MODE_FB_INTERLACED) {
+	if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
 		DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
 		return ERR_PTR(-EINVAL);
 	}
@@ -3290,6 +3296,12 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 		return ERR_PTR(-EINVAL);
 	}
 
+	if (r->flags & DRM_MODE_FB_MODIFIERS &&
+	    !dev->mode_config.allow_fb_modifiers) {
+		DRM_DEBUG_KMS("driver does not support fb modifiers\n");
+		return ERR_PTR(-EINVAL);
+	}
+
 	ret = framebuffer_check(r);
 	if (ret)
 		return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index b1979e7..3053aab 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -837,6 +837,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
 	for (i = 0; i < 4; i++) {
 		fb->pitches[i] = mode_cmd->pitches[i];
 		fb->offsets[i] = mode_cmd->offsets[i];
+		fb->modifier[i] = mode_cmd->modifier[i];
 	}
 	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
 				    &fb->bits_per_pixel);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 3785d66..a6d773a 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -321,6 +321,9 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
 		else
 			req->value = 64;
 		break;
+	case DRM_CAP_ADDFB2_MODIFIERS:
+		req->value = dev->mode_config.allow_fb_modifiers;
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 920e21a..b1465d6 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -202,6 +202,7 @@ struct drm_framebuffer {
 	const struct drm_framebuffer_funcs *funcs;
 	unsigned int pitches[4];
 	unsigned int offsets[4];
+	uint64_t modifier[4];
 	unsigned int width;
 	unsigned int height;
 	/* depth can be 15 or 16 */
@@ -1155,6 +1156,9 @@ struct drm_mode_config {
 	/* whether async page flip is supported or not */
 	bool async_page_flip;
 
+	/* whether the driver supports fb modifiers */
+	bool allow_fb_modifiers;
+
 	/* cursor size */
 	uint32_t cursor_width, cursor_height;
 };
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 01b2d6d..ff6ef62 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -630,6 +630,7 @@ struct drm_gem_open {
  */
 #define DRM_CAP_CURSOR_WIDTH		0x8
 #define DRM_CAP_CURSOR_HEIGHT		0x9
+#define DRM_CAP_ADDFB2_MODIFIERS	0x10
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 646ae5f..6221096 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -132,4 +132,36 @@
 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
 
+
+/*
+ * Format Modifiers:
+ *
+ * Format modifiers describe, typically, a re-ordering or modification
+ * of the data in a plane of an FB.  This can be used to express tiled/
+ * swizzled formats, or compression, or a combination of the two.
+ *
+ * The upper 8 bits of the format modifier are a vendor-id as assigned
+ * below.  The lower 56 bits are assigned as vendor sees fit.
+ */
+
+/* Vendor Ids: */
+#define DRM_FORMAT_MOD_NONE           0
+#define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
+#define DRM_FORMAT_MOD_VENDOR_AMD     0x02
+#define DRM_FORMAT_MOD_VENDOR_NV      0x03
+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
+#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
+/* add more to the end as needed */
+
+#define fourcc_mod_code(vendor, val) \
+	((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffL))
+
+/*
+ * Format Modifier tokens:
+ *
+ * When adding a new token please document the layout with a code comment,
+ * similar to the fourcc codes above. drm_fourcc.h is considered the
+ * authoritative source for all of these.
+ */
+
 #endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index ca788e0..dbeba94 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -336,6 +336,7 @@ struct drm_mode_fb_cmd {
 };
 
 #define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
+#define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer[] */
 
 struct drm_mode_fb_cmd2 {
 	__u32 fb_id;
@@ -356,10 +357,18 @@ struct drm_mode_fb_cmd2 {
 	 * So it would consist of Y as offsets[0] and UV as
 	 * offsets[1].  Note that offsets[0] will generally
 	 * be 0 (but this is not required).
+	 *
+	 * To accommodate tiled, compressed, etc formats, a per-plane
+	 * modifier can be specified.  The default value of zero
+	 * indicates "native" format as specified by the fourcc.
+	 * Vendor specific modifier token.  This allows, for example,
+	 * different tiling/swizzling pattern on different planes.
+	 * See discussion above of DRM_FORMAT_MOD_xxx.
 	 */
 	__u32 handles[4];
 	__u32 pitches[4]; /* pitch for each plane */
 	__u32 offsets[4]; /* offset of each plane */
+	__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
 };
 
 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
-- 
2.2.2

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[RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

To be used from the new addfb2 extension.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/uapi/drm/i915_drm.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6eed16b..a7327fd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -28,6 +28,7 @@
 #define _UAPI_I915_DRM_H_
 
 #include <drm/drm.h>
+#include <uapi/drm/drm_fourcc.h>
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
 	__u64 value;
 };
 
+/** @{
+ * Intel framebuffer modifiers
+ *
+ * Tiling modes supported by the display hardware
+ * to be passed in via the DRM addfb2 ioctl.
+ */
+/** None */
+#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
+/** X tiling */
+#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
+/** @} */
+
 #endif /* _UAPI_I915_DRM_H_ */
-- 
2.2.2

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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> To be used from the new addfb2 extension.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6eed16b..a7327fd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -28,6 +28,7 @@
>  #define _UAPI_I915_DRM_H_
>  
>  #include <drm/drm.h>
> +#include <uapi/drm/drm_fourcc.h>
>  
>  /* Please note that modifications to all structs defined here are
>   * subject to backwards-compatibility constraints.
> @@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>  	__u64 value;
>  };
>  
> +/** @{
> + * Intel framebuffer modifiers
> + *
> + * Tiling modes supported by the display hardware
> + * to be passed in via the DRM addfb2 ioctl.
> + */
> +/** None */
> +#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
> +/** X tiling */
> +#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)

One thing I wonder here is whether we should have a modifier for each
physical layout (tiling modes do change slightly between hw) or whether we
should just continue to assume that this is Intel-specific and add a
disclaimer that the precise layout depends upon the actual intel box
you're running on?

Leaning towards your approach, worst case we get to write some code to
de-alias layout modifiers with established cross-vendor layouts (if they
ever happen). Just want to make sure that we've thought about this. Adding
Rob&dri-devel for this.
-Daniel

> +/** @} */
> +
>  #endif /* _UAPI_I915_DRM_H_ */
> -- 
> 2.2.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Mon, Feb 02, 2015 at 10:41:24AM +0100, Daniel Vetter wrote:
> On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > To be used from the new addfb2 extension.
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  include/uapi/drm/i915_drm.h | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 6eed16b..a7327fd 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -28,6 +28,7 @@
> >  #define _UAPI_I915_DRM_H_
> >  
> >  #include <drm/drm.h>
> > +#include <uapi/drm/drm_fourcc.h>
> >  
> >  /* Please note that modifications to all structs defined here are
> >   * subject to backwards-compatibility constraints.
> > @@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
> >  	__u64 value;
> >  };
> >  
> > +/** @{
> > + * Intel framebuffer modifiers
> > + *
> > + * Tiling modes supported by the display hardware
> > + * to be passed in via the DRM addfb2 ioctl.
> > + */
> > +/** None */
> > +#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
> > +/** X tiling */
> > +#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
> 
> One thing I wonder here is whether we should have a modifier for each
> physical layout (tiling modes do change slightly between hw) or whether we
> should just continue to assume that this is Intel-specific and add a
> disclaimer that the precise layout depends upon the actual intel box
> you're running on?
> 
> Leaning towards your approach, worst case we get to write some code to
> de-alias layout modifiers with established cross-vendor layouts (if they
> ever happen). Just want to make sure that we've thought about this. Adding
> Rob&dri-devel for this.

Something else to ponder: We also need layout modifiers for non-fb formats
in userspace so that clients and compositors can communicate about render
formats. Given that I think it'll make sense to enumerate all the other
tiling formats we have, too (i.e. Y-tiled and W-tiled).
-Daniel
-- 
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Tvrtko Ursulin]

On 02/02/2015 09:58 AM, Daniel Vetter wrote:
> On Mon, Feb 02, 2015 at 10:41:24AM +0100, Daniel Vetter wrote:
>> On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> To be used from the new addfb2 extension.
>>>
>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>>   include/uapi/drm/i915_drm.h | 13 +++++++++++++
>>>   1 file changed, 13 insertions(+)
>>>
>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>>> index 6eed16b..a7327fd 100644
>>> --- a/include/uapi/drm/i915_drm.h
>>> +++ b/include/uapi/drm/i915_drm.h
>>> @@ -28,6 +28,7 @@
>>>   #define _UAPI_I915_DRM_H_
>>>
>>>   #include <drm/drm.h>
>>> +#include <uapi/drm/drm_fourcc.h>
>>>
>>>   /* Please note that modifications to all structs defined here are
>>>    * subject to backwards-compatibility constraints.
>>> @@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>>>   	__u64 value;
>>>   };
>>>
>>> +/** @{
>>> + * Intel framebuffer modifiers
>>> + *
>>> + * Tiling modes supported by the display hardware
>>> + * to be passed in via the DRM addfb2 ioctl.
>>> + */
>>> +/** None */
>>> +#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
>>> +/** X tiling */
>>> +#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
>>
>> One thing I wonder here is whether we should have a modifier for each
>> physical layout (tiling modes do change slightly between hw) or whether we
>> should just continue to assume that this is Intel-specific and add a
>> disclaimer that the precise layout depends upon the actual intel box
>> you're running on?
>>
>> Leaning towards your approach, worst case we get to write some code to
>> de-alias layout modifiers with established cross-vendor layouts (if they
>> ever happen). Just want to make sure that we've thought about this. Adding
>> Rob&dri-devel for this.
>
> Something else to ponder: We also need layout modifiers for non-fb formats
> in userspace so that clients and compositors can communicate about render
> formats. Given that I think it'll make sense to enumerate all the other
> tiling formats we have, too (i.e. Y-tiled and W-tiled).

If we need fb modifiers for non-fb formats, although that sounds a bit 
funky to me, we can always add them in separate patches, no?

Regards,

Tvrtko
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Re: [Intel-gfx] [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Mon, Feb 02, 2015 at 10:23:57AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 09:58 AM, Daniel Vetter wrote:
> >On Mon, Feb 02, 2015 at 10:41:24AM +0100, Daniel Vetter wrote:
> >>On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>>To be used from the new addfb2 extension.
> >>>
> >>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>---
> >>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
> >>>  1 file changed, 13 insertions(+)
> >>>
> >>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> >>>index 6eed16b..a7327fd 100644
> >>>--- a/include/uapi/drm/i915_drm.h
> >>>+++ b/include/uapi/drm/i915_drm.h
> >>>@@ -28,6 +28,7 @@
> >>>  #define _UAPI_I915_DRM_H_
> >>>
> >>>  #include <drm/drm.h>
> >>>+#include <uapi/drm/drm_fourcc.h>
> >>>
> >>>  /* Please note that modifications to all structs defined here are
> >>>   * subject to backwards-compatibility constraints.
> >>>@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
> >>>  	__u64 value;
> >>>  };
> >>>
> >>>+/** @{
> >>>+ * Intel framebuffer modifiers
> >>>+ *
> >>>+ * Tiling modes supported by the display hardware
> >>>+ * to be passed in via the DRM addfb2 ioctl.
> >>>+ */
> >>>+/** None */
> >>>+#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
> >>>+/** X tiling */
> >>>+#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
> >>
> >>One thing I wonder here is whether we should have a modifier for each
> >>physical layout (tiling modes do change slightly between hw) or whether we
> >>should just continue to assume that this is Intel-specific and add a
> >>disclaimer that the precise layout depends upon the actual intel box
> >>you're running on?
> >>
> >>Leaning towards your approach, worst case we get to write some code to
> >>de-alias layout modifiers with established cross-vendor layouts (if they
> >>ever happen). Just want to make sure that we've thought about this. Adding
> >>Rob&dri-devel for this.
> >
> >Something else to ponder: We also need layout modifiers for non-fb formats
> >in userspace so that clients and compositors can communicate about render
> >formats. Given that I think it'll make sense to enumerate all the other
> >tiling formats we have, too (i.e. Y-tiled and W-tiled).
> 
> If we need fb modifiers for non-fb formats, although that sounds a bit funky
> to me, we can always add them in separate patches, no?

Yes and no - I think the aliasing with the I915_TILING_FOO defines would
be nice, and if you reserve another number for the fancy new tiling you're
working on and so block Y-tiled that would be unfortunate ...

Otoh meh, we need to remap anyway sooner or later. Like I've said, just
something to consider.
-Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Mon, Feb 02, 2015 at 10:23:57AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 09:58 AM, Daniel Vetter wrote:
> >On Mon, Feb 02, 2015 at 10:41:24AM +0100, Daniel Vetter wrote:
> >>On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>>To be used from the new addfb2 extension.
> >>>
> >>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>---
> >>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
> >>>  1 file changed, 13 insertions(+)
> >>>
> >>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> >>>index 6eed16b..a7327fd 100644
> >>>--- a/include/uapi/drm/i915_drm.h
> >>>+++ b/include/uapi/drm/i915_drm.h
> >>>@@ -28,6 +28,7 @@
> >>>  #define _UAPI_I915_DRM_H_
> >>>
> >>>  #include <drm/drm.h>
> >>>+#include <uapi/drm/drm_fourcc.h>
> >>>
> >>>  /* Please note that modifications to all structs defined here are
> >>>   * subject to backwards-compatibility constraints.
> >>>@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
> >>>  	__u64 value;
> >>>  };
> >>>
> >>>+/** @{
> >>>+ * Intel framebuffer modifiers
> >>>+ *
> >>>+ * Tiling modes supported by the display hardware
> >>>+ * to be passed in via the DRM addfb2 ioctl.
> >>>+ */
> >>>+/** None */
> >>>+#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
> >>>+/** X tiling */
> >>>+#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
> >>
> >>One thing I wonder here is whether we should have a modifier for each
> >>physical layout (tiling modes do change slightly between hw) or whether we
> >>should just continue to assume that this is Intel-specific and add a
> >>disclaimer that the precise layout depends upon the actual intel box
> >>you're running on?
> >>
> >>Leaning towards your approach, worst case we get to write some code to
> >>de-alias layout modifiers with established cross-vendor layouts (if they
> >>ever happen). Just want to make sure that we've thought about this. Adding
> >>Rob&dri-devel for this.
> >
> >Something else to ponder: We also need layout modifiers for non-fb formats
> >in userspace so that clients and compositors can communicate about render
> >formats. Given that I think it'll make sense to enumerate all the other
> >tiling formats we have, too (i.e. Y-tiled and W-tiled).
> 
> If we need fb modifiers for non-fb formats, although that sounds a bit funky
> to me, we can always add them in separate patches, no?

Oh and the explanation of why this makes sense: Userspace needs to agree
on some modifier numbers assignment too for its purposes of sharing
buffers between clients and compositor. And there's a lot of overlap with
buffers that can actually be scanned out (for the obvious reason called
fullscreen apps), so it makes sense to reuse those numbers instead of
everyone creating their own spec.

But then we need to make sure that non-fb modifiers of interest as used in
userspace aren't eventually used by the kernel for something else. Hence
they need to go into the kernel headers, just to reserve the numbers.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Rob Clark]

On Mon, Feb 2, 2015 at 10:58 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Feb 02, 2015 at 10:23:57AM +0000, Tvrtko Ursulin wrote:
>>
>> On 02/02/2015 09:58 AM, Daniel Vetter wrote:
>> >On Mon, Feb 02, 2015 at 10:41:24AM +0100, Daniel Vetter wrote:
>> >>On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
>> >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>>
>> >>>To be used from the new addfb2 extension.
>> >>>
>> >>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>>---
>> >>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
>> >>>  1 file changed, 13 insertions(+)
>> >>>
>> >>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> >>>index 6eed16b..a7327fd 100644
>> >>>--- a/include/uapi/drm/i915_drm.h
>> >>>+++ b/include/uapi/drm/i915_drm.h
>> >>>@@ -28,6 +28,7 @@
>> >>>  #define _UAPI_I915_DRM_H_
>> >>>
>> >>>  #include <drm/drm.h>
>> >>>+#include <uapi/drm/drm_fourcc.h>
>> >>>
>> >>>  /* Please note that modifications to all structs defined here are
>> >>>   * subject to backwards-compatibility constraints.
>> >>>@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>> >>>   __u64 value;
>> >>>  };
>> >>>
>> >>>+/** @{
>> >>>+ * Intel framebuffer modifiers
>> >>>+ *
>> >>>+ * Tiling modes supported by the display hardware
>> >>>+ * to be passed in via the DRM addfb2 ioctl.
>> >>>+ */
>> >>>+/** None */
>> >>>+#define I915_FORMAT_MOD_NONE      fourcc_mod_code(INTEL, 0x00000000000000L)
>> >>>+/** X tiling */
>> >>>+#define I915_FORMAT_MOD_X_TILED   fourcc_mod_code(INTEL, 0x00000000000001L)
>> >>
>> >>One thing I wonder here is whether we should have a modifier for each
>> >>physical layout (tiling modes do change slightly between hw) or whether we
>> >>should just continue to assume that this is Intel-specific and add a
>> >>disclaimer that the precise layout depends upon the actual intel box
>> >>you're running on?
>> >>
>> >>Leaning towards your approach, worst case we get to write some code to
>> >>de-alias layout modifiers with established cross-vendor layouts (if they
>> >>ever happen). Just want to make sure that we've thought about this. Adding
>> >>Rob&dri-devel for this.
>> >
>> >Something else to ponder: We also need layout modifiers for non-fb formats
>> >in userspace so that clients and compositors can communicate about render
>> >formats. Given that I think it'll make sense to enumerate all the other
>> >tiling formats we have, too (i.e. Y-tiled and W-tiled).
>>
>> If we need fb modifiers for non-fb formats, although that sounds a bit funky
>> to me, we can always add them in separate patches, no?
>
> Oh and the explanation of why this makes sense: Userspace needs to agree
> on some modifier numbers assignment too for its purposes of sharing
> buffers between clients and compositor. And there's a lot of overlap with
> buffers that can actually be scanned out (for the obvious reason called
> fullscreen apps), so it makes sense to reuse those numbers instead of
> everyone creating their own spec.
>
> But then we need to make sure that non-fb modifiers of interest as used in
> userspace aren't eventually used by the kernel for something else. Hence
> they need to go into the kernel headers, just to reserve the numbers.

right..  the next logical step is to extend the egl dmabuf extension
to take modifiers in the same way as addfb2 does.  So it makes sense
to reserve/enumerate any sharable modifier, even if it is not ever
used for scanout.  As w/ fourcc's, it will be nice to keep the egl
extension to keep the same formats and modifiers.

BR,
-R

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Rob Clark]

On Mon, Feb 2, 2015 at 4:41 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> To be used from the new addfb2 extension.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 6eed16b..a7327fd 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -28,6 +28,7 @@
>>  #define _UAPI_I915_DRM_H_
>>
>>  #include <drm/drm.h>
>> +#include <uapi/drm/drm_fourcc.h>
>>
>>  /* Please note that modifications to all structs defined here are
>>   * subject to backwards-compatibility constraints.
>> @@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>>       __u64 value;
>>  };
>>
>> +/** @{
>> + * Intel framebuffer modifiers
>> + *
>> + * Tiling modes supported by the display hardware
>> + * to be passed in via the DRM addfb2 ioctl.
>> + */
>> +/** None */
>> +#define I915_FORMAT_MOD_NONE fourcc_mod_code(INTEL, 0x00000000000000L)
>> +/** X tiling */
>> +#define I915_FORMAT_MOD_X_TILED      fourcc_mod_code(INTEL, 0x00000000000001L)
>
> One thing I wonder here is whether we should have a modifier for each
> physical layout (tiling modes do change slightly between hw) or whether we
> should just continue to assume that this is Intel-specific and add a
> disclaimer that the precise layout depends upon the actual intel box
> you're running on?

I'd kind of lean towards different modifiers per physical layout..
that seems more useful for cases where nvidia/amd support some of the
formats for buffer sharing..

BR,
-R

> Leaning towards your approach, worst case we get to write some code to
> de-alias layout modifiers with established cross-vendor layouts (if they
> ever happen). Just want to make sure that we've thought about this. Adding
> Rob&dri-devel for this.
> -Daniel
>
>> +/** @} */
>> +
>>  #endif /* _UAPI_I915_DRM_H_ */
>> --
>> 2.2.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Tvrtko Ursulin]

On 02/02/2015 04:32 PM, Rob Clark wrote:
> On Mon, Feb 2, 2015 at 4:41 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> To be used from the new addfb2 extension.
>>>
>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>>   include/uapi/drm/i915_drm.h | 13 +++++++++++++
>>>   1 file changed, 13 insertions(+)
>>>
>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>>> index 6eed16b..a7327fd 100644
>>> --- a/include/uapi/drm/i915_drm.h
>>> +++ b/include/uapi/drm/i915_drm.h
>>> @@ -28,6 +28,7 @@
>>>   #define _UAPI_I915_DRM_H_
>>>
>>>   #include <drm/drm.h>
>>> +#include <uapi/drm/drm_fourcc.h>
>>>
>>>   /* Please note that modifications to all structs defined here are
>>>    * subject to backwards-compatibility constraints.
>>> @@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>>>        __u64 value;
>>>   };
>>>
>>> +/** @{
>>> + * Intel framebuffer modifiers
>>> + *
>>> + * Tiling modes supported by the display hardware
>>> + * to be passed in via the DRM addfb2 ioctl.
>>> + */
>>> +/** None */
>>> +#define I915_FORMAT_MOD_NONE fourcc_mod_code(INTEL, 0x00000000000000L)
>>> +/** X tiling */
>>> +#define I915_FORMAT_MOD_X_TILED      fourcc_mod_code(INTEL, 0x00000000000001L)
>>
>> One thing I wonder here is whether we should have a modifier for each
>> physical layout (tiling modes do change slightly between hw) or whether we
>> should just continue to assume that this is Intel-specific and add a
>> disclaimer that the precise layout depends upon the actual intel box
>> you're running on?
>
> I'd kind of lean towards different modifiers per physical layout..
> that seems more useful for cases where nvidia/amd support some of the
> formats for buffer sharing..

Hm.. we've got physical layout, alignment restrictions, geometry 
restrictions, what are the odds this will be shareable or compatible, 
and how will the token names even looks when one puts all of this into them?

Regards,

Tvrtko
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Mon, Feb 02, 2015 at 04:42:32PM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 04:32 PM, Rob Clark wrote:
> >On Mon, Feb 2, 2015 at 4:41 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> >>On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>>To be used from the new addfb2 extension.
> >>>
> >>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>---
> >>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
> >>>  1 file changed, 13 insertions(+)
> >>>
> >>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> >>>index 6eed16b..a7327fd 100644
> >>>--- a/include/uapi/drm/i915_drm.h
> >>>+++ b/include/uapi/drm/i915_drm.h
> >>>@@ -28,6 +28,7 @@
> >>>  #define _UAPI_I915_DRM_H_
> >>>
> >>>  #include <drm/drm.h>
> >>>+#include <uapi/drm/drm_fourcc.h>
> >>>
> >>>  /* Please note that modifications to all structs defined here are
> >>>   * subject to backwards-compatibility constraints.
> >>>@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
> >>>       __u64 value;
> >>>  };
> >>>
> >>>+/** @{
> >>>+ * Intel framebuffer modifiers
> >>>+ *
> >>>+ * Tiling modes supported by the display hardware
> >>>+ * to be passed in via the DRM addfb2 ioctl.
> >>>+ */
> >>>+/** None */
> >>>+#define I915_FORMAT_MOD_NONE fourcc_mod_code(INTEL, 0x00000000000000L)
> >>>+/** X tiling */
> >>>+#define I915_FORMAT_MOD_X_TILED      fourcc_mod_code(INTEL, 0x00000000000001L)
> >>
> >>One thing I wonder here is whether we should have a modifier for each
> >>physical layout (tiling modes do change slightly between hw) or whether we
> >>should just continue to assume that this is Intel-specific and add a
> >>disclaimer that the precise layout depends upon the actual intel box
> >>you're running on?
> >
> >I'd kind of lean towards different modifiers per physical layout..
> >that seems more useful for cases where nvidia/amd support some of the
> >formats for buffer sharing..
> 
> Hm.. we've got physical layout, alignment restrictions, geometry
> restrictions, what are the odds this will be shareable or compatible, and
> how will the token names even looks when one puts all of this into them?

On top of that there's a _lot_ of different physical layouts for just X
tiling. At least if you look at more than just modern platforms. And often
userspace doesn't even know which precise variant it is.

I think if we eventually have a match with some other vendor format (the
one with nvidia wasn't intentionally, it only works if you have swizzling
enabled, not without swizzling) then we could do some aliasing: Define a
new vendor neutral code which then all drivers supporting it would remap
to the correct internal/vendor-specific representation.

Of course integrated gpus are special, with plug-in pci devices you really
have to spec the full thing.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 2/6] drm/i915: Add tiled framebuffer modifiers

[Rob Clark]

On Mon, Feb 2, 2015 at 11:59 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Feb 02, 2015 at 04:42:32PM +0000, Tvrtko Ursulin wrote:
>>
>> On 02/02/2015 04:32 PM, Rob Clark wrote:
>> >On Mon, Feb 2, 2015 at 4:41 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
>> >>On Fri, Jan 30, 2015 at 05:36:54PM +0000, Tvrtko Ursulin wrote:
>> >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>>
>> >>>To be used from the new addfb2 extension.
>> >>>
>> >>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>>---
>> >>>  include/uapi/drm/i915_drm.h | 13 +++++++++++++
>> >>>  1 file changed, 13 insertions(+)
>> >>>
>> >>>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> >>>index 6eed16b..a7327fd 100644
>> >>>--- a/include/uapi/drm/i915_drm.h
>> >>>+++ b/include/uapi/drm/i915_drm.h
>> >>>@@ -28,6 +28,7 @@
>> >>>  #define _UAPI_I915_DRM_H_
>> >>>
>> >>>  #include <drm/drm.h>
>> >>>+#include <uapi/drm/drm_fourcc.h>
>> >>>
>> >>>  /* Please note that modifications to all structs defined here are
>> >>>   * subject to backwards-compatibility constraints.
>> >>>@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
>> >>>       __u64 value;
>> >>>  };
>> >>>
>> >>>+/** @{
>> >>>+ * Intel framebuffer modifiers
>> >>>+ *
>> >>>+ * Tiling modes supported by the display hardware
>> >>>+ * to be passed in via the DRM addfb2 ioctl.
>> >>>+ */
>> >>>+/** None */
>> >>>+#define I915_FORMAT_MOD_NONE fourcc_mod_code(INTEL, 0x00000000000000L)
>> >>>+/** X tiling */
>> >>>+#define I915_FORMAT_MOD_X_TILED      fourcc_mod_code(INTEL, 0x00000000000001L)
>> >>
>> >>One thing I wonder here is whether we should have a modifier for each
>> >>physical layout (tiling modes do change slightly between hw) or whether we
>> >>should just continue to assume that this is Intel-specific and add a
>> >>disclaimer that the precise layout depends upon the actual intel box
>> >>you're running on?
>> >
>> >I'd kind of lean towards different modifiers per physical layout..
>> >that seems more useful for cases where nvidia/amd support some of the
>> >formats for buffer sharing..
>>
>> Hm.. we've got physical layout, alignment restrictions, geometry
>> restrictions, what are the odds this will be shareable or compatible, and
>> how will the token names even looks when one puts all of this into them?
>
> On top of that there's a _lot_ of different physical layouts for just X
> tiling. At least if you look at more than just modern platforms. And often
> userspace doesn't even know which precise variant it is.

hmm, if userspace doesn't know the format, that doesn't bode well for
sharing.. but in that case I915_FORMAT_MOD_DTRT alias might make
sense..

> I think if we eventually have a match with some other vendor format (the
> one with nvidia wasn't intentionally, it only works if you have swizzling
> enabled, not without swizzling) then we could do some aliasing: Define a
> new vendor neutral code which then all drivers supporting it would remap
> to the correct internal/vendor-specific representation.
>
> Of course integrated gpus are special, with plug-in pci devices you really
> have to spec the full thing.

the problem is if you are going to be sharing with another gpu, that
one is going to be plug-in ;-)

BR,
-R


> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[RFC 3/6] drm/i915: Set up fb modifier on initial takeover

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Initialize the simulated ioctl with the new modifier token so it can
be passed on in line with the new API usage.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3d220a6..4425e86 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2382,8 +2382,11 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
 		return false;
 
 	obj->tiling_mode = plane_config->tiling;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (obj->tiling_mode == I915_TILING_X) {
 		obj->stride = crtc->base.primary->fb->pitches[0];
+		mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
+		mode_cmd.modifier[0] = I915_FORMAT_MOD_X_TILED;
+	}
 
 	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
 	mode_cmd.width = crtc->base.primary->fb->width;
-- 
2.2.2

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[RFC 4/6] drm/i915: Use framebuffer tiling mode for display purposes

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

To prepare for framebuffer modifiers, move tiling definition from the
object into the framebuffer. Move in a way that framebuffer tiling is
now used for display while object tiling remains for fencing.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 drivers/gpu/drm/i915/intel_pm.c      |  7 +++---
 drivers/gpu/drm/i915/intel_sprite.c  | 26 ++++++++++----------
 4 files changed, 46 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4425e86..e22afbe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2211,7 +2211,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	switch (obj->tiling_mode) {
+	switch (to_intel_framebuffer(fb)->tiling_mode) {
 	case I915_TILING_NONE:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
@@ -2474,6 +2474,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2545,8 +2546,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4 &&
-	    obj->tiling_mode != I915_TILING_NONE)
+	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
@@ -2556,7 +2556,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(&x, &y,
+						       tiling_mode,
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2606,6 +2607,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2654,7 +2656,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -2662,7 +2664,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y,
+					       tiling_mode,
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
@@ -2750,7 +2753,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	switch (obj->tiling_mode) {
+	switch (to_intel_framebuffer(fb)->tiling_mode) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -9291,7 +9294,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	intel_ring_emit(ring, fb->pitches[0]);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
-			obj->tiling_mode);
+			to_intel_framebuffer(fb)->tiling_mode);
 
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
@@ -9324,7 +9327,8 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP |
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+	intel_ring_emit(ring,
+			fb->pitches[0] | to_intel_framebuffer(fb)->tiling_mode);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	/* Contrary to the suggestions in the documentation,
@@ -9428,7 +9432,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	}
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+	intel_ring_emit(ring,
+			fb->pitches[0] | to_intel_framebuffer(fb)->tiling_mode);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
@@ -9470,13 +9475,12 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	const enum pipe pipe = intel_crtc->pipe;
 	u32 ctl, stride;
 
 	ctl = I915_READ(PLANE_CTL(pipe, 0));
 	ctl &= ~PLANE_CTL_TILED_MASK;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (intel_fb->tiling_mode == I915_TILING_X)
 		ctl |= PLANE_CTL_TILED_X;
 
 	/*
@@ -9484,7 +9488,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	stride = fb->pitches[0] >> 6;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (intel_fb->tiling_mode == I915_TILING_X)
 		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
 
 	/*
@@ -9504,14 +9508,13 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_framebuffer *intel_fb =
 		to_intel_framebuffer(intel_crtc->base.primary->fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	u32 dspcntr;
 	u32 reg;
 
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (intel_fb->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
@@ -9595,6 +9598,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t plane = 0, stride;
 	int ret;
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	switch(intel_crtc->pipe) {
 	case PIPE_A:
@@ -9611,7 +9615,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 		return -ENODEV;
 	}
 
-	switch (obj->tiling_mode) {
+	switch (tiling_mode) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -9639,7 +9643,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, 0);
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
+	intel_ring_emit(ring, stride << 6 | tiling_mode);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	intel_mark_page_flip_active(intel_crtc);
@@ -9764,6 +9768,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	work->event = event;
 	work->crtc = crtc;
 	work->old_fb_obj = intel_fb_obj(old_fb);
+	work->old_tiling_mode = to_intel_framebuffer(old_fb)->tiling_mode;
 	INIT_WORK(&work->work, intel_unpin_work_fn);
 
 	ret = drm_crtc_vblank_get(crtc);
@@ -9814,7 +9819,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-		if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
+		if (to_intel_framebuffer(fb)->tiling_mode !=
+		    work->old_tiling_mode)
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			ring = NULL;
 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -12190,7 +12196,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
+	    to_intel_framebuffer(fb)->tiling_mode) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		ret = -EINVAL;
 	}
@@ -12772,6 +12779,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
 	intel_fb->obj = obj;
 	intel_fb->obj->framebuffer_references++;
+	intel_fb->tiling_mode = obj->tiling_mode;
 
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eef79cc..b8d8a1d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -120,6 +120,7 @@ enum intel_output_type {
 struct intel_framebuffer {
 	struct drm_framebuffer base;
 	struct drm_i915_gem_object *obj;
+	unsigned int tiling_mode;
 };
 
 struct intel_fbdev {
@@ -723,6 +724,7 @@ struct intel_unpin_work {
 	int flip_queued_vblank;
 	int flip_ready_vblank;
 	bool enable_stall_check;
+	unsigned int old_tiling_mode;
 };
 
 struct intel_set_config {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ece663..0ca4088 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1182,12 +1182,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
 	if (IS_I915GM(dev) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->primary->fb);
+		struct intel_framebuffer *intel_fb;
 
 		/* self-refresh seems busted with untiled */
-		if (obj->tiling_mode == I915_TILING_NONE)
+		intel_fb = to_intel_framebuffer(enabled->primary->fb);
+		if (intel_fb->tiling_mode == I915_TILING_NONE)
 			enabled = NULL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44..0659802 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -245,7 +245,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
-	switch (obj->tiling_mode) {
+	switch (to_intel_framebuffer(fb)->tiling_mode) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 
@@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SP_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		sprctl |= SP_TILED;
 
 	sprctl |= SP_ENABLE;
@@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
-							obj->tiling_mode,
+							tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	u32 sprctl, sprscale = 0;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	sprctl = I915_READ(SPRCTL(pipe));
 
@@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		sprctl |= SPRITE_TILED;
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 * register */
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-	else if (obj->tiling_mode != I915_TILING_NONE)
+	else if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	unsigned long dvssurf_offset, linear_offset;
 	u32 dvscntr, dvsscale;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
 
 	dvscntr = I915_READ(DVSCNTR(pipe));
 
@@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	dvscntr |= DVS_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		dvscntr |= DVS_TILED;
 
 	if (IS_GEN6(dev))
@@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
@@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(DVSLINOFF(pipe), linear_offset);
@@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int crtc_x, crtc_y;
 	unsigned int crtc_w, crtc_h;
 	uint32_t src_x, src_y, src_w, src_h;
@@ -1107,7 +1109,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	}
 
 	/* Sprite planes can be linear or x-tiled surfaces */
-	switch (obj->tiling_mode) {
+	switch (to_intel_framebuffer(fb)->tiling_mode) {
 		case I915_TILING_NONE:
 		case I915_TILING_X:
 			break;
-- 
2.2.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
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Re: [RFC 4/6] drm/i915: Use framebuffer tiling mode for display purposes

[Daniel Vetter]

On Fri, Jan 30, 2015 at 05:36:56PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> To prepare for framebuffer modifiers, move tiling definition from the
> object into the framebuffer. Move in a way that framebuffer tiling is
> now used for display while object tiling remains for fencing.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c      |  7 +++---
>  drivers/gpu/drm/i915/intel_sprite.c  | 26 ++++++++++----------
>  4 files changed, 46 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4425e86..e22afbe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2211,7 +2211,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>  
>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>  
> -	switch (obj->tiling_mode) {
> +	switch (to_intel_framebuffer(fb)->tiling_mode) {
>  	case I915_TILING_NONE:

Imo we should just look at fb->modifier[0] and flip over all the enums. A
bit more invasive, but we also don't need to change all the platform code
at once - set_tiling already guarantees that no one can modify the bo
tiling mode when there's an fb object using it. Which means we can change
the code over at leasure.

>  		if (INTEL_INFO(dev)->gen >= 9)
>  			alignment = 256 * 1024;
> @@ -2474,6 +2474,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	u32 dspcntr;
>  	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	if (!intel_crtc->primary_enabled) {
>  		I915_WRITE(reg, 0);
> @@ -2545,8 +2546,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (INTEL_INFO(dev)->gen >= 4 &&
> -	    obj->tiling_mode != I915_TILING_NONE)
> +	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  
>  	if (IS_G4X(dev))
> @@ -2556,7 +2556,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		intel_crtc->dspaddr_offset =
> -			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +			intel_gen4_compute_page_offset(&x, &y,
> +						       tiling_mode,
>  						       pixel_size,
>  						       fb->pitches[0]);
>  		linear_offset -= intel_crtc->dspaddr_offset;
> @@ -2606,6 +2607,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	u32 dspcntr;
>  	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	if (!intel_crtc->primary_enabled) {
>  		I915_WRITE(reg, 0);
> @@ -2654,7 +2656,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  
>  	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> @@ -2662,7 +2664,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	intel_crtc->dspaddr_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y,
> +					       tiling_mode,
>  					       pixel_size,
>  					       fb->pitches[0]);
>  	linear_offset -= intel_crtc->dspaddr_offset;
> @@ -2750,7 +2753,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  	 * The stride is either expressed as a multiple of 64 bytes chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	switch (obj->tiling_mode) {
> +	switch (to_intel_framebuffer(fb)->tiling_mode) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -9291,7 +9294,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
>  			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
>  	intel_ring_emit(ring, fb->pitches[0]);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
> -			obj->tiling_mode);
> +			to_intel_framebuffer(fb)->tiling_mode);
>  
>  	/* XXX Enabling the panel-fitter across page-flip is so far
>  	 * untested on non-native modes, so ignore it for now.
> @@ -9324,7 +9327,8 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP |
>  			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> -	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
> +	intel_ring_emit(ring,
> +			fb->pitches[0] | to_intel_framebuffer(fb)->tiling_mode);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  
>  	/* Contrary to the suggestions in the documentation,
> @@ -9428,7 +9432,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
>  	}
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
> -	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
> +	intel_ring_emit(ring,
> +			fb->pitches[0] | to_intel_framebuffer(fb)->tiling_mode);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  	intel_ring_emit(ring, (MI_NOOP));
>  
> @@ -9470,13 +9475,12 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	struct drm_i915_gem_object *obj = intel_fb->obj;
>  	const enum pipe pipe = intel_crtc->pipe;
>  	u32 ctl, stride;
>  
>  	ctl = I915_READ(PLANE_CTL(pipe, 0));
>  	ctl &= ~PLANE_CTL_TILED_MASK;
> -	if (obj->tiling_mode == I915_TILING_X)
> +	if (intel_fb->tiling_mode == I915_TILING_X)
>  		ctl |= PLANE_CTL_TILED_X;
>  
>  	/*
> @@ -9484,7 +9488,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
>  	stride = fb->pitches[0] >> 6;
> -	if (obj->tiling_mode == I915_TILING_X)
> +	if (intel_fb->tiling_mode == I915_TILING_X)
>  		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
>  
>  	/*
> @@ -9504,14 +9508,13 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_framebuffer *intel_fb =
>  		to_intel_framebuffer(intel_crtc->base.primary->fb);
> -	struct drm_i915_gem_object *obj = intel_fb->obj;
>  	u32 dspcntr;
>  	u32 reg;
>  
>  	reg = DSPCNTR(intel_crtc->plane);
>  	dspcntr = I915_READ(reg);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (intel_fb->tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  	else
>  		dspcntr &= ~DISPPLANE_TILED;
> @@ -9595,6 +9598,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	uint32_t plane = 0, stride;
>  	int ret;
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	switch(intel_crtc->pipe) {
>  	case PIPE_A:
> @@ -9611,7 +9615,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  		return -ENODEV;
>  	}
>  
> -	switch (obj->tiling_mode) {
> +	switch (tiling_mode) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -9639,7 +9643,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  	intel_ring_emit(ring, 0);
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
> -	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
> +	intel_ring_emit(ring, stride << 6 | tiling_mode);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  
>  	intel_mark_page_flip_active(intel_crtc);
> @@ -9764,6 +9768,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  	work->event = event;
>  	work->crtc = crtc;
>  	work->old_fb_obj = intel_fb_obj(old_fb);
> +	work->old_tiling_mode = to_intel_framebuffer(old_fb)->tiling_mode;

Hm, that's actually an interesting bugfix - currently userspace could be
sneaky and destroy the old fb immediately after the flip completes and the
change the tiling of the underlying object before the unpin work had a
chance to run (needs some fudgin with rt prios to starve workers to make
this work though).

Imo the right fix is to hold a reference onto the fb and not the
underlying gem object. With that tiling is guaranteed not to change.

>  	INIT_WORK(&work->work, intel_unpin_work_fn);
>  
>  	ret = drm_crtc_vblank_get(crtc);
> @@ -9814,7 +9819,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		ring = &dev_priv->ring[BCS];
> -		if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
> +		if (to_intel_framebuffer(fb)->tiling_mode !=
> +		    work->old_tiling_mode)
>  			/* vlv: DISPLAY_FLIP fails to change tiling */
>  			ring = NULL;
>  	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> @@ -12190,7 +12196,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
>  
>  	/* we only need to pin inside GTT if cursor is non-phy */
>  	mutex_lock(&dev->struct_mutex);
> -	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
> +	if (!INTEL_INFO(dev)->cursor_needs_physical &&
> +	    to_intel_framebuffer(fb)->tiling_mode) {
>  		DRM_DEBUG_KMS("cursor cannot be tiled\n");
>  		ret = -EINVAL;
>  	}
> @@ -12772,6 +12779,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
>  	intel_fb->obj = obj;
>  	intel_fb->obj->framebuffer_references++;
> +	intel_fb->tiling_mode = obj->tiling_mode;

One side-effect of using fb->modifier[0] is that if the modifier flag is
_not_ set, we need to reconstruct this field from obj->tiling_mode here.
Otoh if it is set this code here should check that fb->modifier and
obj->tiling_mode are consistent.

Perhaps best to split this change out as a prep patch, like you've done
with the code for the initial framebuffer.

>  
>  	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
>  	if (ret) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index eef79cc..b8d8a1d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -120,6 +120,7 @@ enum intel_output_type {
>  struct intel_framebuffer {
>  	struct drm_framebuffer base;
>  	struct drm_i915_gem_object *obj;
> +	unsigned int tiling_mode;
>  };
>  
>  struct intel_fbdev {
> @@ -723,6 +724,7 @@ struct intel_unpin_work {
>  	int flip_queued_vblank;
>  	int flip_ready_vblank;
>  	bool enable_stall_check;
> +	unsigned int old_tiling_mode;
>  };
>  
>  struct intel_set_config {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6ece663..0ca4088 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1182,12 +1182,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>  	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
>  
>  	if (IS_I915GM(dev) && enabled) {
> -		struct drm_i915_gem_object *obj;
> -
> -		obj = intel_fb_obj(enabled->primary->fb);
> +		struct intel_framebuffer *intel_fb;
>  
>  		/* self-refresh seems busted with untiled */
> -		if (obj->tiling_mode == I915_TILING_NONE)
> +		intel_fb = to_intel_framebuffer(enabled->primary->fb);
> +		if (intel_fb->tiling_mode == I915_TILING_NONE)
>  			enabled = NULL;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0a52c44..0659802 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -245,7 +245,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	switch (obj->tiling_mode) {
> +	switch (to_intel_framebuffer(fb)->tiling_mode) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	u32 sprctl;
>  	unsigned long sprsurf_offset, linear_offset;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	sprctl = I915_READ(SPCNTR(pipe, plane));
>  
> @@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	 */
>  	sprctl |= SP_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		sprctl |= SP_TILED;
>  
>  	sprctl |= SP_ENABLE;
> @@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
> -							obj->tiling_mode,
> +							tiling_mode,
>  							pixel_size,
>  							fb->pitches[0]);
>  	linear_offset -= sprsurf_offset;
> @@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
>  	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
>  	else
>  		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> @@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	u32 sprctl, sprscale = 0;
>  	unsigned long sprsurf_offset, linear_offset;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	sprctl = I915_READ(SPRCTL(pipe));
>  
> @@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 */
>  	sprctl |= SPRITE_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		sprctl |= SPRITE_TILED;
>  
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> @@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	sprsurf_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  					       pixel_size, fb->pitches[0]);
>  	linear_offset -= sprsurf_offset;
>  
> @@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 * register */
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
> -	else if (obj->tiling_mode != I915_TILING_NONE)
> +	else if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
>  	else
>  		I915_WRITE(SPRLINOFF(pipe), linear_offset);
> @@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	unsigned long dvssurf_offset, linear_offset;
>  	u32 dvscntr, dvsscale;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = to_intel_framebuffer(fb)->tiling_mode;
>  
>  	dvscntr = I915_READ(DVSCNTR(pipe));
>  
> @@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 */
>  	dvscntr |= DVS_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		dvscntr |= DVS_TILED;
>  
>  	if (IS_GEN6(dev))
> @@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	dvssurf_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  					       pixel_size, fb->pitches[0]);
>  	linear_offset -= dvssurf_offset;
>  
> @@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
>  	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
>  	else
>  		I915_WRITE(DVSLINOFF(pipe), linear_offset);
> @@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
>  	struct intel_plane *intel_plane = to_intel_plane(plane);
>  	struct drm_framebuffer *fb = state->base.fb;
> -	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	int crtc_x, crtc_y;
>  	unsigned int crtc_w, crtc_h;
>  	uint32_t src_x, src_y, src_w, src_h;
> @@ -1107,7 +1109,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>  	}
>  
>  	/* Sprite planes can be linear or x-tiled surfaces */
> -	switch (obj->tiling_mode) {
> +	switch (to_intel_framebuffer(fb)->tiling_mode) {
>  		case I915_TILING_NONE:
>  		case I915_TILING_X:
>  			break;
> -- 
> 2.2.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC 4/6] drm/i915: Use framebuffer tiling mode for display purposes

[Tvrtko Ursulin]

On 02/02/2015 09:49 AM, Daniel Vetter wrote:
> On Fri, Jan 30, 2015 at 05:36:56PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> To prepare for framebuffer modifiers, move tiling definition from the
>> object into the framebuffer. Move in a way that framebuffer tiling is
>> now used for display while object tiling remains for fencing.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++---------------
>>   drivers/gpu/drm/i915/intel_drv.h     |  2 ++
>>   drivers/gpu/drm/i915/intel_pm.c      |  7 +++---
>>   drivers/gpu/drm/i915/intel_sprite.c  | 26 ++++++++++----------
>>   4 files changed, 46 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 4425e86..e22afbe 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2211,7 +2211,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>>
>>   	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>>
>> -	switch (obj->tiling_mode) {
>> +	switch (to_intel_framebuffer(fb)->tiling_mode) {
>>   	case I915_TILING_NONE:
>
> Imo we should just look at fb->modifier[0] and flip over all the enums. A
> bit more invasive, but we also don't need to change all the platform code
> at once - set_tiling already guarantees that no one can modify the bo
> tiling mode when there's an fb object using it. Which means we can change
> the code over at leasure.

What do you mean by "flip over"?

To make places which need to get fb tiling format use fb->modifier[0] 
directly rather than have them mapped to tiling enums at fb init?

>> @@ -9764,6 +9768,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>>   	work->event = event;
>>   	work->crtc = crtc;
>>   	work->old_fb_obj = intel_fb_obj(old_fb);
>> +	work->old_tiling_mode = to_intel_framebuffer(old_fb)->tiling_mode;
>
> Hm, that's actually an interesting bugfix - currently userspace could be
> sneaky and destroy the old fb immediately after the flip completes and the
> change the tiling of the underlying object before the unpin work had a
> chance to run (needs some fudgin with rt prios to starve workers to make
> this work though).
>
> Imo the right fix is to hold a reference onto the fb and not the
> underlying gem object. With that tiling is guaranteed not to change.

Ok I'll pull it out in a separate patch.

>>   	INIT_WORK(&work->work, intel_unpin_work_fn);
>>
>>   	ret = drm_crtc_vblank_get(crtc);
>> @@ -9814,7 +9819,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>>
>>   	if (IS_VALLEYVIEW(dev)) {
>>   		ring = &dev_priv->ring[BCS];
>> -		if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
>> +		if (to_intel_framebuffer(fb)->tiling_mode !=
>> +		    work->old_tiling_mode)
>>   			/* vlv: DISPLAY_FLIP fails to change tiling */
>>   			ring = NULL;
>>   	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
>> @@ -12190,7 +12196,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
>>
>>   	/* we only need to pin inside GTT if cursor is non-phy */
>>   	mutex_lock(&dev->struct_mutex);
>> -	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
>> +	if (!INTEL_INFO(dev)->cursor_needs_physical &&
>> +	    to_intel_framebuffer(fb)->tiling_mode) {
>>   		DRM_DEBUG_KMS("cursor cannot be tiled\n");
>>   		ret = -EINVAL;
>>   	}
>> @@ -12772,6 +12779,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>   	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
>>   	intel_fb->obj = obj;
>>   	intel_fb->obj->framebuffer_references++;
>> +	intel_fb->tiling_mode = obj->tiling_mode;
>
> One side-effect of using fb->modifier[0] is that if the modifier flag is
> _not_ set, we need to reconstruct this field from obj->tiling_mode here.
> Otoh if it is set this code here should check that fb->modifier and
> obj->tiling_mode are consistent.
>
> Perhaps best to split this change out as a prep patch, like you've done
> with the code for the initial framebuffer.

If I understood correctly what you meant in the first quote then yes.

Regards,

Tvrtko
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Re: [RFC 4/6] drm/i915: Use framebuffer tiling mode for display purposes

[Daniel Vetter]

On Mon, Feb 02, 2015 at 10:29:19AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 09:49 AM, Daniel Vetter wrote:
> >On Fri, Jan 30, 2015 at 05:36:56PM +0000, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >>To prepare for framebuffer modifiers, move tiling definition from the
> >>object into the framebuffer. Move in a way that framebuffer tiling is
> >>now used for display while object tiling remains for fencing.
> >>
> >>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++---------------
> >>  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
> >>  drivers/gpu/drm/i915/intel_pm.c      |  7 +++---
> >>  drivers/gpu/drm/i915/intel_sprite.c  | 26 ++++++++++----------
> >>  4 files changed, 46 insertions(+), 35 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>index 4425e86..e22afbe 100644
> >>--- a/drivers/gpu/drm/i915/intel_display.c
> >>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>@@ -2211,7 +2211,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
> >>
> >>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> >>
> >>-	switch (obj->tiling_mode) {
> >>+	switch (to_intel_framebuffer(fb)->tiling_mode) {
> >>  	case I915_TILING_NONE:
> >
> >Imo we should just look at fb->modifier[0] and flip over all the enums. A
> >bit more invasive, but we also don't need to change all the platform code
> >at once - set_tiling already guarantees that no one can modify the bo
> >tiling mode when there's an fb object using it. Which means we can change
> >the code over at leasure.
> 
> What do you mean by "flip over"?
> 
> To make places which need to get fb tiling format use fb->modifier[0]
> directly rather than have them mapped to tiling enums at fb init?

Yes. That way we can drop intel_fb->tiling_mode and have one less somewhat
redundant thing to keep in sync with everything else. Hoping that everyone
just uses the same ime just doesn't work ;-)

> >>@@ -9764,6 +9768,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> >>  	work->event = event;
> >>  	work->crtc = crtc;
> >>  	work->old_fb_obj = intel_fb_obj(old_fb);
> >>+	work->old_tiling_mode = to_intel_framebuffer(old_fb)->tiling_mode;
> >
> >Hm, that's actually an interesting bugfix - currently userspace could be
> >sneaky and destroy the old fb immediately after the flip completes and the
> >change the tiling of the underlying object before the unpin work had a
> >chance to run (needs some fudgin with rt prios to starve workers to make
> >this work though).
> >
> >Imo the right fix is to hold a reference onto the fb and not the
> >underlying gem object. With that tiling is guaranteed not to change.
> 
> Ok I'll pull it out in a separate patch.
> 
> >>  	INIT_WORK(&work->work, intel_unpin_work_fn);
> >>
> >>  	ret = drm_crtc_vblank_get(crtc);
> >>@@ -9814,7 +9819,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> >>
> >>  	if (IS_VALLEYVIEW(dev)) {
> >>  		ring = &dev_priv->ring[BCS];
> >>-		if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
> >>+		if (to_intel_framebuffer(fb)->tiling_mode !=
> >>+		    work->old_tiling_mode)
> >>  			/* vlv: DISPLAY_FLIP fails to change tiling */
> >>  			ring = NULL;
> >>  	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> >>@@ -12190,7 +12196,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
> >>
> >>  	/* we only need to pin inside GTT if cursor is non-phy */
> >>  	mutex_lock(&dev->struct_mutex);
> >>-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
> >>+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
> >>+	    to_intel_framebuffer(fb)->tiling_mode) {
> >>  		DRM_DEBUG_KMS("cursor cannot be tiled\n");
> >>  		ret = -EINVAL;
> >>  	}
> >>@@ -12772,6 +12779,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> >>  	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
> >>  	intel_fb->obj = obj;
> >>  	intel_fb->obj->framebuffer_references++;
> >>+	intel_fb->tiling_mode = obj->tiling_mode;
> >
> >One side-effect of using fb->modifier[0] is that if the modifier flag is
> >_not_ set, we need to reconstruct this field from obj->tiling_mode here.
> >Otoh if it is set this code here should check that fb->modifier and
> >obj->tiling_mode are consistent.
> >
> >Perhaps best to split this change out as a prep patch, like you've done
> >with the code for the initial framebuffer.
> 
> If I understood correctly what you meant in the first quote then yes.

You've already done it, it's the next patch - I just read patch series
sequentially ;-) Patch needs a bit of adjustment ofc due to the removal of
intel_fb->tiling_mode, and needs to be before this one here so that
fb->modifier[0] is guaranteed to be valid also for legacy userspace.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Use the fb modifier if it was specified over object tiling mode.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e22afbe..ca69da0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
 	.create_handle = intel_user_framebuffer_create_handle,
 };
 
+static unsigned int
+intel_fb_modifier_to_tiling(u64 modifier)
+{
+	switch (modifier) {
+	case I915_FORMAT_MOD_X_TILED:
+		return I915_TILING_X;
+	default:
+	case I915_FORMAT_MOD_NONE:
+		break;
+	}
+
+	return I915_TILING_NONE;
+}
+
 static int intel_framebuffer_init(struct drm_device *dev,
 				  struct intel_framebuffer *intel_fb,
 				  struct drm_mode_fb_cmd2 *mode_cmd,
@@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
 {
 	int aligned_height;
 	int pitch_limit;
+	unsigned int tiling_mode = obj->tiling_mode;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	if (obj->tiling_mode == I915_TILING_Y) {
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
+		tiling_mode =
+			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
+		if (tiling_mode != obj->tiling_mode &&
+			obj->tiling_mode != I915_TILING_NONE) {
+			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
+					tiling_mode, obj->tiling_mode);
+			return -EINVAL;
+		}
+	}
+
+	if (tiling_mode == I915_TILING_Y) {
 		DRM_DEBUG("hardware does not support tiling Y\n");
 		return -EINVAL;
 	}
@@ -12696,12 +12722,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 16*1024;
 		else
 			pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 3) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 8*1024;
 		else
 			pitch_limit = 16*1024;
@@ -12711,12 +12737,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-			  obj->tiling_mode ? "tiled" : "linear",
+			  tiling_mode ? "tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE &&
+	if (tiling_mode != I915_TILING_NONE && obj->stride &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
@@ -12771,7 +12797,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-					       obj->tiling_mode);
+					       tiling_mode);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
@@ -12779,7 +12805,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
 	intel_fb->obj = obj;
 	intel_fb->obj->framebuffer_references++;
-	intel_fb->tiling_mode = obj->tiling_mode;
+	intel_fb->tiling_mode = tiling_mode;
 
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
-- 
2.2.2

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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Daniel Vetter]

On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Use the fb modifier if it was specified over object tiling mode.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
>  1 file changed, 33 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e22afbe..ca69da0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
>  	.create_handle = intel_user_framebuffer_create_handle,
>  };
>  
> +static unsigned int
> +intel_fb_modifier_to_tiling(u64 modifier)
> +{
> +	switch (modifier) {
> +	case I915_FORMAT_MOD_X_TILED:
> +		return I915_TILING_X;
> +	default:
> +	case I915_FORMAT_MOD_NONE:
> +		break;
> +	}
> +
> +	return I915_TILING_NONE;
> +}
> +
>  static int intel_framebuffer_init(struct drm_device *dev,
>  				  struct intel_framebuffer *intel_fb,
>  				  struct drm_mode_fb_cmd2 *mode_cmd,
> @@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  {
>  	int aligned_height;
>  	int pitch_limit;
> +	unsigned int tiling_mode = obj->tiling_mode;
>  	int ret;
>  
>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>  
> -	if (obj->tiling_mode == I915_TILING_Y) {
> +	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
> +		tiling_mode =
> +			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
> +		if (tiling_mode != obj->tiling_mode &&
> +			obj->tiling_mode != I915_TILING_NONE) {
> +			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
> +					tiling_mode, obj->tiling_mode);
> +			return -EINVAL;
> +		}
> +	}

Ah, here comes the magic. I think this might be simpler if we just use
->modifier (and fix it up if FB_MODIFIERS isn't set).

Btw another reason for this split is that this way we have a clear
separation between the tiling modes supported generally (as fb modifiers)
and the tiling modes supported by fences. It might therefore make sense to
rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
->fence_tiling_mode). To make it really clear that it's just about the
global gtt fences and nothing more.
-Daniel

> +
> +	if (tiling_mode == I915_TILING_Y) {
>  		DRM_DEBUG("hardware does not support tiling Y\n");
>  		return -EINVAL;
>  	}
> @@ -12696,12 +12722,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
>  		pitch_limit = 32*1024;
>  	} else if (INTEL_INFO(dev)->gen >= 4) {
> -		if (obj->tiling_mode)
> +		if (tiling_mode)
>  			pitch_limit = 16*1024;
>  		else
>  			pitch_limit = 32*1024;
>  	} else if (INTEL_INFO(dev)->gen >= 3) {
> -		if (obj->tiling_mode)
> +		if (tiling_mode)
>  			pitch_limit = 8*1024;
>  		else
>  			pitch_limit = 16*1024;
> @@ -12711,12 +12737,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  
>  	if (mode_cmd->pitches[0] > pitch_limit) {
>  		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
> -			  obj->tiling_mode ? "tiled" : "linear",
> +			  tiling_mode ? "tiled" : "linear",
>  			  mode_cmd->pitches[0], pitch_limit);
>  		return -EINVAL;
>  	}
>  
> -	if (obj->tiling_mode != I915_TILING_NONE &&
> +	if (tiling_mode != I915_TILING_NONE && obj->stride &&
>  	    mode_cmd->pitches[0] != obj->stride) {
>  		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
>  			  mode_cmd->pitches[0], obj->stride);
> @@ -12771,7 +12797,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		return -EINVAL;
>  
>  	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
> -					       obj->tiling_mode);
> +					       tiling_mode);
>  	/* FIXME drm helper for size checks (especially planar formats)? */
>  	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
>  		return -EINVAL;
> @@ -12779,7 +12805,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
>  	intel_fb->obj = obj;
>  	intel_fb->obj->framebuffer_references++;
> -	intel_fb->tiling_mode = obj->tiling_mode;
> +	intel_fb->tiling_mode = tiling_mode;
>  
>  	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
>  	if (ret) {
> -- 
> 2.2.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Tvrtko Ursulin]

On 02/02/2015 09:54 AM, Daniel Vetter wrote:
> On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Use the fb modifier if it was specified over object tiling mode.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
>>   1 file changed, 33 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index e22afbe..ca69da0 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
>>   	.create_handle = intel_user_framebuffer_create_handle,
>>   };
>>
>> +static unsigned int
>> +intel_fb_modifier_to_tiling(u64 modifier)
>> +{
>> +	switch (modifier) {
>> +	case I915_FORMAT_MOD_X_TILED:
>> +		return I915_TILING_X;
>> +	default:
>> +	case I915_FORMAT_MOD_NONE:
>> +		break;
>> +	}
>> +
>> +	return I915_TILING_NONE;
>> +}
>> +
>>   static int intel_framebuffer_init(struct drm_device *dev,
>>   				  struct intel_framebuffer *intel_fb,
>>   				  struct drm_mode_fb_cmd2 *mode_cmd,
>> @@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>   {
>>   	int aligned_height;
>>   	int pitch_limit;
>> +	unsigned int tiling_mode = obj->tiling_mode;
>>   	int ret;
>>
>>   	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>>
>> -	if (obj->tiling_mode == I915_TILING_Y) {
>> +	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
>> +		tiling_mode =
>> +			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
>> +		if (tiling_mode != obj->tiling_mode &&
>> +			obj->tiling_mode != I915_TILING_NONE) {
>> +			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
>> +					tiling_mode, obj->tiling_mode);
>> +			return -EINVAL;
>> +		}
>> +	}
>
> Ah, here comes the magic. I think this might be simpler if we just use
> ->modifier (and fix it up if FB_MODIFIERS isn't set).
>
> Btw another reason for this split is that this way we have a clear
> separation between the tiling modes supported generally (as fb modifiers)
> and the tiling modes supported by fences. It might therefore make sense to
> rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
> ->fence_tiling_mode). To make it really clear that it's just about the
> global gtt fences and nothing more.

I don't really like using ->modifier directly in tiling patch since it 
is an bag of unrelated stuff, not only a superset. Unrelated especially, 
but not only, from the point of view of call sites / users.

Therefore I see some design elegance in extracting the tiling, or any 
other logical group of modifiers before hand.

At the very least would call something like 
intel_fb_modifier_to_tiling(), but, it is very ugly to have a dynamic 
cost at every call site. Which is another reason why I preferred to 
extract the data before hand.

Regards,

Tvrtko
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Daniel Vetter]

On Mon, Feb 02, 2015 at 10:36:30AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 09:54 AM, Daniel Vetter wrote:
> >On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >>Use the fb modifier if it was specified over object tiling mode.
> >>
> >>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
> >>  1 file changed, 33 insertions(+), 7 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>index e22afbe..ca69da0 100644
> >>--- a/drivers/gpu/drm/i915/intel_display.c
> >>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>@@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> >>  	.create_handle = intel_user_framebuffer_create_handle,
> >>  };
> >>
> >>+static unsigned int
> >>+intel_fb_modifier_to_tiling(u64 modifier)
> >>+{
> >>+	switch (modifier) {
> >>+	case I915_FORMAT_MOD_X_TILED:
> >>+		return I915_TILING_X;
> >>+	default:
> >>+	case I915_FORMAT_MOD_NONE:
> >>+		break;
> >>+	}
> >>+
> >>+	return I915_TILING_NONE;
> >>+}
> >>+
> >>  static int intel_framebuffer_init(struct drm_device *dev,
> >>  				  struct intel_framebuffer *intel_fb,
> >>  				  struct drm_mode_fb_cmd2 *mode_cmd,
> >>@@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
> >>  {
> >>  	int aligned_height;
> >>  	int pitch_limit;
> >>+	unsigned int tiling_mode = obj->tiling_mode;
> >>  	int ret;
> >>
> >>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> >>
> >>-	if (obj->tiling_mode == I915_TILING_Y) {
> >>+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
> >>+		tiling_mode =
> >>+			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
> >>+		if (tiling_mode != obj->tiling_mode &&
> >>+			obj->tiling_mode != I915_TILING_NONE) {
> >>+			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
> >>+					tiling_mode, obj->tiling_mode);
> >>+			return -EINVAL;
> >>+		}
> >>+	}
> >
> >Ah, here comes the magic. I think this might be simpler if we just use
> >->modifier (and fix it up if FB_MODIFIERS isn't set).
> >
> >Btw another reason for this split is that this way we have a clear
> >separation between the tiling modes supported generally (as fb modifiers)
> >and the tiling modes supported by fences. It might therefore make sense to
> >rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
> >->fence_tiling_mode). To make it really clear that it's just about the
> >global gtt fences and nothing more.
> 
> I don't really like using ->modifier directly in tiling patch since it is an
> bag of unrelated stuff, not only a superset. Unrelated especially, but not
> only, from the point of view of call sites / users.
> 
> Therefore I see some design elegance in extracting the tiling, or any other
> logical group of modifiers before hand.
> 
> At the very least would call something like intel_fb_modifier_to_tiling(),
> but, it is very ugly to have a dynamic cost at every call site. Which is
> another reason why I preferred to extract the data before hand.

The reason is that the current tiling_mode enum is userspace ABI, and
it's just for how to fence global gtt mappings. That's the point of
splitting the fb modifiers out like in this rfc.

So if you add your fancy new tiling mode you can't do that, since you
can't extend the tiling_mode enum. Adding another enum also seems a bit
too much when we already have fb_modifiers.

And if fb_modifiers get too complicated we can add helper functions which
normalize stuff, e.g. extract just the base tiling mode and remove other
things (like compression mode or whatever it's going to be).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Tvrtko Ursulin]

On 02/02/2015 05:15 PM, Daniel Vetter wrote:
> On Mon, Feb 02, 2015 at 10:36:30AM +0000, Tvrtko Ursulin wrote:
>>
>> On 02/02/2015 09:54 AM, Daniel Vetter wrote:
>>> On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Use the fb modifier if it was specified over object tiling mode.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
>>>>   1 file changed, 33 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>> index e22afbe..ca69da0 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
>>>>   	.create_handle = intel_user_framebuffer_create_handle,
>>>>   };
>>>>
>>>> +static unsigned int
>>>> +intel_fb_modifier_to_tiling(u64 modifier)
>>>> +{
>>>> +	switch (modifier) {
>>>> +	case I915_FORMAT_MOD_X_TILED:
>>>> +		return I915_TILING_X;
>>>> +	default:
>>>> +	case I915_FORMAT_MOD_NONE:
>>>> +		break;
>>>> +	}
>>>> +
>>>> +	return I915_TILING_NONE;
>>>> +}
>>>> +
>>>>   static int intel_framebuffer_init(struct drm_device *dev,
>>>>   				  struct intel_framebuffer *intel_fb,
>>>>   				  struct drm_mode_fb_cmd2 *mode_cmd,
>>>> @@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>>>   {
>>>>   	int aligned_height;
>>>>   	int pitch_limit;
>>>> +	unsigned int tiling_mode = obj->tiling_mode;
>>>>   	int ret;
>>>>
>>>>   	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>>>>
>>>> -	if (obj->tiling_mode == I915_TILING_Y) {
>>>> +	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
>>>> +		tiling_mode =
>>>> +			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
>>>> +		if (tiling_mode != obj->tiling_mode &&
>>>> +			obj->tiling_mode != I915_TILING_NONE) {
>>>> +			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
>>>> +					tiling_mode, obj->tiling_mode);
>>>> +			return -EINVAL;
>>>> +		}
>>>> +	}
>>>
>>> Ah, here comes the magic. I think this might be simpler if we just use
>>> ->modifier (and fix it up if FB_MODIFIERS isn't set).
>>>
>>> Btw another reason for this split is that this way we have a clear
>>> separation between the tiling modes supported generally (as fb modifiers)
>>> and the tiling modes supported by fences. It might therefore make sense to
>>> rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
>>> ->fence_tiling_mode). To make it really clear that it's just about the
>>> global gtt fences and nothing more.
>>
>> I don't really like using ->modifier directly in tiling patch since it is an
>> bag of unrelated stuff, not only a superset. Unrelated especially, but not
>> only, from the point of view of call sites / users.
>>
>> Therefore I see some design elegance in extracting the tiling, or any other
>> logical group of modifiers before hand.
>>
>> At the very least would call something like intel_fb_modifier_to_tiling(),
>> but, it is very ugly to have a dynamic cost at every call site. Which is
>> another reason why I preferred to extract the data before hand.
>
> The reason is that the current tiling_mode enum is userspace ABI, and
> it's just for how to fence global gtt mappings. That's the point of
> splitting the fb modifiers out like in this rfc.
>
> So if you add your fancy new tiling mode you can't do that, since you
> can't extend the tiling_mode enum. Adding another enum also seems a bit

Why not? It is not changing the ABI since obj->tiling_mode stays exactly 
the same as it is today.

Do you worry about leaking new data out in i915_drm.h, under the 
I915_TILING_* #defines? I don't see that we have to change that at all.

> too much when we already have fb_modifiers.
>
> And if fb_modifiers get too complicated we can add helper functions which
> normalize stuff, e.g. extract just the base tiling mode and remove other
> things (like compression mode or whatever it's going to be).

So you are strongly for "looking into a bag of stuff" to see if anything 
interesting is there on every call site?

Helper functions in my view only marginally help there - they make the 
code neater but design is conceptually still untidy. And you add 
pointless processing on every call site.

I just don't see what is the problem with extracting the interesting 
data "from the bag" at fb init time. If you tried to make some 
synchronization argument in the other reply I don't get it.

fb->modifier[0] should be, in my opinion, viewed as immutable. And it 
lives at the base class level while in intel_frambuffer sub-class it 
should be just fine to "parse" that into directly usable data stored at 
the sub-class level.

Regards,

Tvrtko
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Daniel Vetter]

On Mon, Feb 02, 2015 at 05:30:36PM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 05:15 PM, Daniel Vetter wrote:
> >On Mon, Feb 02, 2015 at 10:36:30AM +0000, Tvrtko Ursulin wrote:
> >>
> >>On 02/02/2015 09:54 AM, Daniel Vetter wrote:
> >>>On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
> >>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>
> >>>>Use the fb modifier if it was specified over object tiling mode.
> >>>>
> >>>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>---
> >>>>  drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
> >>>>  1 file changed, 33 insertions(+), 7 deletions(-)
> >>>>
> >>>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>>index e22afbe..ca69da0 100644
> >>>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>>@@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> >>>>  	.create_handle = intel_user_framebuffer_create_handle,
> >>>>  };
> >>>>
> >>>>+static unsigned int
> >>>>+intel_fb_modifier_to_tiling(u64 modifier)
> >>>>+{
> >>>>+	switch (modifier) {
> >>>>+	case I915_FORMAT_MOD_X_TILED:
> >>>>+		return I915_TILING_X;
> >>>>+	default:
> >>>>+	case I915_FORMAT_MOD_NONE:
> >>>>+		break;
> >>>>+	}
> >>>>+
> >>>>+	return I915_TILING_NONE;
> >>>>+}
> >>>>+
> >>>>  static int intel_framebuffer_init(struct drm_device *dev,
> >>>>  				  struct intel_framebuffer *intel_fb,
> >>>>  				  struct drm_mode_fb_cmd2 *mode_cmd,
> >>>>@@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
> >>>>  {
> >>>>  	int aligned_height;
> >>>>  	int pitch_limit;
> >>>>+	unsigned int tiling_mode = obj->tiling_mode;
> >>>>  	int ret;
> >>>>
> >>>>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> >>>>
> >>>>-	if (obj->tiling_mode == I915_TILING_Y) {
> >>>>+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
> >>>>+		tiling_mode =
> >>>>+			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
> >>>>+		if (tiling_mode != obj->tiling_mode &&
> >>>>+			obj->tiling_mode != I915_TILING_NONE) {
> >>>>+			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
> >>>>+					tiling_mode, obj->tiling_mode);
> >>>>+			return -EINVAL;
> >>>>+		}
> >>>>+	}
> >>>
> >>>Ah, here comes the magic. I think this might be simpler if we just use
> >>>->modifier (and fix it up if FB_MODIFIERS isn't set).
> >>>
> >>>Btw another reason for this split is that this way we have a clear
> >>>separation between the tiling modes supported generally (as fb modifiers)
> >>>and the tiling modes supported by fences. It might therefore make sense to
> >>>rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
> >>>->fence_tiling_mode). To make it really clear that it's just about the
> >>>global gtt fences and nothing more.
> >>
> >>I don't really like using ->modifier directly in tiling patch since it is an
> >>bag of unrelated stuff, not only a superset. Unrelated especially, but not
> >>only, from the point of view of call sites / users.
> >>
> >>Therefore I see some design elegance in extracting the tiling, or any other
> >>logical group of modifiers before hand.
> >>
> >>At the very least would call something like intel_fb_modifier_to_tiling(),
> >>but, it is very ugly to have a dynamic cost at every call site. Which is
> >>another reason why I preferred to extract the data before hand.
> >
> >The reason is that the current tiling_mode enum is userspace ABI, and
> >it's just for how to fence global gtt mappings. That's the point of
> >splitting the fb modifiers out like in this rfc.
> >
> >So if you add your fancy new tiling mode you can't do that, since you
> >can't extend the tiling_mode enum. Adding another enum also seems a bit
> 
> Why not? It is not changing the ABI since obj->tiling_mode stays exactly the
> same as it is today.
> 
> Do you worry about leaking new data out in i915_drm.h, under the
> I915_TILING_* #defines? I don't see that we have to change that at all.

I prefer to keep enums for different types of values separate to avoid
confusion.

> >too much when we already have fb_modifiers.
> >
> >And if fb_modifiers get too complicated we can add helper functions which
> >normalize stuff, e.g. extract just the base tiling mode and remove other
> >things (like compression mode or whatever it's going to be).
> 
> So you are strongly for "looking into a bag of stuff" to see if anything
> interesting is there on every call site?
> 
> Helper functions in my view only marginally help there - they make the code
> neater but design is conceptually still untidy. And you add pointless
> processing on every call site.
> 
> I just don't see what is the problem with extracting the interesting data
> "from the bag" at fb init time. If you tried to make some synchronization
> argument in the other reply I don't get it.

So afaik at most we'll get a few more bits for compression, perhaps
swizzling (although that's dead on gen8+), whatelse. If we lay out the
defines in the intel vendor modifier space we can get at that by simple
masking. Also, kms operations are done at about 60fps rate, so computation
overhead is totally irrelevant (well as long as we just waste a few
cycles).

The synchronization argument is that any kind of duplicated data will get
out of sync sooner or later in my experience. We can't smash everything
into obj->tiling with the addfb2.5 abi (and because they're also for
different things), but we can avoid duplicating information between
fb->modifier and intel_fb->tiling_mode by not having the second.

Yes that means we need to fix up ->modifier (which your patches dont do).
But sooner or later someone will look at ->modifier and not ->tiling_mode
(because hey it worked on new userspace) and then *boom* we have a nice
confusing regression report from someone. Or someone looks at
obj->tiling_mode instead of intel_fb->tiling_mode (hey it works, because
they're using the same enum values) until the newfangled tiling thing
shows up.

> fb->modifier[0] should be, in my opinion, viewed as immutable. And it lives
> at the base class level while in intel_frambuffer sub-class it should be
> just fine to "parse" that into directly usable data stored at the sub-class
> level.

Fully agreed on immutable, but that doesn't exclude computing an
appropriate value at fb init time.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Tvrtko Ursulin]

On 02/02/2015 08:17 PM, Daniel Vetter wrote:
> On Mon, Feb 02, 2015 at 05:30:36PM +0000, Tvrtko Ursulin wrote:
>>
>> On 02/02/2015 05:15 PM, Daniel Vetter wrote:
>>> On Mon, Feb 02, 2015 at 10:36:30AM +0000, Tvrtko Ursulin wrote:
>>>>
>>>> On 02/02/2015 09:54 AM, Daniel Vetter wrote:
>>>>> On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>>
>>>>>> Use the fb modifier if it was specified over object tiling mode.
>>>>>>
>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> ---
>>>>>>   drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
>>>>>>   1 file changed, 33 insertions(+), 7 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>>>> index e22afbe..ca69da0 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>>> @@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
>>>>>>   	.create_handle = intel_user_framebuffer_create_handle,
>>>>>>   };
>>>>>>
>>>>>> +static unsigned int
>>>>>> +intel_fb_modifier_to_tiling(u64 modifier)
>>>>>> +{
>>>>>> +	switch (modifier) {
>>>>>> +	case I915_FORMAT_MOD_X_TILED:
>>>>>> +		return I915_TILING_X;
>>>>>> +	default:
>>>>>> +	case I915_FORMAT_MOD_NONE:
>>>>>> +		break;
>>>>>> +	}
>>>>>> +
>>>>>> +	return I915_TILING_NONE;
>>>>>> +}
>>>>>> +
>>>>>>   static int intel_framebuffer_init(struct drm_device *dev,
>>>>>>   				  struct intel_framebuffer *intel_fb,
>>>>>>   				  struct drm_mode_fb_cmd2 *mode_cmd,
>>>>>> @@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
>>>>>>   {
>>>>>>   	int aligned_height;
>>>>>>   	int pitch_limit;
>>>>>> +	unsigned int tiling_mode = obj->tiling_mode;
>>>>>>   	int ret;
>>>>>>
>>>>>>   	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>>>>>>
>>>>>> -	if (obj->tiling_mode == I915_TILING_Y) {
>>>>>> +	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
>>>>>> +		tiling_mode =
>>>>>> +			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
>>>>>> +		if (tiling_mode != obj->tiling_mode &&
>>>>>> +			obj->tiling_mode != I915_TILING_NONE) {
>>>>>> +			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
>>>>>> +					tiling_mode, obj->tiling_mode);
>>>>>> +			return -EINVAL;
>>>>>> +		}
>>>>>> +	}
>>>>>
>>>>> Ah, here comes the magic. I think this might be simpler if we just use
>>>>> ->modifier (and fix it up if FB_MODIFIERS isn't set).
>>>>>
>>>>> Btw another reason for this split is that this way we have a clear
>>>>> separation between the tiling modes supported generally (as fb modifiers)
>>>>> and the tiling modes supported by fences. It might therefore make sense to
>>>>> rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
>>>>> ->fence_tiling_mode). To make it really clear that it's just about the
>>>>> global gtt fences and nothing more.
>>>>
>>>> I don't really like using ->modifier directly in tiling patch since it is an
>>>> bag of unrelated stuff, not only a superset. Unrelated especially, but not
>>>> only, from the point of view of call sites / users.
>>>>
>>>> Therefore I see some design elegance in extracting the tiling, or any other
>>>> logical group of modifiers before hand.
>>>>
>>>> At the very least would call something like intel_fb_modifier_to_tiling(),
>>>> but, it is very ugly to have a dynamic cost at every call site. Which is
>>>> another reason why I preferred to extract the data before hand.
>>>
>>> The reason is that the current tiling_mode enum is userspace ABI, and
>>> it's just for how to fence global gtt mappings. That's the point of
>>> splitting the fb modifiers out like in this rfc.
>>>
>>> So if you add your fancy new tiling mode you can't do that, since you
>>> can't extend the tiling_mode enum. Adding another enum also seems a bit
>>
>> Why not? It is not changing the ABI since obj->tiling_mode stays exactly the
>> same as it is today.
>>
>> Do you worry about leaking new data out in i915_drm.h, under the
>> I915_TILING_* #defines? I don't see that we have to change that at all.
>
> I prefer to keep enums for different types of values separate to avoid
> confusion.
>
>>> too much when we already have fb_modifiers.
>>>
>>> And if fb_modifiers get too complicated we can add helper functions which
>>> normalize stuff, e.g. extract just the base tiling mode and remove other
>>> things (like compression mode or whatever it's going to be).
>>
>> So you are strongly for "looking into a bag of stuff" to see if anything
>> interesting is there on every call site?
>>
>> Helper functions in my view only marginally help there - they make the code
>> neater but design is conceptually still untidy. And you add pointless
>> processing on every call site.
>>
>> I just don't see what is the problem with extracting the interesting data
>> "from the bag" at fb init time. If you tried to make some synchronization
>> argument in the other reply I don't get it.
>
> So afaik at most we'll get a few more bits for compression, perhaps
> swizzling (although that's dead on gen8+), whatelse. If we lay out the
> defines in the intel vendor modifier space we can get at that by simple
> masking. Also, kms operations are done at about 60fps rate, so computation
> overhead is totally irrelevant (well as long as we just waste a few
> cycles).
>
> The synchronization argument is that any kind of duplicated data will get
> out of sync sooner or later in my experience. We can't smash everything
> into obj->tiling with the addfb2.5 abi (and because they're also for
> different things), but we can avoid duplicating information between
> fb->modifier and intel_fb->tiling_mode by not having the second.
 >
> Yes that means we need to fix up ->modifier (which your patches dont do).
> But sooner or later someone will look at ->modifier and not ->tiling_mode
> (because hey it worked on new userspace) and then *boom* we have a nice
> confusing regression report from someone. Or someone looks at
> obj->tiling_mode instead of intel_fb->tiling_mode (hey it works, because
> they're using the same enum values) until the newfangled tiling thing
> shows up.
>
>> fb->modifier[0] should be, in my opinion, viewed as immutable. And it lives
>> at the base class level while in intel_frambuffer sub-class it should be
>> just fine to "parse" that into directly usable data stored at the sub-class
>> level.
>
> Fully agreed on immutable, but that doesn't exclude computing an
> appropriate value at fb init time.

So you want to carefully lay out our fb modifiers so we can get our data 
out easily rather than extract the data at fb creation and have no such 
constraints?

Or in other words you want to reserve some bits for tiling and define a 
mask straight away, did I get that right? Not like this:

1.

intel_fb creation
    -> parse fb modifier and extract private attributes for future use
       -> tiling_mode
       -> compression_mode (eg.)
       -> swizzling_mode (eg.)

tiling_mode use sites
    -> just use intel_fb->tiling_mode

But like this:

2.

intel_fb creation
    -> do nothing

call sites
    -> extract tiling_mode from fb modifier

* Note this still needs to map to same "enum" space as today at least in 
places which program the hardware.

You want option 2, correct?

Regards,

Tvrtko
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Re: [RFC 5/6] drm/i915: Allow fb modifier to set framebuffer tiling

[Daniel Vetter]

On Tue, Feb 03, 2015 at 10:41:49AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/02/2015 08:17 PM, Daniel Vetter wrote:
> >On Mon, Feb 02, 2015 at 05:30:36PM +0000, Tvrtko Ursulin wrote:
> >>
> >>On 02/02/2015 05:15 PM, Daniel Vetter wrote:
> >>>On Mon, Feb 02, 2015 at 10:36:30AM +0000, Tvrtko Ursulin wrote:
> >>>>
> >>>>On 02/02/2015 09:54 AM, Daniel Vetter wrote:
> >>>>>On Fri, Jan 30, 2015 at 05:36:57PM +0000, Tvrtko Ursulin wrote:
> >>>>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>>>
> >>>>>>Use the fb modifier if it was specified over object tiling mode.
> >>>>>>
> >>>>>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>>>---
> >>>>>>  drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++++++++++++++-------
> >>>>>>  1 file changed, 33 insertions(+), 7 deletions(-)
> >>>>>>
> >>>>>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>>>>index e22afbe..ca69da0 100644
> >>>>>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>>>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>>>>@@ -12671,6 +12671,20 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> >>>>>>  	.create_handle = intel_user_framebuffer_create_handle,
> >>>>>>  };
> >>>>>>
> >>>>>>+static unsigned int
> >>>>>>+intel_fb_modifier_to_tiling(u64 modifier)
> >>>>>>+{
> >>>>>>+	switch (modifier) {
> >>>>>>+	case I915_FORMAT_MOD_X_TILED:
> >>>>>>+		return I915_TILING_X;
> >>>>>>+	default:
> >>>>>>+	case I915_FORMAT_MOD_NONE:
> >>>>>>+		break;
> >>>>>>+	}
> >>>>>>+
> >>>>>>+	return I915_TILING_NONE;
> >>>>>>+}
> >>>>>>+
> >>>>>>  static int intel_framebuffer_init(struct drm_device *dev,
> >>>>>>  				  struct intel_framebuffer *intel_fb,
> >>>>>>  				  struct drm_mode_fb_cmd2 *mode_cmd,
> >>>>>>@@ -12678,11 +12692,23 @@ static int intel_framebuffer_init(struct drm_device *dev,
> >>>>>>  {
> >>>>>>  	int aligned_height;
> >>>>>>  	int pitch_limit;
> >>>>>>+	unsigned int tiling_mode = obj->tiling_mode;
> >>>>>>  	int ret;
> >>>>>>
> >>>>>>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> >>>>>>
> >>>>>>-	if (obj->tiling_mode == I915_TILING_Y) {
> >>>>>>+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
> >>>>>>+		tiling_mode =
> >>>>>>+			intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
> >>>>>>+		if (tiling_mode != obj->tiling_mode &&
> >>>>>>+			obj->tiling_mode != I915_TILING_NONE) {
> >>>>>>+			DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
> >>>>>>+					tiling_mode, obj->tiling_mode);
> >>>>>>+			return -EINVAL;
> >>>>>>+		}
> >>>>>>+	}
> >>>>>
> >>>>>Ah, here comes the magic. I think this might be simpler if we just use
> >>>>>->modifier (and fix it up if FB_MODIFIERS isn't set).
> >>>>>
> >>>>>Btw another reason for this split is that this way we have a clear
> >>>>>separation between the tiling modes supported generally (as fb modifiers)
> >>>>>and the tiling modes supported by fences. It might therefore make sense to
> >>>>>rename obj->tiling_mode with a cocci patch to obj->fencing_mode or
> >>>>>->fence_tiling_mode). To make it really clear that it's just about the
> >>>>>global gtt fences and nothing more.
> >>>>
> >>>>I don't really like using ->modifier directly in tiling patch since it is an
> >>>>bag of unrelated stuff, not only a superset. Unrelated especially, but not
> >>>>only, from the point of view of call sites / users.
> >>>>
> >>>>Therefore I see some design elegance in extracting the tiling, or any other
> >>>>logical group of modifiers before hand.
> >>>>
> >>>>At the very least would call something like intel_fb_modifier_to_tiling(),
> >>>>but, it is very ugly to have a dynamic cost at every call site. Which is
> >>>>another reason why I preferred to extract the data before hand.
> >>>
> >>>The reason is that the current tiling_mode enum is userspace ABI, and
> >>>it's just for how to fence global gtt mappings. That's the point of
> >>>splitting the fb modifiers out like in this rfc.
> >>>
> >>>So if you add your fancy new tiling mode you can't do that, since you
> >>>can't extend the tiling_mode enum. Adding another enum also seems a bit
> >>
> >>Why not? It is not changing the ABI since obj->tiling_mode stays exactly the
> >>same as it is today.
> >>
> >>Do you worry about leaking new data out in i915_drm.h, under the
> >>I915_TILING_* #defines? I don't see that we have to change that at all.
> >
> >I prefer to keep enums for different types of values separate to avoid
> >confusion.
> >
> >>>too much when we already have fb_modifiers.
> >>>
> >>>And if fb_modifiers get too complicated we can add helper functions which
> >>>normalize stuff, e.g. extract just the base tiling mode and remove other
> >>>things (like compression mode or whatever it's going to be).
> >>
> >>So you are strongly for "looking into a bag of stuff" to see if anything
> >>interesting is there on every call site?
> >>
> >>Helper functions in my view only marginally help there - they make the code
> >>neater but design is conceptually still untidy. And you add pointless
> >>processing on every call site.
> >>
> >>I just don't see what is the problem with extracting the interesting data
> >>"from the bag" at fb init time. If you tried to make some synchronization
> >>argument in the other reply I don't get it.
> >
> >So afaik at most we'll get a few more bits for compression, perhaps
> >swizzling (although that's dead on gen8+), whatelse. If we lay out the
> >defines in the intel vendor modifier space we can get at that by simple
> >masking. Also, kms operations are done at about 60fps rate, so computation
> >overhead is totally irrelevant (well as long as we just waste a few
> >cycles).
> >
> >The synchronization argument is that any kind of duplicated data will get
> >out of sync sooner or later in my experience. We can't smash everything
> >into obj->tiling with the addfb2.5 abi (and because they're also for
> >different things), but we can avoid duplicating information between
> >fb->modifier and intel_fb->tiling_mode by not having the second.
> >
> >Yes that means we need to fix up ->modifier (which your patches dont do).
> >But sooner or later someone will look at ->modifier and not ->tiling_mode
> >(because hey it worked on new userspace) and then *boom* we have a nice
> >confusing regression report from someone. Or someone looks at
> >obj->tiling_mode instead of intel_fb->tiling_mode (hey it works, because
> >they're using the same enum values) until the newfangled tiling thing
> >shows up.
> >
> >>fb->modifier[0] should be, in my opinion, viewed as immutable. And it lives
> >>at the base class level while in intel_frambuffer sub-class it should be
> >>just fine to "parse" that into directly usable data stored at the sub-class
> >>level.
> >
> >Fully agreed on immutable, but that doesn't exclude computing an
> >appropriate value at fb init time.
> 
> So you want to carefully lay out our fb modifiers so we can get our data out
> easily rather than extract the data at fb creation and have no such
> constraints?

Not sure it'll be that bad really, often it should look like this I expect
(totally made up example):

	switch(fb->modifier) {
		case MOD_NONE:
			break;
		case MOD_X:
			plane_mode |= TILE_X
			break;
		case MOD_FANCY_TILING_WITH_COMPRESSION:
			plane_mode |= COMPRESSED;
		case MOD_FANCY_TILING:
			plane_mode |= TILE_FANCY;
			break;
		default:
			/* this plane doesn't support any other
			 * combination */
			MISSING_CASE(fb->modifier);
	}

So not even sure we'd need to split stuff up that badly and make it all
maskable. In any case 56 bits gives us a lot of places for submasks, I
don't think that's a severe restriction really.

> Or in other words you want to reserve some bits for tiling and define a mask
> straight away, did I get that right? Not like this:
> 
> 1.
> 
> intel_fb creation
>    -> parse fb modifier and extract private attributes for future use
>       -> tiling_mode
>       -> compression_mode (eg.)
>       -> swizzling_mode (eg.)
> 
> tiling_mode use sites
>    -> just use intel_fb->tiling_mode
> 
> But like this:
> 
> 2.
> 
> intel_fb creation
>    -> do nothing

s/do nothing/fixup fb modifier for legacy userspace not using it/

> call sites
>    -> extract tiling_mode from fb modifier
> 
> * Note this still needs to map to same "enum" space as today at least in
> places which program the hardware.
> 
> You want option 2, correct?

Yes, I think that overall has less opportunities for accidental bugs.
-Daniel
-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[RFC 6/6] drm/i915: Announce support for framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Let the DRM core know we can handle it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ca69da0..1a8d433 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13202,6 +13202,8 @@ void intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
 
+	dev->mode_config.allow_fb_modifiers = 1;
+
 	dev->mode_config.funcs = &intel_mode_funcs;
 
 	intel_init_quirks(dev);
-- 
2.2.2

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Re: [RFC 6/6] drm/i915: Announce support for framebuffer modifiers

[Daniel Vetter]

On Fri, Jan 30, 2015 at 05:36:58PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Let the DRM core know we can handle it.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ca69da0..1a8d433 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13202,6 +13202,8 @@ void intel_modeset_init(struct drm_device *dev)
>  	dev->mode_config.preferred_depth = 24;
>  	dev->mode_config.prefer_shadow = 1;
>  
> +	dev->mode_config.allow_fb_modifiers = 1;

Bikeshed: s/1/true/ (and perhaps do that for prefer_shadow too in a
trivial patch ...).
-Daniel

> +
>  	dev->mode_config.funcs = &intel_mode_funcs;
>  
>  	intel_init_quirks(dev);
> -- 
> 2.2.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[RFC v2 0/4] Use framebuffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Instead of using driver private set tiling ioctl, use the proposed addfb2 ioctl
extension to tell the driver about display buffer special formatting.

Lightly tested only with a hacked up igt/testdisplay.

v2:
   * Refactor the series to use fb->modifier[0] directly at call sites
     interested in tiling. (Daniel Vetter)

Rob Clark (1):
  RFC: drm: add support for tiled/compressed/etc modifier in addfb2

Tvrtko Ursulin (3):
  drm/i915: Add tiled framebuffer modifiers
  drm/i915: Use frame buffer modifiers for tiled display
  drm/i915: Announce support for framebuffer modifiers

 drivers/gpu/drm/drm_crtc.c           | 14 +++++-
 drivers/gpu/drm/drm_crtc_helper.c    |  1 +
 drivers/gpu/drm/drm_ioctl.c          |  3 ++
 drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +
 drivers/gpu/drm/i915/intel_pm.c      |  7 +--
 drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
 include/drm/drm_crtc.h               |  4 ++
 include/uapi/drm/drm.h               |  1 +
 include/uapi/drm/drm_fourcc.h        | 32 ++++++++++++
 include/uapi/drm/drm_mode.h          |  9 ++++
 include/uapi/drm/i915_drm.h          | 13 +++++
 12 files changed, 163 insertions(+), 46 deletions(-)

-- 
2.2.2

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[PATCH 1/4] RFC: drm: add support for tiled/compressed/etc modifier in addfb2

[Tvrtko Ursulin]

From: Rob Clark <robdclark@gmail.com>

In DRM/KMS we are lacking a good way to deal with tiled/compressed
formats.  Especially in the case of dmabuf/prime buffer sharing, where
we cannot always rely on under-the-hood flags passed to driver specific
gem-create ioctl to pass around these extra flags.

The proposal is to add a per-plane format modifier.  This allows to, if
necessary, use different tiling patters for sub-sampled planes, etc.
The format modifiers are added at the end of the ioctl struct, so for
legacy userspace it will be zero padded.

v1: original
v1.5: increase modifier to 64b

v2: Incorporate review comments from the big thread, plus a few more.

- Add a getcap so that userspace doesn't have to jump through hoops.
- Allow modifiers only when a flag is set. That way drivers know when
  they're dealing with old userspace and need to fish out e.g. tiling
  from other information.
- After rolling out checks for ->modifier to all drivers I've decided
  that this is way too fragile and needs an explicit opt-in flag. So
  do that instead.
- Add a define (just for documentation really) for the "NONE"
  modifier. Imo we don't need to add mask #defines since drivers
  really should only do exact matches against values defined with
  fourcc_mod_code.
- Drop the Samsung tiling modifier on Rob's request since he's not yet
  sure whether that one is accurate.

v3:
- Also add a new ->modifier[] array to struct drm_framebuffer and fill
  it in drm_helper_mode_fill_fb_struct. Requested by Tvrkto Uruslin.
- Remove TODO in comment and add code comment that modifiers should be
  properly documented, requested by Rob.

Cc: Rob Clark <robdclark@gmail.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Rob Clark <robdclark@gmail.com> (v1.5)
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/drm_crtc.c        | 14 +++++++++++++-
 drivers/gpu/drm/drm_crtc_helper.c |  1 +
 drivers/gpu/drm/drm_ioctl.c       |  3 +++
 include/drm/drm_crtc.h            |  4 ++++
 include/uapi/drm/drm.h            |  1 +
 include/uapi/drm/drm_fourcc.h     | 32 ++++++++++++++++++++++++++++++++
 include/uapi/drm/drm_mode.h       |  9 +++++++++
 7 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6b00173..e6e2de3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3261,6 +3261,12 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
 			DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i);
 			return -EINVAL;
 		}
+
+		if (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) {
+			DRM_DEBUG_KMS("bad fb modifier %llu for plane %d\n",
+				      r->modifier[i], i);
+			return -EINVAL;
+		}
 	}
 
 	return 0;
@@ -3274,7 +3280,7 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 	struct drm_framebuffer *fb;
 	int ret;
 
-	if (r->flags & ~DRM_MODE_FB_INTERLACED) {
+	if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
 		DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
 		return ERR_PTR(-EINVAL);
 	}
@@ -3290,6 +3296,12 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 		return ERR_PTR(-EINVAL);
 	}
 
+	if (r->flags & DRM_MODE_FB_MODIFIERS &&
+	    !dev->mode_config.allow_fb_modifiers) {
+		DRM_DEBUG_KMS("driver does not support fb modifiers\n");
+		return ERR_PTR(-EINVAL);
+	}
+
 	ret = framebuffer_check(r);
 	if (ret)
 		return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index b1979e7..3053aab 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -837,6 +837,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
 	for (i = 0; i < 4; i++) {
 		fb->pitches[i] = mode_cmd->pitches[i];
 		fb->offsets[i] = mode_cmd->offsets[i];
+		fb->modifier[i] = mode_cmd->modifier[i];
 	}
 	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
 				    &fb->bits_per_pixel);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 3785d66..a6d773a 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -321,6 +321,9 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
 		else
 			req->value = 64;
 		break;
+	case DRM_CAP_ADDFB2_MODIFIERS:
+		req->value = dev->mode_config.allow_fb_modifiers;
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 920e21a..b1465d6 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -202,6 +202,7 @@ struct drm_framebuffer {
 	const struct drm_framebuffer_funcs *funcs;
 	unsigned int pitches[4];
 	unsigned int offsets[4];
+	uint64_t modifier[4];
 	unsigned int width;
 	unsigned int height;
 	/* depth can be 15 or 16 */
@@ -1155,6 +1156,9 @@ struct drm_mode_config {
 	/* whether async page flip is supported or not */
 	bool async_page_flip;
 
+	/* whether the driver supports fb modifiers */
+	bool allow_fb_modifiers;
+
 	/* cursor size */
 	uint32_t cursor_width, cursor_height;
 };
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 01b2d6d..ff6ef62 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -630,6 +630,7 @@ struct drm_gem_open {
  */
 #define DRM_CAP_CURSOR_WIDTH		0x8
 #define DRM_CAP_CURSOR_HEIGHT		0x9
+#define DRM_CAP_ADDFB2_MODIFIERS	0x10
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 646ae5f..6221096 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -132,4 +132,36 @@
 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
 
+
+/*
+ * Format Modifiers:
+ *
+ * Format modifiers describe, typically, a re-ordering or modification
+ * of the data in a plane of an FB.  This can be used to express tiled/
+ * swizzled formats, or compression, or a combination of the two.
+ *
+ * The upper 8 bits of the format modifier are a vendor-id as assigned
+ * below.  The lower 56 bits are assigned as vendor sees fit.
+ */
+
+/* Vendor Ids: */
+#define DRM_FORMAT_MOD_NONE           0
+#define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
+#define DRM_FORMAT_MOD_VENDOR_AMD     0x02
+#define DRM_FORMAT_MOD_VENDOR_NV      0x03
+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
+#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
+/* add more to the end as needed */
+
+#define fourcc_mod_code(vendor, val) \
+	((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffL))
+
+/*
+ * Format Modifier tokens:
+ *
+ * When adding a new token please document the layout with a code comment,
+ * similar to the fourcc codes above. drm_fourcc.h is considered the
+ * authoritative source for all of these.
+ */
+
 #endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index ca788e0..dbeba94 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -336,6 +336,7 @@ struct drm_mode_fb_cmd {
 };
 
 #define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
+#define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer[] */
 
 struct drm_mode_fb_cmd2 {
 	__u32 fb_id;
@@ -356,10 +357,18 @@ struct drm_mode_fb_cmd2 {
 	 * So it would consist of Y as offsets[0] and UV as
 	 * offsets[1].  Note that offsets[0] will generally
 	 * be 0 (but this is not required).
+	 *
+	 * To accommodate tiled, compressed, etc formats, a per-plane
+	 * modifier can be specified.  The default value of zero
+	 * indicates "native" format as specified by the fourcc.
+	 * Vendor specific modifier token.  This allows, for example,
+	 * different tiling/swizzling pattern on different planes.
+	 * See discussion above of DRM_FORMAT_MOD_xxx.
 	 */
 	__u32 handles[4];
 	__u32 pitches[4]; /* pitch for each plane */
 	__u32 offsets[4]; /* offset of each plane */
+	__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
 };
 
 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
-- 
2.2.2

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[PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

To be used from the new addfb2 extension.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/uapi/drm/i915_drm.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6eed16b..a7327fd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -28,6 +28,7 @@
 #define _UAPI_I915_DRM_H_
 
 #include <drm/drm.h>
+#include <uapi/drm/drm_fourcc.h>
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
@@ -1101,4 +1102,16 @@ struct drm_i915_gem_context_param {
 	__u64 value;
 };
 
+/** @{
+ * Intel framebuffer modifiers
+ *
+ * Tiling modes supported by the display hardware
+ * to be passed in via the DRM addfb2 ioctl.
+ */
+/** None */
+#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
+/** X tiling */
+#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
+/** @} */
+
 #endif /* _UAPI_I915_DRM_H_ */
-- 
2.2.2

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[PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using frame buffer modifiers instead of object tiling mode
for display purposes.

To ensure compatibility with old userspace which is using set_tiling
and does not know about frame buffer modifiers, the latter are faked
internally when tile object is set for display. This way all interested
call sites can use fb modifiers exclusively.

Also ensure tiling specified via fb modifiers must match object tiling
used for fencing if both are specified.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +
 drivers/gpu/drm/i915/intel_pm.c      |  7 +--
 drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
 4 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7a3ed61..6825016 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
 	return ALIGN(height, tile_height);
 }
 
+static unsigned int intel_fb_modifier_to_tiling(u64 mod)
+{
+	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
+		     I915_TILING_X);
+
+	return mod & 1;
+}
+
+unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
+{
+	return intel_fb_modifier_to_tiling(fb->modifier[0]);
+}
+
 int
 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			   struct drm_framebuffer *fb,
@@ -2211,7 +2224,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	switch (obj->tiling_mode) {
+	switch (intel_fb_tiling_mode(fb)) {
 	case I915_TILING_NONE:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
@@ -2447,7 +2460,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 			continue;
 
 		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
-			if (obj->tiling_mode != I915_TILING_NONE)
+			if (intel_fb_tiling_mode(c->primary->fb) !=
+			    I915_TILING_NONE)
 				dev_priv->preserve_bios_swizzle = true;
 
 			drm_framebuffer_reference(c->primary->fb);
@@ -2471,6 +2485,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2542,8 +2557,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4 &&
-	    obj->tiling_mode != I915_TILING_NONE)
+	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
@@ -2553,7 +2567,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2603,6 +2617,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2651,7 +2666,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -2659,7 +2674,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
@@ -2747,7 +2762,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	switch (obj->tiling_mode) {
+	switch (intel_fb_tiling_mode(fb)) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -9288,7 +9303,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	intel_ring_emit(ring, fb->pitches[0]);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
-			obj->tiling_mode);
+			intel_fb_tiling_mode(fb));
 
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
@@ -9321,7 +9336,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP |
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+	intel_ring_emit(ring, fb->pitches[0] | intel_fb_tiling_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	/* Contrary to the suggestions in the documentation,
@@ -9425,7 +9440,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	}
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+	intel_ring_emit(ring, (fb->pitches[0] | intel_fb_tiling_mode(fb)));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
@@ -9466,14 +9481,13 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	const enum pipe pipe = intel_crtc->pipe;
 	u32 ctl, stride;
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	ctl = I915_READ(PLANE_CTL(pipe, 0));
 	ctl &= ~PLANE_CTL_TILED_MASK;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_TILING_X)
 		ctl |= PLANE_CTL_TILED_X;
 
 	/*
@@ -9481,7 +9495,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	stride = fb->pitches[0] >> 6;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_TILING_X)
 		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
 
 	/*
@@ -9499,16 +9513,14 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_framebuffer *intel_fb =
-		to_intel_framebuffer(intel_crtc->base.primary->fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
+	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
 	u32 dspcntr;
 	u32 reg;
 
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (intel_fb_tiling_mode(fb) != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
@@ -9591,6 +9603,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t plane = 0, stride;
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 	int ret;
 
 	switch(intel_crtc->pipe) {
@@ -9608,7 +9621,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 		return -ENODEV;
 	}
 
-	switch (obj->tiling_mode) {
+	switch (tiling_mode) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -9636,7 +9649,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, 0);
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
+	intel_ring_emit(ring, stride << 6 | tiling_mode);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	intel_mark_page_flip_active(intel_crtc);
@@ -9811,7 +9824,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
+		if (intel_fb_tiling_mode(fb) !=
+		    intel_fb_tiling_mode(work->old_fb))
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			ring = NULL;
 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -12187,7 +12201,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
+	    intel_fb_tiling_mode(fb)) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		ret = -EINVAL;
 	}
@@ -12668,6 +12683,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 {
 	int aligned_height;
 	int pitch_limit;
+	unsigned int tiling_mode = I915_TILING_NONE;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -12677,6 +12693,29 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 	}
 
+	/* If obj is tiled and fb modifier not set propagate it in
+	 * for backward compatibility with old userspace.
+	 */
+	if (obj->tiling_mode && !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
+		tiling_mode = obj->tiling_mode;
+		mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
+	}
+
+	/* Get tiling mode from fb modifier if set. */
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS)
+		tiling_mode = intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
+
+	/* Ensure new userspace is using the interface correctly by only
+	 * allowing old usage of set_tiling if it matches with the
+	 * fb modifier tiling.
+	 */
+	if (obj->tiling_mode != I915_TILING_NONE &&
+	    obj->tiling_mode != tiling_mode) {
+		DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
+				tiling_mode, obj->tiling_mode);
+		return -EINVAL;
+	}
+
 	if (mode_cmd->pitches[0] & 63) {
 		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
 			  mode_cmd->pitches[0]);
@@ -12686,12 +12725,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 16*1024;
 		else
 			pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 3) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 8*1024;
 		else
 			pitch_limit = 16*1024;
@@ -12701,12 +12740,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-			  obj->tiling_mode ? "tiled" : "linear",
+			  tiling_mode ? "tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE &&
+	if (tiling_mode != I915_TILING_NONE && obj->stride &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
@@ -12761,7 +12800,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-					       obj->tiling_mode);
+					       tiling_mode);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f048f8b..b40dad8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1008,6 +1008,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
+unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb);
+
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ece663..de9e433 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1182,12 +1182,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
 	if (IS_I915GM(dev) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->primary->fb);
-
 		/* self-refresh seems busted with untiled */
-		if (obj->tiling_mode == I915_TILING_NONE)
+		if (intel_fb_tiling_mode(enabled->primary->fb) ==
+		    I915_TILING_NONE)
 			enabled = NULL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44..8f89766 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -245,7 +245,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
-	switch (obj->tiling_mode) {
+	switch (intel_fb_tiling_mode(fb)) {
 	case I915_TILING_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
@@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 
@@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SP_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		sprctl |= SP_TILED;
 
 	sprctl |= SP_ENABLE;
@@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
-							obj->tiling_mode,
+							tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	u32 sprctl, sprscale = 0;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPRCTL(pipe));
 
@@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		sprctl |= SPRITE_TILED;
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 * register */
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-	else if (obj->tiling_mode != I915_TILING_NONE)
+	else if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	unsigned long dvssurf_offset, linear_offset;
 	u32 dvscntr, dvsscale;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
 
 	dvscntr = I915_READ(DVSCNTR(pipe));
 
@@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	dvscntr |= DVS_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		dvscntr |= DVS_TILED;
 
 	if (IS_GEN6(dev))
@@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
@@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_TILING_NONE)
 		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(DVSLINOFF(pipe), linear_offset);
@@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int crtc_x, crtc_y;
 	unsigned int crtc_w, crtc_h;
 	uint32_t src_x, src_y, src_w, src_h;
@@ -1107,7 +1109,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	}
 
 	/* Sprite planes can be linear or x-tiled surfaces */
-	switch (obj->tiling_mode) {
+	switch (intel_fb_tiling_mode(fb)) {
 		case I915_TILING_NONE:
 		case I915_TILING_X:
 			break;
-- 
2.2.2

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Daniel Vetter]

On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Start using frame buffer modifiers instead of object tiling mode
> for display purposes.
> 
> To ensure compatibility with old userspace which is using set_tiling
> and does not know about frame buffer modifiers, the latter are faked
> internally when tile object is set for display. This way all interested
> call sites can use fb modifiers exclusively.
> 
> Also ensure tiling specified via fb modifiers must match object tiling
> used for fencing if both are specified.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
>  drivers/gpu/drm/i915/intel_pm.c      |  7 +--
>  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
>  4 files changed, 85 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7a3ed61..6825016 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
>  	return ALIGN(height, tile_height);
>  }
>  
> +static unsigned int intel_fb_modifier_to_tiling(u64 mod)
> +{
> +	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
> +		     I915_TILING_X);
> +
> +	return mod & 1;
> +}
> +
> +unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
> +{
> +	return intel_fb_modifier_to_tiling(fb->modifier[0]);
> +}

I expect that these here will create a bit of churn with the skl patches
you have based, since I really don't want a new I915_TILING_FANCY define
in the enum space used by obj->tiling mode. But makes sense for backwards
compat with older platforms and less churn in code.

With igt for the new cases in addfb and review this is imo good to get in.
-Daniel

> +
>  int
>  intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>  			   struct drm_framebuffer *fb,
> @@ -2211,7 +2224,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
>  
>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>  
> -	switch (obj->tiling_mode) {
> +	switch (intel_fb_tiling_mode(fb)) {
>  	case I915_TILING_NONE:
>  		if (INTEL_INFO(dev)->gen >= 9)
>  			alignment = 256 * 1024;
> @@ -2447,7 +2460,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
>  			continue;
>  
>  		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
> -			if (obj->tiling_mode != I915_TILING_NONE)
> +			if (intel_fb_tiling_mode(c->primary->fb) !=
> +			    I915_TILING_NONE)
>  				dev_priv->preserve_bios_swizzle = true;
>  
>  			drm_framebuffer_reference(c->primary->fb);
> @@ -2471,6 +2485,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	u32 dspcntr;
>  	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	if (!intel_crtc->primary_enabled) {
>  		I915_WRITE(reg, 0);
> @@ -2542,8 +2557,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (INTEL_INFO(dev)->gen >= 4 &&
> -	    obj->tiling_mode != I915_TILING_NONE)
> +	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  
>  	if (IS_G4X(dev))
> @@ -2553,7 +2567,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		intel_crtc->dspaddr_offset =
> -			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +			intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  						       pixel_size,
>  						       fb->pitches[0]);
>  		linear_offset -= intel_crtc->dspaddr_offset;
> @@ -2603,6 +2617,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	u32 dspcntr;
>  	u32 reg = DSPCNTR(plane);
>  	int pixel_size;
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	if (!intel_crtc->primary_enabled) {
>  		I915_WRITE(reg, 0);
> @@ -2651,7 +2666,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  
>  	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> @@ -2659,7 +2674,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	intel_crtc->dspaddr_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  					       pixel_size,
>  					       fb->pitches[0]);
>  	linear_offset -= intel_crtc->dspaddr_offset;
> @@ -2747,7 +2762,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>  	 * The stride is either expressed as a multiple of 64 bytes chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	switch (obj->tiling_mode) {
> +	switch (intel_fb_tiling_mode(fb)) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -9288,7 +9303,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
>  			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
>  	intel_ring_emit(ring, fb->pitches[0]);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
> -			obj->tiling_mode);
> +			intel_fb_tiling_mode(fb));
>  
>  	/* XXX Enabling the panel-fitter across page-flip is so far
>  	 * untested on non-native modes, so ignore it for now.
> @@ -9321,7 +9336,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP |
>  			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
> -	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
> +	intel_ring_emit(ring, fb->pitches[0] | intel_fb_tiling_mode(fb));
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  
>  	/* Contrary to the suggestions in the documentation,
> @@ -9425,7 +9440,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
>  	}
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
> -	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
> +	intel_ring_emit(ring, (fb->pitches[0] | intel_fb_tiling_mode(fb)));
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  	intel_ring_emit(ring, (MI_NOOP));
>  
> @@ -9466,14 +9481,13 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
> -	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	struct drm_i915_gem_object *obj = intel_fb->obj;
>  	const enum pipe pipe = intel_crtc->pipe;
>  	u32 ctl, stride;
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	ctl = I915_READ(PLANE_CTL(pipe, 0));
>  	ctl &= ~PLANE_CTL_TILED_MASK;
> -	if (obj->tiling_mode == I915_TILING_X)
> +	if (tiling_mode == I915_TILING_X)
>  		ctl |= PLANE_CTL_TILED_X;
>  
>  	/*
> @@ -9481,7 +9495,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
>  	stride = fb->pitches[0] >> 6;
> -	if (obj->tiling_mode == I915_TILING_X)
> +	if (tiling_mode == I915_TILING_X)
>  		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
>  
>  	/*
> @@ -9499,16 +9513,14 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_framebuffer *intel_fb =
> -		to_intel_framebuffer(intel_crtc->base.primary->fb);
> -	struct drm_i915_gem_object *obj = intel_fb->obj;
> +	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
>  	u32 dspcntr;
>  	u32 reg;
>  
>  	reg = DSPCNTR(intel_crtc->plane);
>  	dspcntr = I915_READ(reg);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (intel_fb_tiling_mode(fb) != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
>  	else
>  		dspcntr &= ~DISPPLANE_TILED;
> @@ -9591,6 +9603,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  {
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	uint32_t plane = 0, stride;
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  	int ret;
>  
>  	switch(intel_crtc->pipe) {
> @@ -9608,7 +9621,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  		return -ENODEV;
>  	}
>  
> -	switch (obj->tiling_mode) {
> +	switch (tiling_mode) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -9636,7 +9649,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
>  	intel_ring_emit(ring, 0);
>  
>  	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
> -	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
> +	intel_ring_emit(ring, stride << 6 | tiling_mode);
>  	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
>  
>  	intel_mark_page_flip_active(intel_crtc);
> @@ -9811,7 +9824,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		ring = &dev_priv->ring[BCS];
> -		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
> +		if (intel_fb_tiling_mode(fb) !=
> +		    intel_fb_tiling_mode(work->old_fb))
>  			/* vlv: DISPLAY_FLIP fails to change tiling */
>  			ring = NULL;
>  	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> @@ -12187,7 +12201,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
>  
>  	/* we only need to pin inside GTT if cursor is non-phy */
>  	mutex_lock(&dev->struct_mutex);
> -	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
> +	if (!INTEL_INFO(dev)->cursor_needs_physical &&
> +	    intel_fb_tiling_mode(fb)) {
>  		DRM_DEBUG_KMS("cursor cannot be tiled\n");
>  		ret = -EINVAL;
>  	}
> @@ -12668,6 +12683,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  {
>  	int aligned_height;
>  	int pitch_limit;
> +	unsigned int tiling_mode = I915_TILING_NONE;
>  	int ret;
>  
>  	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> @@ -12677,6 +12693,29 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		return -EINVAL;
>  	}
>  
> +	/* If obj is tiled and fb modifier not set propagate it in
> +	 * for backward compatibility with old userspace.
> +	 */
> +	if (obj->tiling_mode && !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
> +		tiling_mode = obj->tiling_mode;
> +		mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
> +	}
> +
> +	/* Get tiling mode from fb modifier if set. */
> +	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS)
> +		tiling_mode = intel_fb_modifier_to_tiling(mode_cmd->modifier[0]);
> +
> +	/* Ensure new userspace is using the interface correctly by only
> +	 * allowing old usage of set_tiling if it matches with the
> +	 * fb modifier tiling.
> +	 */
> +	if (obj->tiling_mode != I915_TILING_NONE &&
> +	    obj->tiling_mode != tiling_mode) {
> +		DRM_ERROR("Tiling modifier mismatch %u vs obj %u!\n",
> +				tiling_mode, obj->tiling_mode);
> +		return -EINVAL;
> +	}
> +
>  	if (mode_cmd->pitches[0] & 63) {
>  		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
>  			  mode_cmd->pitches[0]);
> @@ -12686,12 +12725,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
>  		pitch_limit = 32*1024;
>  	} else if (INTEL_INFO(dev)->gen >= 4) {
> -		if (obj->tiling_mode)
> +		if (tiling_mode)
>  			pitch_limit = 16*1024;
>  		else
>  			pitch_limit = 32*1024;
>  	} else if (INTEL_INFO(dev)->gen >= 3) {
> -		if (obj->tiling_mode)
> +		if (tiling_mode)
>  			pitch_limit = 8*1024;
>  		else
>  			pitch_limit = 16*1024;
> @@ -12701,12 +12740,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  
>  	if (mode_cmd->pitches[0] > pitch_limit) {
>  		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
> -			  obj->tiling_mode ? "tiled" : "linear",
> +			  tiling_mode ? "tiled" : "linear",
>  			  mode_cmd->pitches[0], pitch_limit);
>  		return -EINVAL;
>  	}
>  
> -	if (obj->tiling_mode != I915_TILING_NONE &&
> +	if (tiling_mode != I915_TILING_NONE && obj->stride &&
>  	    mode_cmd->pitches[0] != obj->stride) {
>  		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
>  			  mode_cmd->pitches[0], obj->stride);
> @@ -12761,7 +12800,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  		return -EINVAL;
>  
>  	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
> -					       obj->tiling_mode);
> +					       tiling_mode);
>  	/* FIXME drm helper for size checks (especially planar formats)? */
>  	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f048f8b..b40dad8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1008,6 +1008,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>  void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
>  void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
>  
> +unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb);
> +
>  /* intel_dp.c */
>  void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
>  bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6ece663..de9e433 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1182,12 +1182,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>  	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
>  
>  	if (IS_I915GM(dev) && enabled) {
> -		struct drm_i915_gem_object *obj;
> -
> -		obj = intel_fb_obj(enabled->primary->fb);
> -
>  		/* self-refresh seems busted with untiled */
> -		if (obj->tiling_mode == I915_TILING_NONE)
> +		if (intel_fb_tiling_mode(enabled->primary->fb) ==
> +		    I915_TILING_NONE)
>  			enabled = NULL;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0a52c44..8f89766 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -245,7 +245,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	switch (obj->tiling_mode) {
> +	switch (intel_fb_tiling_mode(fb)) {
>  	case I915_TILING_NONE:
>  		stride = fb->pitches[0] >> 6;
>  		break;
> @@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	u32 sprctl;
>  	unsigned long sprsurf_offset, linear_offset;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	sprctl = I915_READ(SPCNTR(pipe, plane));
>  
> @@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	 */
>  	sprctl |= SP_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		sprctl |= SP_TILED;
>  
>  	sprctl |= SP_ENABLE;
> @@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
> -							obj->tiling_mode,
> +							tiling_mode,
>  							pixel_size,
>  							fb->pitches[0]);
>  	linear_offset -= sprsurf_offset;
> @@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>  	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
>  	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
>  	else
>  		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
> @@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	u32 sprctl, sprscale = 0;
>  	unsigned long sprsurf_offset, linear_offset;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	sprctl = I915_READ(SPRCTL(pipe));
>  
> @@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 */
>  	sprctl |= SPRITE_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		sprctl |= SPRITE_TILED;
>  
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> @@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	sprsurf_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  					       pixel_size, fb->pitches[0]);
>  	linear_offset -= sprsurf_offset;
>  
> @@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 * register */
>  	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
> -	else if (obj->tiling_mode != I915_TILING_NONE)
> +	else if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
>  	else
>  		I915_WRITE(SPRLINOFF(pipe), linear_offset);
> @@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	unsigned long dvssurf_offset, linear_offset;
>  	u32 dvscntr, dvsscale;
>  	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> +	unsigned int tiling_mode = intel_fb_tiling_mode(fb);
>  
>  	dvscntr = I915_READ(DVSCNTR(pipe));
>  
> @@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	 */
>  	dvscntr |= DVS_GAMMA_ENABLE;
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		dvscntr |= DVS_TILED;
>  
>  	if (IS_GEN6(dev))
> @@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	linear_offset = y * fb->pitches[0] + x * pixel_size;
>  	dvssurf_offset =
> -		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> +		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
>  					       pixel_size, fb->pitches[0]);
>  	linear_offset -= dvssurf_offset;
>  
> @@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
>  	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
>  
> -	if (obj->tiling_mode != I915_TILING_NONE)
> +	if (tiling_mode != I915_TILING_NONE)
>  		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
>  	else
>  		I915_WRITE(DVSLINOFF(pipe), linear_offset);
> @@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
>  	struct intel_plane *intel_plane = to_intel_plane(plane);
>  	struct drm_framebuffer *fb = state->base.fb;
> -	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	int crtc_x, crtc_y;
>  	unsigned int crtc_w, crtc_h;
>  	uint32_t src_x, src_y, src_w, src_h;
> @@ -1107,7 +1109,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>  	}
>  
>  	/* Sprite planes can be linear or x-tiled surfaces */
> -	switch (obj->tiling_mode) {
> +	switch (intel_fb_tiling_mode(fb)) {
>  		case I915_TILING_NONE:
>  		case I915_TILING_X:
>  			break;
> -- 
> 2.2.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

On 02/03/2015 07:47 PM, Daniel Vetter wrote:
> On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Start using frame buffer modifiers instead of object tiling mode
>> for display purposes.
>>
>> To ensure compatibility with old userspace which is using set_tiling
>> and does not know about frame buffer modifiers, the latter are faked
>> internally when tile object is set for display. This way all interested
>> call sites can use fb modifiers exclusively.
>>
>> Also ensure tiling specified via fb modifiers must match object tiling
>> used for fencing if both are specified.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
>>   drivers/gpu/drm/i915/intel_drv.h     |  2 +
>>   drivers/gpu/drm/i915/intel_pm.c      |  7 +--
>>   drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
>>   4 files changed, 85 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 7a3ed61..6825016 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
>>   	return ALIGN(height, tile_height);
>>   }
>>
>> +static unsigned int intel_fb_modifier_to_tiling(u64 mod)
>> +{
>> +	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
>> +		     I915_TILING_X);
>> +
>> +	return mod & 1;
>> +}
>> +
>> +unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
>> +{
>> +	return intel_fb_modifier_to_tiling(fb->modifier[0]);
>> +}
>
> I expect that these here will create a bit of churn with the skl patches
> you have based, since I really don't want a new I915_TILING_FANCY define
> in the enum space used by obj->tiling mode. But makes sense for backwards
> compat with older platforms and less churn in code.

I thought we talked about effectively creating a new enum space for fb 
tiling? By masking out bits from the fb modifier, no? Only thing for 
backward compatibility is that object X tiling and fb X tiling == 1.

> With igt for the new cases in addfb and review this is imo good to get in.

I can do the IGT, but who is doing the libdrm part? :)

Regards,

Tvrtko
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Daniel Vetter]

On Wed, Feb 04, 2015 at 10:01:45AM +0000, Tvrtko Ursulin wrote:
> 
> On 02/03/2015 07:47 PM, Daniel Vetter wrote:
> >On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >>Start using frame buffer modifiers instead of object tiling mode
> >>for display purposes.
> >>
> >>To ensure compatibility with old userspace which is using set_tiling
> >>and does not know about frame buffer modifiers, the latter are faked
> >>internally when tile object is set for display. This way all interested
> >>call sites can use fb modifiers exclusively.
> >>
> >>Also ensure tiling specified via fb modifiers must match object tiling
> >>used for fencing if both are specified.
> >>
> >>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
> >>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
> >>  drivers/gpu/drm/i915/intel_pm.c      |  7 +--
> >>  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
> >>  4 files changed, 85 insertions(+), 45 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>index 7a3ed61..6825016 100644
> >>--- a/drivers/gpu/drm/i915/intel_display.c
> >>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>@@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
> >>  	return ALIGN(height, tile_height);
> >>  }
> >>
> >>+static unsigned int intel_fb_modifier_to_tiling(u64 mod)
> >>+{
> >>+	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
> >>+		     I915_TILING_X);
> >>+
> >>+	return mod & 1;
> >>+}
> >>+
> >>+unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
> >>+{
> >>+	return intel_fb_modifier_to_tiling(fb->modifier[0]);
> >>+}
> >
> >I expect that these here will create a bit of churn with the skl patches
> >you have based, since I really don't want a new I915_TILING_FANCY define
> >in the enum space used by obj->tiling mode. But makes sense for backwards
> >compat with older platforms and less churn in code.
> 
> I thought we talked about effectively creating a new enum space for fb
> tiling? By masking out bits from the fb modifier, no? Only thing for
> backward compatibility is that object X tiling and fb X tiling == 1.

intel_fb_tiling_mode maps modifier (the new enum space) to
obj->tiling_mode (the old enum space). Means a notch less churn in legacy
code (but if that's the metric I'd just have kept using obj->tiling_mode
there). But means that you get to chance skl code twice, because I very
much don't want a new I915_TILING_DEFINE but instead the skl code should
check the new modifiers directly. Otherwise we can mash up tiling modes
valid just for ggtt fencing and fb modifiers in general.

Maybe I wasn't really clear with what I've meant ...

> >With igt for the new cases in addfb and review this is imo good to get in.
> 
> I can do the IGT, but who is doing the libdrm part? :)

Generally when we do igts for new interfaces we just copypaste the new
struct definitions with local_ prefixed to avoid blocking the test on a
new libdrm release. So no one needs to do a libdrm patch ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

On 02/04/2015 02:25 PM, Daniel Vetter wrote:
> On Wed, Feb 04, 2015 at 10:01:45AM +0000, Tvrtko Ursulin wrote:
>>
>> On 02/03/2015 07:47 PM, Daniel Vetter wrote:
>>> On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Start using frame buffer modifiers instead of object tiling mode
>>>> for display purposes.
>>>>
>>>> To ensure compatibility with old userspace which is using set_tiling
>>>> and does not know about frame buffer modifiers, the latter are faked
>>>> internally when tile object is set for display. This way all interested
>>>> call sites can use fb modifiers exclusively.
>>>>
>>>> Also ensure tiling specified via fb modifiers must match object tiling
>>>> used for fencing if both are specified.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
>>>>   drivers/gpu/drm/i915/intel_drv.h     |  2 +
>>>>   drivers/gpu/drm/i915/intel_pm.c      |  7 +--
>>>>   drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
>>>>   4 files changed, 85 insertions(+), 45 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>> index 7a3ed61..6825016 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
>>>>   	return ALIGN(height, tile_height);
>>>>   }
>>>>
>>>> +static unsigned int intel_fb_modifier_to_tiling(u64 mod)
>>>> +{
>>>> +	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
>>>> +		     I915_TILING_X);
>>>> +
>>>> +	return mod & 1;
>>>> +}
>>>> +
>>>> +unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
>>>> +{
>>>> +	return intel_fb_modifier_to_tiling(fb->modifier[0]);
>>>> +}
>>>
>>> I expect that these here will create a bit of churn with the skl patches
>>> you have based, since I really don't want a new I915_TILING_FANCY define
>>> in the enum space used by obj->tiling mode. But makes sense for backwards
>>> compat with older platforms and less churn in code.
>>
>> I thought we talked about effectively creating a new enum space for fb
>> tiling? By masking out bits from the fb modifier, no? Only thing for
>> backward compatibility is that object X tiling and fb X tiling == 1.
>
> intel_fb_tiling_mode maps modifier (the new enum space) to
> obj->tiling_mode (the old enum space). Means a notch less churn in legacy
> code (but if that's the metric I'd just have kept using obj->tiling_mode
> there). But means that you get to chance skl code twice, because I very
> much don't want a new I915_TILING_DEFINE but instead the skl code should
> check the new modifiers directly. Otherwise we can mash up tiling modes
> valid just for ggtt fencing and fb modifiers in general.
>
> Maybe I wasn't really clear with what I've meant ...

It does seem it is taking very long to get on the same page here. :/

I did not plan to add new I915_TILING_xxx. I was exploiting the fact 
both map to the same value, with masking. So legacy continues to work 
since this will be true forever. (ABI)

Then the plan was to add a new namespace for display tiling enums.

This was since fb modifier could contain more than tiling and this way 
it is possible to mask out and case-switch just as the current code does.

There are three namespaces here:

1. I915_TILING_xxx
2. I915_FORMAT_MOD_ (fb modifiers)
3. Tiling as programmed to display hardware

And then add a fourth one:

4. I915_DISPLAY_TILING_xxx

At this step also add something like I915_FORMAT_MOD_TILING_MASK and 
redefine I915_FORMAT_MOD_X_TILE to be fourcc_mod(INTEL, 
I915_DISPLAY_TILING_X). (Instead of hardcoded 1)

At call sites (opencoded):

switch (fb->modifier[0] & I915_FORMAT_MOD_TILING) {
case I915_DISPLAY_TILING_X:
...

I mean we could do:

switch (fb->modifier[0]) {
case I915_FORMAT_MOD_X_TILE:
...

If fb modifiers won't have any overlap, like for example:

#define I915_FORMAT_MOD_X_TILE fourcc_mod(INTEL, 1)
#define I915_FORMAT_MOD_X_TILE_AND_UNRELATED fourcc_mod(INTEL, 1<<8 && 1)

Then the direct usage stops working..

Up to you, I have to unblock other stuff so we can't strangle this for 
too long.

>>> With igt for the new cases in addfb and review this is imo good to get in.
>>
>> I can do the IGT, but who is doing the libdrm part? :)
>
> Generally when we do igts for new interfaces we just copypaste the new
> struct definitions with local_ prefixed to avoid blocking the test on a
> new libdrm release. So no one needs to do a libdrm patch ;-)

Okay I can do that. Even better that's what I already did. :)

Regards,

Tvrtko
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Daniel Vetter]

On Wed, Feb 04, 2015 at 03:09:38PM +0000, Tvrtko Ursulin wrote:
> On 02/04/2015 02:25 PM, Daniel Vetter wrote:
> >On Wed, Feb 04, 2015 at 10:01:45AM +0000, Tvrtko Ursulin wrote:
> >>
> >>On 02/03/2015 07:47 PM, Daniel Vetter wrote:
> >>>On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
> >>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>
> >>>>Start using frame buffer modifiers instead of object tiling mode
> >>>>for display purposes.
> >>>>
> >>>>To ensure compatibility with old userspace which is using set_tiling
> >>>>and does not know about frame buffer modifiers, the latter are faked
> >>>>internally when tile object is set for display. This way all interested
> >>>>call sites can use fb modifiers exclusively.
> >>>>
> >>>>Also ensure tiling specified via fb modifiers must match object tiling
> >>>>used for fencing if both are specified.
> >>>>
> >>>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>---
> >>>>  drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
> >>>>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
> >>>>  drivers/gpu/drm/i915/intel_pm.c      |  7 +--
> >>>>  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
> >>>>  4 files changed, 85 insertions(+), 45 deletions(-)
> >>>>
> >>>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>>index 7a3ed61..6825016 100644
> >>>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>>@@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
> >>>>  	return ALIGN(height, tile_height);
> >>>>  }
> >>>>
> >>>>+static unsigned int intel_fb_modifier_to_tiling(u64 mod)
> >>>>+{
> >>>>+	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
> >>>>+		     I915_TILING_X);
> >>>>+
> >>>>+	return mod & 1;
> >>>>+}
> >>>>+
> >>>>+unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
> >>>>+{
> >>>>+	return intel_fb_modifier_to_tiling(fb->modifier[0]);
> >>>>+}
> >>>
> >>>I expect that these here will create a bit of churn with the skl patches
> >>>you have based, since I really don't want a new I915_TILING_FANCY define
> >>>in the enum space used by obj->tiling mode. But makes sense for backwards
> >>>compat with older platforms and less churn in code.
> >>
> >>I thought we talked about effectively creating a new enum space for fb
> >>tiling? By masking out bits from the fb modifier, no? Only thing for
> >>backward compatibility is that object X tiling and fb X tiling == 1.
> >
> >intel_fb_tiling_mode maps modifier (the new enum space) to
> >obj->tiling_mode (the old enum space). Means a notch less churn in legacy
> >code (but if that's the metric I'd just have kept using obj->tiling_mode
> >there). But means that you get to chance skl code twice, because I very
> >much don't want a new I915_TILING_DEFINE but instead the skl code should
> >check the new modifiers directly. Otherwise we can mash up tiling modes
> >valid just for ggtt fencing and fb modifiers in general.
> >
> >Maybe I wasn't really clear with what I've meant ...
> 
> It does seem it is taking very long to get on the same page here. :/
> 
> I did not plan to add new I915_TILING_xxx. I was exploiting the fact both
> map to the same value, with masking. So legacy continues to work since this
> will be true forever. (ABI)
> 
> Then the plan was to add a new namespace for display tiling enums.
> 
> This was since fb modifier could contain more than tiling and this way it is
> possible to mask out and case-switch just as the current code does.
> 
> There are three namespaces here:
> 
> 1. I915_TILING_xxx
> 2. I915_FORMAT_MOD_ (fb modifiers)
> 3. Tiling as programmed to display hardware
> 
> And then add a fourth one:
> 
> 4. I915_DISPLAY_TILING_xxx
> 
> At this step also add something like I915_FORMAT_MOD_TILING_MASK and
> redefine I915_FORMAT_MOD_X_TILE to be fourcc_mod(INTEL,
> I915_DISPLAY_TILING_X). (Instead of hardcoded 1)
> 
> At call sites (opencoded):
> 
> switch (fb->modifier[0] & I915_FORMAT_MOD_TILING) {
> case I915_DISPLAY_TILING_X:

This is kinda what I'd have done, expect that you can cleverly define the
mask to include the vendor prefix, i.e.

#define I915_FORMAT_MOD_TILING_MASK ((0xff << 56) | 0xff)

and then you don't need yet another set of defines. And still have the
clear separation between I915_TILING_FOO and the new fb modifier stuff.

> ...
> 
> I mean we could do:
> 
> switch (fb->modifier[0]) {
> case I915_FORMAT_MOD_X_TILE:

Or this. Since we don't yet have anything else than tiling modes you'll
get away with it and can postpone the mask stuff to whomever ends up
implementing the non-tiling fb modifiers.

> ...
> 
> If fb modifiers won't have any overlap, like for example:
> 
> #define I915_FORMAT_MOD_X_TILE fourcc_mod(INTEL, 1)
> #define I915_FORMAT_MOD_X_TILE_AND_UNRELATED fourcc_mod(INTEL, 1<<8 && 1)
> 
> Then the direct usage stops working..
> 
> Up to you, I have to unblock other stuff so we can't strangle this for too
> long.

The super-minimal approach would be to shrink this patch down to the
fixup/check code in framebuffer_init and then move the conversion for skl
display code (and just that) into the next series which adds the fancy skl
patches. And use one of the switch statements above to decode the fb
modifier. Goes well with my default stance of "in case of doubt, pick less
churn".

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

On 02/04/2015 03:33 PM, Daniel Vetter wrote:
> On Wed, Feb 04, 2015 at 03:09:38PM +0000, Tvrtko Ursulin wrote:
>> On 02/04/2015 02:25 PM, Daniel Vetter wrote:
>>> On Wed, Feb 04, 2015 at 10:01:45AM +0000, Tvrtko Ursulin wrote:
>>>>
>>>> On 02/03/2015 07:47 PM, Daniel Vetter wrote:
>>>>> On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>>
>>>>>> Start using frame buffer modifiers instead of object tiling mode
>>>>>> for display purposes.
>>>>>>
>>>>>> To ensure compatibility with old userspace which is using set_tiling
>>>>>> and does not know about frame buffer modifiers, the latter are faked
>>>>>> internally when tile object is set for display. This way all interested
>>>>>> call sites can use fb modifiers exclusively.
>>>>>>
>>>>>> Also ensure tiling specified via fb modifiers must match object tiling
>>>>>> used for fencing if both are specified.
>>>>>>
>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> ---
>>>>>>   drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
>>>>>>   drivers/gpu/drm/i915/intel_drv.h     |  2 +
>>>>>>   drivers/gpu/drm/i915/intel_pm.c      |  7 +--
>>>>>>   drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
>>>>>>   4 files changed, 85 insertions(+), 45 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>>>> index 7a3ed61..6825016 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>>> @@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
>>>>>>   	return ALIGN(height, tile_height);
>>>>>>   }
>>>>>>
>>>>>> +static unsigned int intel_fb_modifier_to_tiling(u64 mod)
>>>>>> +{
>>>>>> +	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
>>>>>> +		     I915_TILING_X);
>>>>>> +
>>>>>> +	return mod & 1;
>>>>>> +}
>>>>>> +
>>>>>> +unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
>>>>>> +{
>>>>>> +	return intel_fb_modifier_to_tiling(fb->modifier[0]);
>>>>>> +}
>>>>>
>>>>> I expect that these here will create a bit of churn with the skl patches
>>>>> you have based, since I really don't want a new I915_TILING_FANCY define
>>>>> in the enum space used by obj->tiling mode. But makes sense for backwards
>>>>> compat with older platforms and less churn in code.
>>>>
>>>> I thought we talked about effectively creating a new enum space for fb
>>>> tiling? By masking out bits from the fb modifier, no? Only thing for
>>>> backward compatibility is that object X tiling and fb X tiling == 1.
>>>
>>> intel_fb_tiling_mode maps modifier (the new enum space) to
>>> obj->tiling_mode (the old enum space). Means a notch less churn in legacy
>>> code (but if that's the metric I'd just have kept using obj->tiling_mode
>>> there). But means that you get to chance skl code twice, because I very
>>> much don't want a new I915_TILING_DEFINE but instead the skl code should
>>> check the new modifiers directly. Otherwise we can mash up tiling modes
>>> valid just for ggtt fencing and fb modifiers in general.
>>>
>>> Maybe I wasn't really clear with what I've meant ...
>>
>> It does seem it is taking very long to get on the same page here. :/
>>
>> I did not plan to add new I915_TILING_xxx. I was exploiting the fact both
>> map to the same value, with masking. So legacy continues to work since this
>> will be true forever. (ABI)
>>
>> Then the plan was to add a new namespace for display tiling enums.
>>
>> This was since fb modifier could contain more than tiling and this way it is
>> possible to mask out and case-switch just as the current code does.
>>
>> There are three namespaces here:
>>
>> 1. I915_TILING_xxx
>> 2. I915_FORMAT_MOD_ (fb modifiers)
>> 3. Tiling as programmed to display hardware
>>
>> And then add a fourth one:
>>
>> 4. I915_DISPLAY_TILING_xxx
>>
>> At this step also add something like I915_FORMAT_MOD_TILING_MASK and
>> redefine I915_FORMAT_MOD_X_TILE to be fourcc_mod(INTEL,
>> I915_DISPLAY_TILING_X). (Instead of hardcoded 1)
>>
>> At call sites (opencoded):
>>
>> switch (fb->modifier[0] & I915_FORMAT_MOD_TILING) {
>> case I915_DISPLAY_TILING_X:
>
> This is kinda what I'd have done, expect that you can cleverly define the
> mask to include the vendor prefix, i.e.
>
> #define I915_FORMAT_MOD_TILING_MASK ((0xff << 56) | 0xff)
>
> and then you don't need yet another set of defines. And still have the
> clear separation between I915_TILING_FOO and the new fb modifier stuff.

Hm side question - maybe DRM patch could instead of allow_fb_modifiers 
boolean take allow_fb_modifier = VENDORA | VENDORB, and then stem at the 
source any attempts to pass unsupported ones to the driver. :)

>> ...
>>
>> I mean we could do:
>>
>> switch (fb->modifier[0]) {
>> case I915_FORMAT_MOD_X_TILE:
>
> Or this. Since we don't yet have anything else than tiling modes you'll
> get away with it and can postpone the mask stuff to whomever ends up
> implementing the non-tiling fb modifiers.

Not nice but you told me to do it. :D

>> ...
>>
>> If fb modifiers won't have any overlap, like for example:
>>
>> #define I915_FORMAT_MOD_X_TILE fourcc_mod(INTEL, 1)
>> #define I915_FORMAT_MOD_X_TILE_AND_UNRELATED fourcc_mod(INTEL, 1<<8 && 1)
>>
>> Then the direct usage stops working..
>>
>> Up to you, I have to unblock other stuff so we can't strangle this for too
>> long.
>
> The super-minimal approach would be to shrink this patch down to the
> fixup/check code in framebuffer_init and then move the conversion for skl
> display code (and just that) into the next series which adds the fancy skl
> patches. And use one of the switch statements above to decode the fb
> modifier. Goes well with my default stance of "in case of doubt, pick less
> churn".

Disallow fb modifiers on gen < 9 regardless of DRM_CAP? Sounds nasty..

Regards,

Tvrtko
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Re: [PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Daniel Vetter]

On Wed, Feb 04, 2015 at 03:44:58PM +0000, Tvrtko Ursulin wrote:
> 
> On 02/04/2015 03:33 PM, Daniel Vetter wrote:
> >On Wed, Feb 04, 2015 at 03:09:38PM +0000, Tvrtko Ursulin wrote:
> >>On 02/04/2015 02:25 PM, Daniel Vetter wrote:
> >>>On Wed, Feb 04, 2015 at 10:01:45AM +0000, Tvrtko Ursulin wrote:
> >>>>
> >>>>On 02/03/2015 07:47 PM, Daniel Vetter wrote:
> >>>>>On Tue, Feb 03, 2015 at 05:22:31PM +0000, Tvrtko Ursulin wrote:
> >>>>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>>>
> >>>>>>Start using frame buffer modifiers instead of object tiling mode
> >>>>>>for display purposes.
> >>>>>>
> >>>>>>To ensure compatibility with old userspace which is using set_tiling
> >>>>>>and does not know about frame buffer modifiers, the latter are faked
> >>>>>>internally when tile object is set for display. This way all interested
> >>>>>>call sites can use fb modifiers exclusively.
> >>>>>>
> >>>>>>Also ensure tiling specified via fb modifiers must match object tiling
> >>>>>>used for fencing if both are specified.
> >>>>>>
> >>>>>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>>>---
> >>>>>>  drivers/gpu/drm/i915/intel_display.c | 95 +++++++++++++++++++++++++-----------
> >>>>>>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
> >>>>>>  drivers/gpu/drm/i915/intel_pm.c      |  7 +--
> >>>>>>  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++-----
> >>>>>>  4 files changed, 85 insertions(+), 45 deletions(-)
> >>>>>>
> >>>>>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>>>>index 7a3ed61..6825016 100644
> >>>>>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>>>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>>>>@@ -2198,6 +2198,19 @@ intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
> >>>>>>  	return ALIGN(height, tile_height);
> >>>>>>  }
> >>>>>>
> >>>>>>+static unsigned int intel_fb_modifier_to_tiling(u64 mod)
> >>>>>>+{
> >>>>>>+	BUILD_BUG_ON((I915_FORMAT_MOD_X_TILED & 0x00ffffffffffffffL) !=
> >>>>>>+		     I915_TILING_X);
> >>>>>>+
> >>>>>>+	return mod & 1;
> >>>>>>+}
> >>>>>>+
> >>>>>>+unsigned int intel_fb_tiling_mode(struct drm_framebuffer *fb)
> >>>>>>+{
> >>>>>>+	return intel_fb_modifier_to_tiling(fb->modifier[0]);
> >>>>>>+}
> >>>>>
> >>>>>I expect that these here will create a bit of churn with the skl patches
> >>>>>you have based, since I really don't want a new I915_TILING_FANCY define
> >>>>>in the enum space used by obj->tiling mode. But makes sense for backwards
> >>>>>compat with older platforms and less churn in code.
> >>>>
> >>>>I thought we talked about effectively creating a new enum space for fb
> >>>>tiling? By masking out bits from the fb modifier, no? Only thing for
> >>>>backward compatibility is that object X tiling and fb X tiling == 1.
> >>>
> >>>intel_fb_tiling_mode maps modifier (the new enum space) to
> >>>obj->tiling_mode (the old enum space). Means a notch less churn in legacy
> >>>code (but if that's the metric I'd just have kept using obj->tiling_mode
> >>>there). But means that you get to chance skl code twice, because I very
> >>>much don't want a new I915_TILING_DEFINE but instead the skl code should
> >>>check the new modifiers directly. Otherwise we can mash up tiling modes
> >>>valid just for ggtt fencing and fb modifiers in general.
> >>>
> >>>Maybe I wasn't really clear with what I've meant ...
> >>
> >>It does seem it is taking very long to get on the same page here. :/
> >>
> >>I did not plan to add new I915_TILING_xxx. I was exploiting the fact both
> >>map to the same value, with masking. So legacy continues to work since this
> >>will be true forever. (ABI)
> >>
> >>Then the plan was to add a new namespace for display tiling enums.
> >>
> >>This was since fb modifier could contain more than tiling and this way it is
> >>possible to mask out and case-switch just as the current code does.
> >>
> >>There are three namespaces here:
> >>
> >>1. I915_TILING_xxx
> >>2. I915_FORMAT_MOD_ (fb modifiers)
> >>3. Tiling as programmed to display hardware
> >>
> >>And then add a fourth one:
> >>
> >>4. I915_DISPLAY_TILING_xxx
> >>
> >>At this step also add something like I915_FORMAT_MOD_TILING_MASK and
> >>redefine I915_FORMAT_MOD_X_TILE to be fourcc_mod(INTEL,
> >>I915_DISPLAY_TILING_X). (Instead of hardcoded 1)
> >>
> >>At call sites (opencoded):
> >>
> >>switch (fb->modifier[0] & I915_FORMAT_MOD_TILING) {
> >>case I915_DISPLAY_TILING_X:
> >
> >This is kinda what I'd have done, expect that you can cleverly define the
> >mask to include the vendor prefix, i.e.
> >
> >#define I915_FORMAT_MOD_TILING_MASK ((0xff << 56) | 0xff)
> >
> >and then you don't need yet another set of defines. And still have the
> >clear separation between I915_TILING_FOO and the new fb modifier stuff.
> 
> Hm side question - maybe DRM patch could instead of allow_fb_modifiers
> boolean take allow_fb_modifier = VENDORA | VENDORB, and then stem at the
> source any attempts to pass unsupported ones to the driver. :)
> 
> >>...
> >>
> >>I mean we could do:
> >>
> >>switch (fb->modifier[0]) {
> >>case I915_FORMAT_MOD_X_TILE:
> >
> >Or this. Since we don't yet have anything else than tiling modes you'll
> >get away with it and can postpone the mask stuff to whomever ends up
> >implementing the non-tiling fb modifiers.
> 
> Not nice but you told me to do it. :D
> 
> >>...
> >>
> >>If fb modifiers won't have any overlap, like for example:
> >>
> >>#define I915_FORMAT_MOD_X_TILE fourcc_mod(INTEL, 1)
> >>#define I915_FORMAT_MOD_X_TILE_AND_UNRELATED fourcc_mod(INTEL, 1<<8 && 1)
> >>
> >>Then the direct usage stops working..
> >>
> >>Up to you, I have to unblock other stuff so we can't strangle this for too
> >>long.
> >
> >The super-minimal approach would be to shrink this patch down to the
> >fixup/check code in framebuffer_init and then move the conversion for skl
> >display code (and just that) into the next series which adds the fancy skl
> >patches. And use one of the switch statements above to decode the fb
> >modifier. Goes well with my default stance of "in case of doubt, pick less
> >churn".
> 
> Disallow fb modifiers on gen < 9 regardless of DRM_CAP? Sounds nasty..

Nope, we'd allow the in framebuffer_init, but the only thing you can do is
ask for TILE_X, and it must match with obj->tiling. Hm, that gives a
slightly different check than what you have now, but really shouldn't be a
restriction since scanout stuff is always allocated as separate buffers
and userspace does an unconditional set_tiling when using X-tiled.
-Daniel
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[PATCH 4/4] drm/i915: Announce support for framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Let the DRM core know we can handle it.

v2: Change to boolean true. (Daniel Vetter)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6825016..9a99b37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13204,6 +13204,8 @@ void intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
 
+	dev->mode_config.allow_fb_modifiers = true;
+
 	dev->mode_config.funcs = &intel_mode_funcs;
 
 	intel_init_quirks(dev);
-- 
2.2.2

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[RFC v3 0/4] Use framebuffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Instead of using driver private set tiling ioctl, use the proposed addfb2 ioctl
extension to tell the driver about display buffer special formatting.

Lightly tested only with a hacked up igt/testdisplay.

v2:
   * Refactor the series to use fb->modifier[0] directly at call sites
     interested in tiling. (Daniel Vetter)

v3:
   * Completey split obj and fb modifier tiling namespaces.

Rob Clark (1):
  RFC: drm: add support for tiled/compressed/etc modifier in addfb2

Tvrtko Ursulin (3):
  drm/i915: Add tiled framebuffer modifiers
  drm/i915: Use frame buffer modifiers for tiled display
  drm/i915: Announce support for framebuffer modifiers

 drivers/gpu/drm/drm_crtc.c           |  14 +++-
 drivers/gpu/drm/drm_crtc_helper.c    |   1 +
 drivers/gpu/drm/drm_ioctl.c          |   3 +
 drivers/gpu/drm/i915/intel_display.c | 152 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
 drivers/gpu/drm/i915/intel_pm.c      |   7 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  34 ++++----
 include/drm/drm_crtc.h               |   4 +
 include/uapi/drm/drm.h               |   1 +
 include/uapi/drm/drm_fourcc.h        |  32 ++++++++
 include/uapi/drm/drm_mode.h          |   9 +++
 include/uapi/drm/i915_drm.h          |  15 ++++
 12 files changed, 204 insertions(+), 77 deletions(-)

-- 
2.2.2

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[PATCH 1/4] RFC: drm: add support for tiled/compressed/etc modifier in addfb2

[Tvrtko Ursulin]

From: Rob Clark <robdclark@gmail.com>

In DRM/KMS we are lacking a good way to deal with tiled/compressed
formats.  Especially in the case of dmabuf/prime buffer sharing, where
we cannot always rely on under-the-hood flags passed to driver specific
gem-create ioctl to pass around these extra flags.

The proposal is to add a per-plane format modifier.  This allows to, if
necessary, use different tiling patters for sub-sampled planes, etc.
The format modifiers are added at the end of the ioctl struct, so for
legacy userspace it will be zero padded.

v1: original
v1.5: increase modifier to 64b

v2: Incorporate review comments from the big thread, plus a few more.

- Add a getcap so that userspace doesn't have to jump through hoops.
- Allow modifiers only when a flag is set. That way drivers know when
  they're dealing with old userspace and need to fish out e.g. tiling
  from other information.
- After rolling out checks for ->modifier to all drivers I've decided
  that this is way too fragile and needs an explicit opt-in flag. So
  do that instead.
- Add a define (just for documentation really) for the "NONE"
  modifier. Imo we don't need to add mask #defines since drivers
  really should only do exact matches against values defined with
  fourcc_mod_code.
- Drop the Samsung tiling modifier on Rob's request since he's not yet
  sure whether that one is accurate.

v3:
- Also add a new ->modifier[] array to struct drm_framebuffer and fill
  it in drm_helper_mode_fill_fb_struct. Requested by Tvrkto Uruslin.
- Remove TODO in comment and add code comment that modifiers should be
  properly documented, requested by Rob.

Cc: Rob Clark <robdclark@gmail.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Rob Clark <robdclark@gmail.com> (v1.5)
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/drm_crtc.c        | 14 +++++++++++++-
 drivers/gpu/drm/drm_crtc_helper.c |  1 +
 drivers/gpu/drm/drm_ioctl.c       |  3 +++
 include/drm/drm_crtc.h            |  4 ++++
 include/uapi/drm/drm.h            |  1 +
 include/uapi/drm/drm_fourcc.h     | 32 ++++++++++++++++++++++++++++++++
 include/uapi/drm/drm_mode.h       |  9 +++++++++
 7 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6b00173..e6e2de3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3261,6 +3261,12 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
 			DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i);
 			return -EINVAL;
 		}
+
+		if (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) {
+			DRM_DEBUG_KMS("bad fb modifier %llu for plane %d\n",
+				      r->modifier[i], i);
+			return -EINVAL;
+		}
 	}
 
 	return 0;
@@ -3274,7 +3280,7 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 	struct drm_framebuffer *fb;
 	int ret;
 
-	if (r->flags & ~DRM_MODE_FB_INTERLACED) {
+	if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
 		DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
 		return ERR_PTR(-EINVAL);
 	}
@@ -3290,6 +3296,12 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
 		return ERR_PTR(-EINVAL);
 	}
 
+	if (r->flags & DRM_MODE_FB_MODIFIERS &&
+	    !dev->mode_config.allow_fb_modifiers) {
+		DRM_DEBUG_KMS("driver does not support fb modifiers\n");
+		return ERR_PTR(-EINVAL);
+	}
+
 	ret = framebuffer_check(r);
 	if (ret)
 		return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index b1979e7..3053aab 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -837,6 +837,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
 	for (i = 0; i < 4; i++) {
 		fb->pitches[i] = mode_cmd->pitches[i];
 		fb->offsets[i] = mode_cmd->offsets[i];
+		fb->modifier[i] = mode_cmd->modifier[i];
 	}
 	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
 				    &fb->bits_per_pixel);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 3785d66..a6d773a 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -321,6 +321,9 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
 		else
 			req->value = 64;
 		break;
+	case DRM_CAP_ADDFB2_MODIFIERS:
+		req->value = dev->mode_config.allow_fb_modifiers;
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 920e21a..b1465d6 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -202,6 +202,7 @@ struct drm_framebuffer {
 	const struct drm_framebuffer_funcs *funcs;
 	unsigned int pitches[4];
 	unsigned int offsets[4];
+	uint64_t modifier[4];
 	unsigned int width;
 	unsigned int height;
 	/* depth can be 15 or 16 */
@@ -1155,6 +1156,9 @@ struct drm_mode_config {
 	/* whether async page flip is supported or not */
 	bool async_page_flip;
 
+	/* whether the driver supports fb modifiers */
+	bool allow_fb_modifiers;
+
 	/* cursor size */
 	uint32_t cursor_width, cursor_height;
 };
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 01b2d6d..ff6ef62 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -630,6 +630,7 @@ struct drm_gem_open {
  */
 #define DRM_CAP_CURSOR_WIDTH		0x8
 #define DRM_CAP_CURSOR_HEIGHT		0x9
+#define DRM_CAP_ADDFB2_MODIFIERS	0x10
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index a284f11..188e61f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -129,4 +129,36 @@
 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
 
+
+/*
+ * Format Modifiers:
+ *
+ * Format modifiers describe, typically, a re-ordering or modification
+ * of the data in a plane of an FB.  This can be used to express tiled/
+ * swizzled formats, or compression, or a combination of the two.
+ *
+ * The upper 8 bits of the format modifier are a vendor-id as assigned
+ * below.  The lower 56 bits are assigned as vendor sees fit.
+ */
+
+/* Vendor Ids: */
+#define DRM_FORMAT_MOD_NONE           0
+#define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
+#define DRM_FORMAT_MOD_VENDOR_AMD     0x02
+#define DRM_FORMAT_MOD_VENDOR_NV      0x03
+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
+#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
+/* add more to the end as needed */
+
+#define fourcc_mod_code(vendor, val) \
+	((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffL))
+
+/*
+ * Format Modifier tokens:
+ *
+ * When adding a new token please document the layout with a code comment,
+ * similar to the fourcc codes above. drm_fourcc.h is considered the
+ * authoritative source for all of these.
+ */
+
 #endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index ca788e0..dbeba94 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -336,6 +336,7 @@ struct drm_mode_fb_cmd {
 };
 
 #define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */
+#define DRM_MODE_FB_MODIFIERS	(1<<1) /* enables ->modifer[] */
 
 struct drm_mode_fb_cmd2 {
 	__u32 fb_id;
@@ -356,10 +357,18 @@ struct drm_mode_fb_cmd2 {
 	 * So it would consist of Y as offsets[0] and UV as
 	 * offsets[1].  Note that offsets[0] will generally
 	 * be 0 (but this is not required).
+	 *
+	 * To accommodate tiled, compressed, etc formats, a per-plane
+	 * modifier can be specified.  The default value of zero
+	 * indicates "native" format as specified by the fourcc.
+	 * Vendor specific modifier token.  This allows, for example,
+	 * different tiling/swizzling pattern on different planes.
+	 * See discussion above of DRM_FORMAT_MOD_xxx.
 	 */
 	__u32 handles[4];
 	__u32 pitches[4]; /* pitch for each plane */
 	__u32 offsets[4]; /* offset of each plane */
+	__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
 };
 
 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
-- 
2.2.2

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Re: [PATCH 1/4] RFC: drm: add support for tiled/compressed/etc modifier in addfb2

[Daniel Stone]

On 5 February 2015 at 14:41, Tvrtko Ursulin
<tvrtko.ursulin@linux.intel.com> wrote:
> In DRM/KMS we are lacking a good way to deal with tiled/compressed
> formats.  Especially in the case of dmabuf/prime buffer sharing, where
> we cannot always rely on under-the-hood flags passed to driver specific
> gem-create ioctl to pass around these extra flags.
>
> The proposal is to add a per-plane format modifier.  This allows to, if
> necessary, use different tiling patters for sub-sampled planes, etc.
> The format modifiers are added at the end of the ioctl struct, so for
> legacy userspace it will be zero padded.

Reviewed-by: Daniel Stone <daniels@collabora.com>
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[PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

To be used from the new addfb2 extension.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/uapi/drm/i915_drm.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6eed16b..e4c09e2 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -28,6 +28,7 @@
 #define _UAPI_I915_DRM_H_
 
 #include <drm/drm.h>
+#include <uapi/drm/drm_fourcc.h>
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
@@ -1101,4 +1102,18 @@ struct drm_i915_gem_context_param {
 	__u64 value;
 };
 
+/** @{
+ * Intel framebuffer modifiers
+ *
+ * Tiling modes supported by the display hardware
+ * to be passed in via the DRM addfb2 ioctl.
+ */
+/** Bits reserved for tiling */
+#define I915_FORMAT_MOD_TILING_MASK fourcc_mod_code(INTEL, 0xff)
+/** None */
+#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
+/** X tiling */
+#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
+/** @} */
+
 #endif /* _UAPI_I915_DRM_H_ */
-- 
2.2.2

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Re: [PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Thu, Feb 05, 2015 at 02:41:53PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> To be used from the new addfb2 extension.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  include/uapi/drm/i915_drm.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6eed16b..e4c09e2 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -28,6 +28,7 @@
>  #define _UAPI_I915_DRM_H_
>  
>  #include <drm/drm.h>
> +#include <uapi/drm/drm_fourcc.h>
>  
>  /* Please note that modifications to all structs defined here are
>   * subject to backwards-compatibility constraints.
> @@ -1101,4 +1102,18 @@ struct drm_i915_gem_context_param {
>  	__u64 value;
>  };
>  
> +/** @{
> + * Intel framebuffer modifiers
> + *
> + * Tiling modes supported by the display hardware
> + * to be passed in via the DRM addfb2 ioctl.
> + */
> +/** Bits reserved for tiling */
> +#define I915_FORMAT_MOD_TILING_MASK fourcc_mod_code(INTEL, 0xff)
> +/** None */
> +#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)
> +/** X tiling */
> +#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
> +/** @} */

These must be in drm_fourcc.h, adn ** @{ isn't how kerneldoc works. I've
fixed this up plus add a bit of wording to make it clearer what these are.

Btw for the new tiling modes I think we should fully spec out the layout,
as Rob suggested.
-Daniel

> +
>  #endif /* _UAPI_I915_DRM_H_ */
> -- 
> 2.2.2
> 
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Re: [PATCH 2/4] drm/i915: Add tiled framebuffer modifiers

[Daniel Vetter]

On Thu, Feb 05, 2015 at 02:41:53PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> To be used from the new addfb2 extension.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  include/uapi/drm/i915_drm.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6eed16b..e4c09e2 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -28,6 +28,7 @@
>  #define _UAPI_I915_DRM_H_
>  
>  #include <drm/drm.h>
> +#include <uapi/drm/drm_fourcc.h>
>  
>  /* Please note that modifications to all structs defined here are
>   * subject to backwards-compatibility constraints.
> @@ -1101,4 +1102,18 @@ struct drm_i915_gem_context_param {
>  	__u64 value;
>  };
>  
> +/** @{
> + * Intel framebuffer modifiers
> + *
> + * Tiling modes supported by the display hardware
> + * to be passed in via the DRM addfb2 ioctl.
> + */
> +/** Bits reserved for tiling */
> +#define I915_FORMAT_MOD_TILING_MASK fourcc_mod_code(INTEL, 0xff)
> +/** None */
> +#define I915_FORMAT_MOD_NONE	fourcc_mod_code(INTEL, 0x00000000000000L)

And we don't need an intel specific version for untiled either.
-Daniel

> +/** X tiling */
> +#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 0x00000000000001L)
> +/** @} */
> +
>  #endif /* _UAPI_I915_DRM_H_ */
> -- 
> 2.2.2
> 
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Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Intel-gfx@lists.freedesktop.org
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[PATCH 3/4] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using frame buffer modifiers instead of object tiling mode
for display purposes.

To ensure compatibility with old userspace which is using set_tiling
and does not know about frame buffer modifiers, the latter are faked
internally when tile object is set for display. This way all interested
call sites can use fb modifiers exclusively.

Also ensure tiling specified via fb modifiers must match object tiling
used for fencing if both are specified.

v2:
   * Refactored to use fb modifiers directly in switch statements in
     order to completely disconnect from the object tiling namespace.
     (Daniel Vetter)
   * Added helper to convert to hardware mode representation for
     future proofing.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 150 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
 drivers/gpu/drm/i915/intel_pm.c      |   7 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  34 ++++----
 4 files changed, 124 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5c0579..cf64e3c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2190,14 +2190,31 @@ static bool need_vtd_wa(struct drm_device *dev)
 }
 
 int
-intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
+intel_fb_align_height(struct drm_device *dev, int height, u64 tiling)
 {
 	int tile_height;
 
-	tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
+	tile_height = tiling != I915_FORMAT_MOD_NONE ?
+					(IS_GEN2(dev) ? 16 : 8) : 1;
 	return ALIGN(height, tile_height);
 }
 
+static u64 intel_fb_modifier_tiling(u64 mod)
+{
+	return mod & I915_FORMAT_MOD_TILING_MASK;
+}
+
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb)
+{
+	return fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK;
+}
+
+static u32 intel_fb_tiling_hw_mode(struct drm_framebuffer *fb)
+{
+	return (fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK) !=
+	       I915_FORMAT_MOD_NONE ? 1 : 0;
+}
+
 int
 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			   struct drm_framebuffer *fb,
@@ -2211,8 +2228,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
@@ -2222,7 +2239,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 		else
 			alignment = 64 * 1024;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else {
@@ -2230,11 +2247,9 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			alignment = 0;
 		}
 		break;
-	case I915_TILING_Y:
-		WARN(1, "Y tiled bo slipped through, driver bug!\n");
-		return -EINVAL;
 	default:
-		BUG();
+		MISSING_CASE(intel_fb_tiling_mode(fb));
+		return -EINVAL;
 	}
 
 	/* Note that the w/a also requires 64 PTE of padding following the
@@ -2293,11 +2308,11 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int cpp,
 					     unsigned int pitch)
 {
-	if (tiling_mode != I915_TILING_NONE) {
+	if (tiling_mode != I915_FORMAT_MOD_NONE) {
 		unsigned int tile_rows, tiles;
 
 		tile_rows = *y / 8;
@@ -2381,14 +2396,17 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
 	if (!obj)
 		return false;
 
-	obj->tiling_mode = plane_config->tiling;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (plane_config->tiling == I915_FORMAT_MOD_X_TILED) {
+		obj->tiling_mode = I915_TILING_X;
 		obj->stride = crtc->base.primary->fb->pitches[0];
+	}
 
 	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
 	mode_cmd.width = crtc->base.primary->fb->width;
 	mode_cmd.height = crtc->base.primary->fb->height;
+	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 	mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
+	mode_cmd.modifier[0] = plane_config->tiling;
 
 	mutex_lock(&dev->struct_mutex);
 
@@ -2461,7 +2479,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 			continue;
 
 		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
-			if (obj->tiling_mode != I915_TILING_NONE)
+			if (intel_fb_tiling_mode(c->primary->fb) !=
+			    I915_FORMAT_MOD_NONE)
 				dev_priv->preserve_bios_swizzle = true;
 
 			drm_framebuffer_reference(c->primary->fb);
@@ -2487,6 +2506,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2558,8 +2578,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4 &&
-	    obj->tiling_mode != I915_TILING_NONE)
+	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
@@ -2569,7 +2588,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2619,6 +2638,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2667,7 +2687,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -2675,7 +2695,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
@@ -2763,11 +2783,11 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -6613,9 +6633,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(plane));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -6623,7 +6644,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(plane));
 		else
 			offset = I915_READ(DSPLINOFF(plane));
@@ -7646,7 +7667,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, 0));
 	if (val & PLANE_CTL_TILED_MASK)
-		plane_config->tiling = I915_TILING_X;
+		plane_config->tiling = I915_FORMAT_MOD_X_TILED;
+	else
+		plane_config->tiling = I915_FORMAT_MOD_NONE;
 
 	pixel_format = val & PLANE_CTL_FORMAT_MASK;
 	fourcc = skl_format_to_fourcc(pixel_format,
@@ -7666,10 +7689,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_STRIDE(pipe, 0));
 	switch (plane_config->tiling) {
-	case I915_TILING_NONE:
+	case I915_FORMAT_MOD_NONE:
 		stride_mult = 64;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride_mult = 512;
 		break;
 	default:
@@ -7743,9 +7766,10 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(pipe));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -7756,7 +7780,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		offset = I915_READ(DSPOFFSET(pipe));
 	} else {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(pipe));
 		else
 			offset = I915_READ(DSPLINOFF(pipe));
@@ -9307,7 +9331,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	intel_ring_emit(ring, fb->pitches[0]);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
-			obj->tiling_mode);
+			intel_fb_tiling_hw_mode(fb));
 
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
@@ -9340,7 +9364,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP |
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+	intel_ring_emit(ring, fb->pitches[0] | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	/* Contrary to the suggestions in the documentation,
@@ -9444,7 +9468,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	}
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+	intel_ring_emit(ring, (fb->pitches[0] | intel_fb_tiling_hw_mode(fb)));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
@@ -9485,14 +9509,13 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	const enum pipe pipe = intel_crtc->pipe;
 	u32 ctl, stride;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	ctl = I915_READ(PLANE_CTL(pipe, 0));
 	ctl &= ~PLANE_CTL_TILED_MASK;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		ctl |= PLANE_CTL_TILED_X;
 
 	/*
@@ -9500,7 +9523,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	stride = fb->pitches[0] >> 6;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
 
 	/*
@@ -9518,16 +9541,14 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_framebuffer *intel_fb =
-		to_intel_framebuffer(intel_crtc->base.primary->fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
+	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
 	u32 dspcntr;
 	u32 reg;
 
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
@@ -9627,11 +9648,11 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 		return -ENODEV;
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride = fb->pitches[0] >> 9;
 		break;
 	default:
@@ -9655,7 +9676,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, 0);
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
+	intel_ring_emit(ring, stride << 6 | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	intel_mark_page_flip_active(intel_crtc);
@@ -9831,7 +9852,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
+		if (intel_fb_tiling_mode(fb) !=
+		    intel_fb_tiling_mode(work->old_fb))
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			ring = NULL;
 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -12208,7 +12230,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
+	    intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		ret = -EINVAL;
 	}
@@ -12689,6 +12712,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 {
 	int aligned_height;
 	int pitch_limit;
+	u64 tiling_mode = I915_FORMAT_MOD_NONE;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -12698,6 +12722,29 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 	}
 
+	/* If obj is tiled and fb modifier not set propagate it in
+	 * for backward compatibility with old userspace.
+	 */
+	if (obj->tiling_mode && !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
+		tiling_mode = mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
+	}
+
+	/* Get tiling mode from fb modifier if set. */
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS)
+		tiling_mode = intel_fb_modifier_tiling(mode_cmd->modifier[0]);
+	else
+		mode_cmd->modifier[0] = tiling_mode;
+
+	/* Ensure new userspace is using the interface correctly by only
+	 * allowing old usage of set_tiling if it matches with the
+	 * fb modifier tiling.
+	 */
+	if (obj->tiling_mode && tiling_mode != I915_FORMAT_MOD_X_TILED) {
+		DRM_ERROR("Object (%u) and fb (%llx) tiling mismatch!\n",
+			  obj->tiling_mode, tiling_mode);
+		return -EINVAL;
+	}
+
 	if (mode_cmd->pitches[0] & 63) {
 		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
 			  mode_cmd->pitches[0]);
@@ -12707,12 +12754,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 16*1024;
 		else
 			pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 3) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 8*1024;
 		else
 			pitch_limit = 16*1024;
@@ -12722,12 +12769,13 @@ static int intel_framebuffer_init(struct drm_device *dev,
 
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-			  obj->tiling_mode ? "tiled" : "linear",
+			  tiling_mode != I915_FORMAT_MOD_NONE ?
+				"tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE &&
+	if (tiling_mode != I915_FORMAT_MOD_NONE && obj->stride &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
@@ -12782,7 +12830,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-					       obj->tiling_mode);
+					       tiling_mode);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f048f8b..f96dc51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -258,7 +258,7 @@ struct intel_plane_state {
 };
 
 struct intel_initial_plane_config {
-	unsigned int tiling;
+	u64 tiling;
 	int size;
 	u32 base;
 };
@@ -877,8 +877,7 @@ void intel_frontbuffer_flip(struct drm_device *dev,
 	intel_frontbuffer_flush(dev, frontbuffer_bits);
 }
 
-int intel_fb_align_height(struct drm_device *dev, int height,
-			  unsigned int tiling);
+int intel_fb_align_height(struct drm_device *dev, int height, u64 tiling);
 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 
 
@@ -984,7 +983,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int bpp,
 					     unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
@@ -1008,6 +1007,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb);
+
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..db82184 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1182,12 +1182,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
 	if (IS_I915GM(dev) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->primary->fb);
-
 		/* self-refresh seems busted with untiled */
-		if (obj->tiling_mode == I915_TILING_NONE)
+		if (intel_fb_tiling_mode(enabled->primary->fb) ==
+		    I915_FORMAT_MOD_NONE)
 			enabled = NULL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44..c64e854 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -245,11 +245,11 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 
@@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SP_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SP_TILED;
 
 	sprctl |= SP_ENABLE;
@@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
-							obj->tiling_mode,
+							tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	u32 sprctl, sprscale = 0;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPRCTL(pipe));
 
@@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SPRITE_TILED;
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 * register */
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-	else if (obj->tiling_mode != I915_TILING_NONE)
+	else if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	unsigned long dvssurf_offset, linear_offset;
 	u32 dvscntr, dvsscale;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	dvscntr = I915_READ(DVSCNTR(pipe));
 
@@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	dvscntr |= DVS_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dvscntr |= DVS_TILED;
 
 	if (IS_GEN6(dev))
@@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
@@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(DVSLINOFF(pipe), linear_offset);
@@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int crtc_x, crtc_y;
 	unsigned int crtc_w, crtc_h;
 	uint32_t src_x, src_y, src_w, src_h;
@@ -1107,9 +1109,9 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	}
 
 	/* Sprite planes can be linear or x-tiled surfaces */
-	switch (obj->tiling_mode) {
-		case I915_TILING_NONE:
-		case I915_TILING_X:
+	switch (intel_fb_tiling_mode(fb)) {
+		case I915_FORMAT_MOD_NONE:
+		case I915_FORMAT_MOD_X_TILED:
 			break;
 		default:
 			DRM_DEBUG_KMS("Unsupported tiling mode\n");
-- 
2.2.2

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[PATCH 4/4] drm/i915: Announce support for framebuffer modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Let the DRM core know we can handle it.

v2: Change to boolean true. (Daniel Vetter)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cf64e3c..39a17f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13234,6 +13234,8 @@ void intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
 
+	dev->mode_config.allow_fb_modifiers = true;
+
 	dev->mode_config.funcs = &intel_mode_funcs;
 
 	intel_init_quirks(dev);
-- 
2.2.2

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Re: [PATCH 4/4] drm/i915: Announce support for framebuffer modifiers

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5721
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  283/283              283/283
ILK              +1                 308/319              309/319
SNB              +23-1              319/346              341/346
IVB              +2                 376/384              378/384
BYT                                  296/296              296/296
HSW                 -1              425/428              424/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 ILK  igt_kms_flip_vblank-vs-hang      TIMEOUT(1, M37)PASS(1, M37)      PASS(1, M37)
*SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(2, M35M22)      PASS(1, M22)
 SNB  igt_kms_flip_modeset-vs-vblank-race-interruptible      DMESG_WARN(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
*SNB  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2      PASS(2, M35M22)      TIMEOUT(1, M22)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_cursor      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_fences      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_fences-dpms      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_gem-pread      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
*SNB  igt_pm_rpm_i2c      FAIL(1, M22)NSPT(1, M35)      PASS(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
 SNB  igt_pm_rpm_rte      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
*IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(2, M34)      PASS(1, M34)
 IVB  igt_gem_storedw_batches_loop_secure-dispatch      DMESG_WARN(1, M34)PASS(1, M34)      PASS(1, M34)
*HSW  igt_gem_storedw_loop_blt      PASS(2, M40M20)      DMESG_WARN(1, M20)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 4/4] drm/i915: Announce support for framebuffer modifiers

[He, Shuang]

Hello, this one is invalid report when debugging smarter patch apply method, in which case, baseline has id bigger than this task will generate invalidate comparison result.
I have fixed the comparison algorithm.
A correct one will be sent out later

Thanks
	--Shuang

> -----Original Message-----
> From: He, Shuang
> Sent: Sunday, February 08, 2015 5:57 PM
> To: He, Shuang; Gao, Ethan; intel-gfx@lists.freedesktop.org;
> tvrtko.ursulin@linux.intel.com
> Subject: RE: [Intel-gfx] [PATCH 4/4] drm/i915: Announce support for
> framebuffer modifiers
> 
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang.he@intel.com)
> Task id: 5721
> -------------------------------------Summary-------------------------------------
> Platform          Delta          drm-intel-nightly          Series
> Applied
> PNV                                  283/283
> 283/283
> ILK              +1                 308/319              309/319
> SNB              +23-1              319/346              341/346
> IVB              +2                 376/384              378/384
> BYT                                  296/296
> 296/296
> HSW                 -1              425/428              424/428
> BDW                                  318/333
> 318/333
> -------------------------------------Detailed-------------------------------------
> Platform  Test                                drm-intel-nightly
> Series Applied
>  ILK  igt_kms_flip_vblank-vs-hang      TIMEOUT(1, M37)PASS(1, M37)
> PASS(1, M37)
> *SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(2, M35M22)
> PASS(1, M22)
>  SNB  igt_kms_flip_modeset-vs-vblank-race-interruptible
> DMESG_WARN(1, M35)PASS(1, M22)      PASS(1, M22)
>  SNB  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible
> DMESG_WARN(1, M35)PASS(1, M22)      PASS(1, M22)
>  SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1,
> M35)PASS(1, M22)      PASS(1, M22)
>  SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1,
> M35)PASS(1, M22)      PASS(1, M22)
> *SNB  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2
> PASS(2, M35M22)      TIMEOUT(1, M22)
>  SNB  igt_kms_rotation_crc_primary-rotation      NSPT(1, M35)PASS(1,
> M22)      PASS(1, M22)
>  SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_cursor      NSPT(1, M35)PASS(1, M22)      PASS(1,
> M22)
>  SNB  igt_pm_rpm_cursor-dpms      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M35)PASS(1,
> M22)      PASS(1, M22)
>  SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_drm-resources-equal      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_fences      NSPT(1, M35)PASS(1, M22)      PASS(1,
> M22)
>  SNB  igt_pm_rpm_fences-dpms      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_gem-execbuf      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_gem-pread      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
> *SNB  igt_pm_rpm_i2c      FAIL(1, M22)NSPT(1, M35)      PASS(1, M22)
>  SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1,
> M35)PASS(1, M22)      PASS(1, M22)
>  SNB  igt_pm_rpm_pci-d3-state      NSPT(1, M35)PASS(1, M22)
> PASS(1, M22)
>  SNB  igt_pm_rpm_rte      NSPT(1, M35)PASS(1, M22)      PASS(1, M22)
> *IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(2, M34)
> PASS(1, M34)
>  IVB  igt_gem_storedw_batches_loop_secure-dispatch
> DMESG_WARN(1, M34)PASS(1, M34)      PASS(1, M34)
> *HSW  igt_gem_storedw_loop_blt      PASS(2, M40M20)
> DMESG_WARN(1, M20)
> Note: You need to pay more attention to line start with '*'
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Re: [PATCH 4/4] drm/i915: Announce support for framebuffer modifiers

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5721
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  283/283              283/283
ILK                                  309/319              309/319
SNB              +1-2              342/346              341/346
IVB              +1-1              378/384              378/384
BYT                                  296/296              296/296
HSW              +1                 423/428              424/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      PASS(1, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_pipe_crc_basic_read-crc-pipe-A      DMESG_WARN(1, M22)PASS(1, M22)      PASS(1, M22)
*SNB  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2      PASS(1, M22)      TIMEOUT(1, M22)
*IVB  igt_gem_pwrite_pread_snooped-copy-performance      PASS(1, M34)      DMESG_WARN(1, M34)
*IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(1, M34)      PASS(1, M34)
*HSW  igt_gem_storedw_loop_vebox      DMESG_WARN(2, M20)      PASS(1, M20)
Note: You need to pay more attention to line start with '*'
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[PATCH 3/4 v3] drm/i915: Use frame buffer modifiers for tiled display

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using frame buffer modifiers instead of object tiling mode
for display purposes.

To ensure compatibility with old userspace which is using set_tiling
and does not know about frame buffer modifiers, the latter are faked
internally when tile object is set for display. This way all interested
call sites can use fb modifiers exclusively.

Also ensure tiling specified via fb modifiers must match object tiling
used for fencing if both are specified.

v2:
   * Refactored to use fb modifiers directly in switch statements in
     order to completely disconnect from the object tiling namespace.
     (Daniel Vetter)
   * Added helper to convert to hardware mode representation for
     future proofing.

v3:
   * Simplified old vs new userspace logic flow.
   * Reject zero fb modifier when flag is set.
   * Correct pitch_limit checks.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 175 ++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      |   7 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  34 +++----
 4 files changed, 146 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5c0579..9e725af 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2190,14 +2190,31 @@ static bool need_vtd_wa(struct drm_device *dev)
 }
 
 int
-intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
+intel_fb_align_height(struct drm_device *dev, int height, u64 tiling)
 {
 	int tile_height;
 
-	tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
+	tile_height = tiling != I915_FORMAT_MOD_NONE ?
+					(IS_GEN2(dev) ? 16 : 8) : 1;
 	return ALIGN(height, tile_height);
 }
 
+static u64 intel_fb_modifier_tiling(u64 mod)
+{
+	return mod & I915_FORMAT_MOD_TILING_MASK;
+}
+
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb)
+{
+	return fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK;
+}
+
+static u32 intel_fb_tiling_hw_mode(struct drm_framebuffer *fb)
+{
+	return (fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK) !=
+	       I915_FORMAT_MOD_NONE ? 1 : 0;
+}
+
 int
 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			   struct drm_framebuffer *fb,
@@ -2211,8 +2228,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
@@ -2222,7 +2239,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 		else
 			alignment = 64 * 1024;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else {
@@ -2230,11 +2247,9 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			alignment = 0;
 		}
 		break;
-	case I915_TILING_Y:
-		WARN(1, "Y tiled bo slipped through, driver bug!\n");
-		return -EINVAL;
 	default:
-		BUG();
+		MISSING_CASE(intel_fb_tiling_mode(fb));
+		return -EINVAL;
 	}
 
 	/* Note that the w/a also requires 64 PTE of padding following the
@@ -2293,11 +2308,11 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int cpp,
 					     unsigned int pitch)
 {
-	if (tiling_mode != I915_TILING_NONE) {
+	if (tiling_mode != I915_FORMAT_MOD_NONE) {
 		unsigned int tile_rows, tiles;
 
 		tile_rows = *y / 8;
@@ -2381,14 +2396,17 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
 	if (!obj)
 		return false;
 
-	obj->tiling_mode = plane_config->tiling;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (plane_config->tiling == I915_FORMAT_MOD_X_TILED) {
+		obj->tiling_mode = I915_TILING_X;
 		obj->stride = crtc->base.primary->fb->pitches[0];
+	}
 
 	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
 	mode_cmd.width = crtc->base.primary->fb->width;
 	mode_cmd.height = crtc->base.primary->fb->height;
+	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 	mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
+	mode_cmd.modifier[0] = plane_config->tiling;
 
 	mutex_lock(&dev->struct_mutex);
 
@@ -2461,7 +2479,8 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
 			continue;
 
 		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
-			if (obj->tiling_mode != I915_TILING_NONE)
+			if (intel_fb_tiling_mode(c->primary->fb) !=
+			    I915_FORMAT_MOD_NONE)
 				dev_priv->preserve_bios_swizzle = true;
 
 			drm_framebuffer_reference(c->primary->fb);
@@ -2487,6 +2506,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2558,8 +2578,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4 &&
-	    obj->tiling_mode != I915_TILING_NONE)
+	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
@@ -2569,7 +2588,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2619,6 +2638,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2667,7 +2687,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -2675,7 +2695,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
@@ -2763,11 +2783,11 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -6613,9 +6633,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(plane));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -6623,7 +6644,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(plane));
 		else
 			offset = I915_READ(DSPLINOFF(plane));
@@ -7646,7 +7667,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, 0));
 	if (val & PLANE_CTL_TILED_MASK)
-		plane_config->tiling = I915_TILING_X;
+		plane_config->tiling = I915_FORMAT_MOD_X_TILED;
+	else
+		plane_config->tiling = I915_FORMAT_MOD_NONE;
 
 	pixel_format = val & PLANE_CTL_FORMAT_MASK;
 	fourcc = skl_format_to_fourcc(pixel_format,
@@ -7666,10 +7689,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_STRIDE(pipe, 0));
 	switch (plane_config->tiling) {
-	case I915_TILING_NONE:
+	case I915_FORMAT_MOD_NONE:
 		stride_mult = 64;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride_mult = 512;
 		break;
 	default:
@@ -7743,9 +7766,10 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(pipe));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -7756,7 +7780,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		offset = I915_READ(DSPOFFSET(pipe));
 	} else {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(pipe));
 		else
 			offset = I915_READ(DSPLINOFF(pipe));
@@ -9307,7 +9331,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	intel_ring_emit(ring, fb->pitches[0]);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
-			obj->tiling_mode);
+			intel_fb_tiling_hw_mode(fb));
 
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
@@ -9340,7 +9364,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP |
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+	intel_ring_emit(ring, fb->pitches[0] | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	/* Contrary to the suggestions in the documentation,
@@ -9444,7 +9468,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	}
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+	intel_ring_emit(ring, (fb->pitches[0] | intel_fb_tiling_hw_mode(fb)));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
@@ -9485,14 +9509,13 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	const enum pipe pipe = intel_crtc->pipe;
 	u32 ctl, stride;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	ctl = I915_READ(PLANE_CTL(pipe, 0));
 	ctl &= ~PLANE_CTL_TILED_MASK;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		ctl |= PLANE_CTL_TILED_X;
 
 	/*
@@ -9500,7 +9523,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	stride = fb->pitches[0] >> 6;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
 
 	/*
@@ -9518,16 +9541,14 @@ static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_framebuffer *intel_fb =
-		to_intel_framebuffer(intel_crtc->base.primary->fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
+	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
 	u32 dspcntr;
 	u32 reg;
 
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
@@ -9627,11 +9648,11 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 		return -ENODEV;
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride = fb->pitches[0] >> 9;
 		break;
 	default:
@@ -9655,7 +9676,7 @@ static int intel_gen9_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, 0);
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
+	intel_ring_emit(ring, stride << 6 | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	intel_mark_page_flip_active(intel_crtc);
@@ -9831,7 +9852,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
+		if (intel_fb_tiling_mode(fb) !=
+		    intel_fb_tiling_mode(work->old_fb))
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			ring = NULL;
 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -12208,7 +12230,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
+	    intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		ret = -EINVAL;
 	}
@@ -12689,13 +12712,56 @@ static int intel_framebuffer_init(struct drm_device *dev,
 {
 	int aligned_height;
 	int pitch_limit;
+	u64 tiling_mode;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	if (obj->tiling_mode == I915_TILING_Y) {
-		DRM_DEBUG("hardware does not support tiling Y\n");
-		return -EINVAL;
+	/* Get tiling mode from fb modifier if set, or from the object with
+	 * legacy userspace.
+	 */
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
+		tiling_mode = intel_fb_modifier_tiling(mode_cmd->modifier[0]);
+
+		if (!tiling_mode) {
+			DRM_ERROR("Zero fb modifier!\n");
+			return -EINVAL;
+		}
+
+		/* Ensure new userspace is using the interface correctly - only
+		 * legacy usage of set_tiling() is allowed with the new fb
+		 * modifier tiling.
+		 */
+		if (!(obj->tiling_mode == I915_TILING_NONE ||
+		      obj->tiling_mode == I915_TILING_X)) {
+			DRM_ERROR("Object not linear or X tiled!\n");
+			return -EINVAL;
+		}
+
+		if (obj->tiling_mode &&
+		    tiling_mode != I915_FORMAT_MOD_X_TILED) {
+			DRM_ERROR(
+				  "Object and fb tiling mismatch! (%llx)\n",
+				  tiling_mode);
+			return -EINVAL;
+		}
+	} else {
+		switch (obj->tiling_mode) {
+		case I915_TILING_NONE:
+			tiling_mode = I915_FORMAT_MOD_NONE;
+			break;
+		case I915_TILING_X:
+			tiling_mode = I915_FORMAT_MOD_X_TILED;
+			break;
+		case I915_TILING_Y:
+			DRM_DEBUG("hardware does not support tiling Y\n");
+			return -EINVAL;
+		default:
+			MISSING_CASE(obj->tiling_mode);
+			return -EINVAL;
+		}
+
+		mode_cmd->modifier[0] = tiling_mode;
 	}
 
 	if (mode_cmd->pitches[0] & 63) {
@@ -12707,12 +12773,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode)
+		if (tiling_mode != I915_FORMAT_MOD_NONE)
 			pitch_limit = 16*1024;
 		else
 			pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 3) {
-		if (obj->tiling_mode)
+		if (tiling_mode != I915_FORMAT_MOD_NONE)
 			pitch_limit = 8*1024;
 		else
 			pitch_limit = 16*1024;
@@ -12722,12 +12788,13 @@ static int intel_framebuffer_init(struct drm_device *dev,
 
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-			  obj->tiling_mode ? "tiled" : "linear",
+			  tiling_mode != I915_FORMAT_MOD_NONE ?
+				"tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE &&
+	if (tiling_mode != I915_FORMAT_MOD_NONE && obj->stride &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
@@ -12782,7 +12849,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-					       obj->tiling_mode);
+					       tiling_mode);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f048f8b..f96dc51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -258,7 +258,7 @@ struct intel_plane_state {
 };
 
 struct intel_initial_plane_config {
-	unsigned int tiling;
+	u64 tiling;
 	int size;
 	u32 base;
 };
@@ -877,8 +877,7 @@ void intel_frontbuffer_flip(struct drm_device *dev,
 	intel_frontbuffer_flush(dev, frontbuffer_bits);
 }
 
-int intel_fb_align_height(struct drm_device *dev, int height,
-			  unsigned int tiling);
+int intel_fb_align_height(struct drm_device *dev, int height, u64 tiling);
 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 
 
@@ -984,7 +983,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int bpp,
 					     unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
@@ -1008,6 +1007,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb);
+
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..db82184 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1182,12 +1182,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
 	if (IS_I915GM(dev) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->primary->fb);
-
 		/* self-refresh seems busted with untiled */
-		if (obj->tiling_mode == I915_TILING_NONE)
+		if (intel_fb_tiling_mode(enabled->primary->fb) ==
+		    I915_FORMAT_MOD_NONE)
 			enabled = NULL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44..c64e854 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -245,11 +245,11 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -413,6 +413,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 
@@ -471,7 +472,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SP_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SP_TILED;
 
 	sprctl |= SP_ENABLE;
@@ -488,7 +489,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
-							obj->tiling_mode,
+							tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -509,7 +510,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -613,6 +614,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	u32 sprctl, sprscale = 0;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPRCTL(pipe));
 
@@ -652,7 +654,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SPRITE_TILED;
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -680,7 +682,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -705,7 +707,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 * register */
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-	else if (obj->tiling_mode != I915_TILING_NONE)
+	else if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -818,6 +820,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	unsigned long dvssurf_offset, linear_offset;
 	u32 dvscntr, dvsscale;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	dvscntr = I915_READ(DVSCNTR(pipe));
 
@@ -857,7 +860,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	dvscntr |= DVS_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dvscntr |= DVS_TILED;
 
 	if (IS_GEN6(dev))
@@ -880,7 +883,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
@@ -897,7 +900,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(DVSLINOFF(pipe), linear_offset);
@@ -1076,7 +1079,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int crtc_x, crtc_y;
 	unsigned int crtc_w, crtc_h;
 	uint32_t src_x, src_y, src_w, src_h;
@@ -1107,9 +1109,9 @@ intel_check_sprite_plane(struct drm_plane *plane,
 	}
 
 	/* Sprite planes can be linear or x-tiled surfaces */
-	switch (obj->tiling_mode) {
-		case I915_TILING_NONE:
-		case I915_TILING_X:
+	switch (intel_fb_tiling_mode(fb)) {
+		case I915_FORMAT_MOD_NONE:
+		case I915_FORMAT_MOD_X_TILED:
 			break;
 		default:
 			DRM_DEBUG_KMS("Unsupported tiling mode\n");
-- 
2.2.2

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