From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Yu Zhang <yu.c.zhang@linux.intel.com>, intel-gfx@lists.freedesktop.org
Cc: daniel.vetter@ffwll.ch
Subject: Re: [PATCH v4 0/8] Add enlightenments for vGPU
Date: Tue, 10 Feb 2015 12:11:02 +0000 [thread overview]
Message-ID: <54D9F556.1000106@linux.intel.com> (raw)
In-Reply-To: <1423566354-5532-1-git-send-email-yu.c.zhang@linux.intel.com>
On 02/10/2015 11:05 AM, Yu Zhang wrote:
> This patch set includes necessary code changes when i915 driver
> runs inside a VM. Though ideally we can run an unmodified i915
> driver in VM, adding such enlightenments can greatly reduce the
> virtualization complexity in orders of magnitude. Code changes
> for the host side, which includes the actual Intel GVT-g
> implementation, will be sent out in other patches.
>
> The primary change introduced here is to implement so-called
> "address space ballooning" technique. XenGT partitions global
> graphics memory among multiple VMs, so each VM can directly
> access a portion of the memory without hypervisor's intervention,
> e.g. filling textures or queuing commands. However with the
> partitioning an unmodified i915 driver would assume a smaller
> graphics memory starting from address ZERO, so requires XenGT
> core module (vgt) to translate the graphics address between
> 'guest view' and 'host view', for all registers and command
> opcodes which contain a graphics memory address. To reduce the
> complexity, XenGT introduces "address space ballooning", by
> telling the exact partitioning knowledge to each guest i915
> driver, which then reserves and prevents non-allocated portions
> from allocation. Then vgt module only needs to scan and validate
> graphics addresses without complexity of translation.
>
> Note: The partitioning of global graphics memory may break some
> applications, with large objects in the aperture, because current
> userspace assumes half of the aperture usable. That would need
> separate fix either in user space (e.g. remove assumption in mesa)
> or in kernel (with some faulting mechanism).
>
> The partitioning knowledge is conveyed through a reserved MMIO
> range, called PVINFO, which will be architecturally reserved in
> future hardware generations. Another information carried through
> PVINFO is about the number of fence registers. As a global resource,
> XenGT also partitions them among VMs.
>
> Other changes are trivial as optimizations, to either reduce the
> trap overhead or disable power management features which don't
> make sense in a virtualized environment.
>
>
> Yu Zhang (8):
> drm/i915: Introduce a PV INFO page structure for Intel GVT-g.
> drm/i915: Adds graphic address space ballooning logic
> drm/i915: Partition the fence registers for vGPU in i915 driver
> drm/i915: Disable framebuffer compression for i915 driver in VM
> drm/i915: Add the display switch logic for vGPU in i915 driver
> drm/i915: Disable power management for i915 driver in VM
> drm/i915: Create vGPU specific MMIO operations to reduce traps
> drm/i915: Support alias ppgtt in VM if ppgtt is enabled
All my comments have been addressed (and I especially like the ASCII
diagram of the memory space!) so you can put my r-b on all the patches
from this series:
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-02-10 12:11 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-10 11:05 [PATCH v4 0/8] Add enlightenments for vGPU Yu Zhang
2015-02-10 11:05 ` [PATCH v4 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g Yu Zhang
2015-03-11 6:43 ` Dave Airlie
2015-02-10 11:05 ` [PATCH v4 2/8] drm/i915: Adds graphic address space ballooning logic Yu Zhang
2015-02-10 11:05 ` [PATCH v4 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver Yu Zhang
2015-02-10 11:05 ` [PATCH v4 4/8] drm/i915: Disable framebuffer compression for i915 driver in VM Yu Zhang
2015-02-10 11:05 ` [PATCH v4 5/8] drm/i915: Add the display switch logic for vGPU in i915 driver Yu Zhang
2015-02-10 11:05 ` [PATCH v4 6/8] drm/i915: Disable power management for i915 driver in VM Yu Zhang
2015-02-10 11:05 ` [PATCH v4 7/8] drm/i915: Create vGPU specific MMIO operations to reduce traps Yu Zhang
2015-02-10 11:05 ` [PATCH v4 8/8] drm/i915: Support alias ppgtt in VM if ppgtt is enabled Yu Zhang
2015-02-10 12:11 ` Tvrtko Ursulin [this message]
2015-02-11 7:47 ` [PATCH v4 0/8] Add enlightenments for vGPU Yu, Zhang
2015-02-11 8:06 ` Daniel Vetter
2015-02-11 8:12 ` Yu, Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=54D9F556.1000106@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=daniel.vetter@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
--cc=yu.c.zhang@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox