* [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.
@ 2015-02-10 9:11 Zhi Wang
2015-02-11 8:03 ` Daniel Vetter
0 siblings, 1 reply; 3+ messages in thread
From: Zhi Wang @ 2015-02-10 9:11 UTC (permalink / raw)
To: intel-gfx
This patch introduces 2 bit definitions of context save/restore
control register.
Thanks comments from David/Thomas/Daniel.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d05f3bc..2196e9c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1668,7 +1668,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
reg_state[CTX_CONTEXT_CONTROL+1] =
- _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
+ _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
+ CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
reg_state[CTX_RING_HEAD+1] = 0;
reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 6f2d7da..ced191f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -30,6 +30,8 @@
#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.
2015-02-10 9:11 [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register Zhi Wang
@ 2015-02-11 8:03 ` Daniel Vetter
2015-02-10 16:36 ` Zhi Wang
0 siblings, 1 reply; 3+ messages in thread
From: Daniel Vetter @ 2015-02-11 8:03 UTC (permalink / raw)
To: Zhi Wang, david.s.gordon
Cc: intel-gfx, orprtsshouldn'tupdateuntiltestshavebeenvetted
On Tue, Feb 10, 2015 at 05:11:36PM +0800, Zhi Wang wrote:
> This patch introduces 2 bit definitions of context save/restore
> control register.
>
> Thanks comments from David/Thomas/Daniel.
Instead of Thanks just add the usual Suggested-by: lines. And please Cc:
everyone from the previous discussion when you follow up with a patch.
I've added that now.
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> drivers/gpu/drm/i915/intel_lrc.h | 2 ++
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d05f3bc..2196e9c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1668,7 +1668,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
> reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
> reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
> reg_state[CTX_CONTEXT_CONTROL+1] =
> - _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
> + _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
> + CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
> reg_state[CTX_RING_HEAD+1] = 0;
> reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 6f2d7da..ced191f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -30,6 +30,8 @@
> #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
> #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
> #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
> +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
> #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
> #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.
2015-02-11 8:03 ` Daniel Vetter
@ 2015-02-10 16:36 ` Zhi Wang
0 siblings, 0 replies; 3+ messages in thread
From: Zhi Wang @ 2015-02-10 16:36 UTC (permalink / raw)
To: Daniel Vetter, david.s.gordon
Cc: intel-gfx, orprtsshouldn'tupdateuntiltestshavebeenvetted
Thanks Daniel! :)
于 2015年02月11日 16:03, Daniel Vetter 写道:
> On Tue, Feb 10, 2015 at 05:11:36PM +0800, Zhi Wang wrote:
>> This patch introduces 2 bit definitions of context save/restore
>> control register.
>>
>> Thanks comments from David/Thomas/Daniel.
>
> Instead of Thanks just add the usual Suggested-by: lines. And please Cc:
> everyone from the previous discussion when you follow up with a patch.
> I've added that now.
>>
>> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
>
> Queued for -next, thanks for the patch.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
>> drivers/gpu/drm/i915/intel_lrc.h | 2 ++
>> 2 files changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index d05f3bc..2196e9c 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1668,7 +1668,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>> reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
>> reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
>> reg_state[CTX_CONTEXT_CONTROL+1] =
>> - _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
>> + _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
>> + CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>> reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
>> reg_state[CTX_RING_HEAD+1] = 0;
>> reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
>> index 6f2d7da..ced191f 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.h
>> +++ b/drivers/gpu/drm/i915/intel_lrc.h
>> @@ -30,6 +30,8 @@
>> #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
>> #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
>> #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
>> +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
>> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
>> #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
>> #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-02-11 8:05 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-02-10 9:11 [PATCH] drm/i915: Introduce bit definitions of CTXT_SR_CTRL register Zhi Wang
2015-02-11 8:03 ` Daniel Vetter
2015-02-10 16:36 ` Zhi Wang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox