[PATCH libdrm 00/12] Introduce drm_intel_device and use i915

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* [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
@ 2015-03-05 16:20 Damien Lespiau
  2015-03-05 16:20 ` [PATCH 01/12] intel: Remove unused define IS_MOBILE() Damien Lespiau
                   ` (13 more replies)
  0 siblings, 14 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

A couple of things I wanted to do for the longest time:
  
  - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the
    file when updating
  - Start a new object, struct drm_intel_device where we could put common code
    across several userspace projects. For instance it could be where we put
    the "number of threads" logic we need to use in several 3d/gpgpu
    states/instructions (that's a bit fiddly starting with CHV: we can't use
    static tables anymore and need a runtime query to the kernel)

I tested it a bit so it can't be totally wrong:

  - I ran with this series on a couple of machines with no noticeable problem
  - I check that the INTEL_DEVID_OVERRIDE env variable was still working (to
    dump AUB files)
  - make check, which exercises changes in the decoder path, still passes

-- 
Damien

Damien Lespiau (12):
  intel: Remove unused define IS_MOBILE()
  intel: Introduce an drm_intel_device object
  intel: Use drm_intel_device in the gem buffer manager
  intel: Make drm_intel_decode use a drm_intel_device
  intel: Use '||' for the boolean or
  intel: Kill the IS_9XX() macro
  intel: Kill the IS_GEN4() macro
  intel: Remove direct usage of IS_915()
  intel: Provide IS_GENX() macros taking a drm_intel_device as argument
  intel: Make test_decode fail gracefully the decode context is NULL
  intel: Make test_decode not depend on intel_chipset.h
  intel: Remove intel_chipset.h

 intel/Makefile.sources    |   5 +-
 intel/i915_pciids.h       | 289 +++++++++++++++++++++++++++++++++++
 intel/intel_bufmgr_gem.c  |  70 ++-------
 intel/intel_chipset.h     | 376 ----------------------------------------------
 intel/intel_decode.c      |  82 +++++-----
 intel/intel_device.c      | 300 ++++++++++++++++++++++++++++++++++++
 intel/intel_device.h      |  99 ++++++++++++
 intel/intel_device_priv.h |  43 ++++++
 intel/test_decode.c       |  12 +-
 9 files changed, 791 insertions(+), 485 deletions(-)
 create mode 100644 intel/i915_pciids.h
 delete mode 100644 intel/intel_chipset.h
 create mode 100644 intel/intel_device.c
 create mode 100644 intel/intel_device.h
 create mode 100644 intel/intel_device_priv.h

-- 
1.8.3.1

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^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH 01/12] intel: Remove unused define IS_MOBILE()
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 02/12] intel: Introduce an drm_intel_device object Damien Lespiau
                   ` (12 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_chipset.h | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e22a867..9a8df6a 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,16 +181,6 @@
 #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
 #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
 
-#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
-				 (devid) == PCI_CHIP_I915_GM || \
-				 (devid) == PCI_CHIP_I945_GM || \
-				 (devid) == PCI_CHIP_I945_GME || \
-				 (devid) == PCI_CHIP_I965_GM || \
-				 (devid) == PCI_CHIP_I965_GME || \
-				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
-
 #define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
 				 (devid) == PCI_CHIP_Q45_G || \
 				 (devid) == PCI_CHIP_G45_G || \
-- 
1.8.3.1

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^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 02/12] intel: Introduce an drm_intel_device object
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
  2015-03-05 16:20 ` [PATCH 01/12] intel: Remove unused define IS_MOBILE() Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 03/12] intel: Use drm_intel_device in the gem buffer manager Damien Lespiau
                   ` (11 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

The intention here is to:

  - have a single object that represents a device

  - reuse the kernel i915_pciids.h file so we only one place to update
    and copy the file over.

  - hide the various information about an intel device in that object
    instead of having endless #define in intel_chipset.h. That can be
    basic info like which gen are we talking about or, hopefully soon,
    detailed information about the device (number of
    slices/sub-slices/eus/...)

We'll start slowy by making this API an internal detail at the moment.
Maybe it can grow into something better.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/Makefile.sources |   3 +
 intel/i915_pciids.h    | 289 +++++++++++++++++++++++++++++++++++++++++++++++
 intel/intel_device.c   | 300 +++++++++++++++++++++++++++++++++++++++++++++++++
 intel/intel_device.h   |  99 ++++++++++++++++
 4 files changed, 691 insertions(+)
 create mode 100644 intel/i915_pciids.h
 create mode 100644 intel/intel_device.c
 create mode 100644 intel/intel_device.h

diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 7b2272c..0077a17 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -1,9 +1,12 @@
 LIBDRM_INTEL_FILES := \
+	i915_pciids.h \
 	intel_bufmgr.c \
 	intel_bufmgr_priv.h \
 	intel_bufmgr_fake.c \
 	intel_bufmgr_gem.c \
 	intel_decode.c \
+	intel_device.c \
+	intel_device.h \
 	intel_chipset.h \
 	mm.c \
 	mm.h
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
new file mode 100644
index 0000000..f2e47fd
--- /dev/null
+++ b/intel/i915_pciids.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2013 Intel Corporation
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _I915_PCIIDS_H
+#define _I915_PCIIDS_H
+
+/*
+ * A pci_device_id struct {
+ *	__u32 vendor, device;
+ *      __u32 subvendor, subdevice;
+ *	__u32 class, class_mask;
+ *	kernel_ulong_t driver_data;
+ * };
+ * Don't use C99 here because "class" is reserved and we want to
+ * give userspace flexibility.
+ */
+#define INTEL_VGA_DEVICE(id, info) {		\
+	0x8086,	id,				\
+	~0, ~0,					\
+	0x030000, 0xff0000,			\
+	(unsigned long) info }
+
+#define INTEL_QUANTA_VGA_DEVICE(info) {		\
+	0x8086,	0x16a,				\
+	0x152d,	0x8990,				\
+	0x030000, 0xff0000,			\
+	(unsigned long) info }
+
+#define INTEL_I830_IDS(info)				\
+	INTEL_VGA_DEVICE(0x3577, info)
+
+#define INTEL_I845G_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2562, info)
+
+#define INTEL_I85X_IDS(info)				\
+	INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
+	INTEL_VGA_DEVICE(0x358e, info)
+
+#define INTEL_I865G_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
+
+#define INTEL_I915G_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
+	INTEL_VGA_DEVICE(0x258a, info)  /* E7221_G */
+
+#define INTEL_I915GM_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
+
+#define INTEL_I945G_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
+
+#define INTEL_I945GM_IDS(info)				\
+	INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
+	INTEL_VGA_DEVICE(0x27ae, info)  /* I945_GME */
+
+#define INTEL_I965G_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */	\
+	INTEL_VGA_DEVICE(0x2982, info),	/* G35_G */	\
+	INTEL_VGA_DEVICE(0x2992, info),	/* I965_Q */	\
+	INTEL_VGA_DEVICE(0x29a2, info)	/* I965_G */
+
+#define INTEL_G33_IDS(info)				\
+	INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
+	INTEL_VGA_DEVICE(0x29c2, info),	/* G33_G */ \
+	INTEL_VGA_DEVICE(0x29d2, info)	/* Q33_G */
+
+#define INTEL_I965GM_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2a02, info),	/* I965_GM */ \
+	INTEL_VGA_DEVICE(0x2a12, info)  /* I965_GME */
+
+#define INTEL_GM45_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
+
+#define INTEL_G45_IDS(info)				\
+	INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
+	INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
+	INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
+	INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
+	INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
+	INTEL_VGA_DEVICE(0x2e92, info)	/* B43_G.1 */
+
+#define INTEL_PINEVIEW_IDS(info)			\
+	INTEL_VGA_DEVICE(0xa001, info),			\
+	INTEL_VGA_DEVICE(0xa011, info)
+
+#define INTEL_IRONLAKE_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0042, info)
+
+#define INTEL_IRONLAKE_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0046, info)
+
+#define INTEL_SNB_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0102, info), \
+	INTEL_VGA_DEVICE(0x0112, info), \
+	INTEL_VGA_DEVICE(0x0122, info), \
+	INTEL_VGA_DEVICE(0x010A, info)
+
+#define INTEL_SNB_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0106, info), \
+	INTEL_VGA_DEVICE(0x0116, info), \
+	INTEL_VGA_DEVICE(0x0126, info)
+
+#define INTEL_IVB_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0166, info)  /* GT2 mobile */
+
+#define INTEL_IVB_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
+	INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
+
+#define INTEL_IVB_Q_IDS(info) \
+	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
+
+#define INTEL_HSW_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+	INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+	INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
+	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
+	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
+	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
+	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
+	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
+	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
+
+#define INTEL_HSW_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
+
+#define INTEL_VLV_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0f30, info), \
+	INTEL_VGA_DEVICE(0x0f31, info), \
+	INTEL_VGA_DEVICE(0x0f32, info), \
+	INTEL_VGA_DEVICE(0x0f33, info), \
+	INTEL_VGA_DEVICE(0x0157, info)
+
+#define INTEL_VLV_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0155, info)
+
+#define _INTEL_BDW_M(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+#define _INTEL_BDW_D(gt, id, info) \
+	INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
+
+#define _INTEL_BDW_M_IDS(gt, info) \
+	_INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \
+	_INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \
+	_INTEL_BDW_M(gt, 0x160E, info) /* ULX */
+
+#define _INTEL_BDW_D_IDS(gt, info) \
+	_INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
+	_INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
+
+#define INTEL_BDW_GT12M_IDS(info) \
+	_INTEL_BDW_M_IDS(1, info), \
+	_INTEL_BDW_M_IDS(2, info)
+
+#define INTEL_BDW_GT12D_IDS(info) \
+	_INTEL_BDW_D_IDS(1, info), \
+	_INTEL_BDW_D_IDS(2, info)
+
+#define INTEL_BDW_GT3M_IDS(info) \
+	_INTEL_BDW_M_IDS(3, info)
+
+#define INTEL_BDW_GT3D_IDS(info) \
+	_INTEL_BDW_D_IDS(3, info)
+
+#define INTEL_BDW_RSVDM_IDS(info) \
+	_INTEL_BDW_M_IDS(4, info)
+
+#define INTEL_BDW_RSVDD_IDS(info) \
+	_INTEL_BDW_D_IDS(4, info)
+
+#define INTEL_BDW_M_IDS(info) \
+	INTEL_BDW_GT12M_IDS(info), \
+	INTEL_BDW_GT3M_IDS(info), \
+	INTEL_BDW_RSVDM_IDS(info)
+
+#define INTEL_BDW_D_IDS(info) \
+	INTEL_BDW_GT12D_IDS(info), \
+	INTEL_BDW_GT3D_IDS(info), \
+	INTEL_BDW_RSVDD_IDS(info)
+
+#define INTEL_CHV_IDS(info) \
+	INTEL_VGA_DEVICE(0x22b0, info), \
+	INTEL_VGA_DEVICE(0x22b1, info), \
+	INTEL_VGA_DEVICE(0x22b2, info), \
+	INTEL_VGA_DEVICE(0x22b3, info)
+
+#define INTEL_SKL_GT1_IDS(info)	\
+	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+	INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+	INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
+	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
+
+#define INTEL_SKL_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+	INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \
+
+#define INTEL_SKL_IDS(info) \
+	INTEL_SKL_GT1_IDS(info), \
+	INTEL_SKL_GT2_IDS(info), \
+	INTEL_SKL_GT3_IDS(info)
+
+
+#endif /* _I915_PCIIDS_H */
diff --git a/intel/intel_device.c b/intel/intel_device.c
new file mode 100644
index 0000000..92f498c
--- /dev/null
+++ b/intel/intel_device.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include <xf86drm.h>
+
+#include "i915_drm.h"
+#include "i915_pciids.h"
+#include "intel_device.h"
+
+#ifdef HAVE_VALGRIND
+#include <valgrind.h>
+#include <memcheck.h>
+#define VG(x) x
+#else
+#define VG(x)
+#endif
+
+#define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
+
+#define DBG(...) do {					\
+	if (bufmgr_gem->bufmgr.debug)			\
+		fprintf(stderr, __VA_ARGS__);		\
+} while (0)
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*
+ * The first few fields here have to match the layout of the publicly defined
+ * struct drm_intel_device
+ */
+struct drm_intel_device_info {
+	uint16_t chip, gen;
+};
+
+struct _drm_intel_device {
+	struct drm_intel_device_info info;
+	int fd;
+	uint16_t devid;
+};
+
+#define _to_dev(d)	((struct _drm_intel_device *)(d))
+
+static const struct drm_intel_device_info intel_i830_info = {
+	.chip = DRM_INTEL_CHIP_I830,
+	.gen = 2,
+};
+static const struct drm_intel_device_info intel_i845_info = {
+	.chip = DRM_INTEL_CHIP_I845,
+	.gen = 2,
+};
+static const struct drm_intel_device_info intel_i85x_info = {
+	.chip = DRM_INTEL_CHIP_I85X,
+	.gen = 2,
+};
+static const struct drm_intel_device_info intel_i865_info = {
+	.chip = DRM_INTEL_CHIP_I865,
+	.gen = 2,
+};
+
+static const struct drm_intel_device_info intel_i915_info = {
+	.chip = DRM_INTEL_CHIP_I915,
+	.gen = 3,
+};
+static const struct drm_intel_device_info intel_i945_info = {
+	.chip = DRM_INTEL_CHIP_I945,
+	.gen = 3,
+};
+
+static const struct drm_intel_device_info intel_g33_info = {
+	.chip = DRM_INTEL_CHIP_G33,
+	.gen = 3,
+};
+static const struct drm_intel_device_info intel_pineview_info = {
+	.chip = DRM_INTEL_CHIP_PINEVIEW,
+	.gen = 3,
+};
+
+static const struct drm_intel_device_info intel_i965_info = {
+	.chip = DRM_INTEL_CHIP_I965,
+	.gen = 4,
+};
+
+static const struct drm_intel_device_info intel_g4x_info = {
+	.chip = DRM_INTEL_CHIP_IG4X,
+	.gen = 4,
+};
+
+static const struct drm_intel_device_info intel_ironlake_info = {
+	.chip = DRM_INTEL_CHIP_IRONLAKE,
+	.gen = 5,
+};
+
+static const struct drm_intel_device_info intel_sandybridge_info = {
+	.chip = DRM_INTEL_CHIP_SANDYBRIDGE,
+	.gen = 6,
+};
+
+static const struct drm_intel_device_info intel_ivybridge_info = {
+	.chip = DRM_INTEL_CHIP_IVYBRIDGE,
+	.gen = 7,
+};
+static const struct drm_intel_device_info intel_valleyview_info = {
+	.chip = DRM_INTEL_CHIP_VALLEYVIEW,
+	.gen = 7,
+};
+
+static const struct drm_intel_device_info intel_haswell_info = {
+	.chip = DRM_INTEL_CHIP_HASWELL,
+	.gen = 7,
+};
+
+static const struct drm_intel_device_info intel_broadwell_info = {
+	.chip = DRM_INTEL_CHIP_BROADWELL,
+	.gen = 8,
+};
+
+static const struct drm_intel_device_info intel_cherryview_info = {
+	.chip = DRM_INTEL_CHIP_CHERRYVIEW,
+	.gen = 8,
+};
+
+static const struct drm_intel_device_info intel_skylake_info = {
+	.chip = DRM_INTEL_CHIP_SKYLAKE,
+	.gen = 9,
+};
+
+/*
+ * let's not introduce a dependency on libpciaccess just for the struct
+ * pci_id_match definition...
+ */
+struct device_info_match {
+	uint32_t vendor, device;
+	uint32_t subvendor, subdevice;
+	uint32_t class, class_mask;
+	unsigned long info;
+};
+
+static const struct device_info_match intel_devices[] = {
+	INTEL_I830_IDS(&intel_i830_info),
+	INTEL_I845G_IDS(&intel_i830_info),
+	INTEL_I85X_IDS(&intel_i85x_info),
+	INTEL_I865G_IDS(&intel_i865_info),
+
+	INTEL_I915G_IDS(&intel_i915_info),
+	INTEL_I915GM_IDS(&intel_i915_info),
+	INTEL_I945G_IDS(&intel_i945_info),
+	INTEL_I945GM_IDS(&intel_i945_info),
+
+	INTEL_G33_IDS(&intel_g33_info),
+	INTEL_PINEVIEW_IDS(&intel_pineview_info),
+
+	INTEL_I965G_IDS(&intel_i965_info),
+	INTEL_I965GM_IDS(&intel_i965_info),
+
+	INTEL_G45_IDS(&intel_g4x_info),
+	INTEL_GM45_IDS(&intel_g4x_info),
+
+	INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
+	INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),
+
+	INTEL_SNB_D_IDS(&intel_sandybridge_info),
+	INTEL_SNB_M_IDS(&intel_sandybridge_info),
+
+	INTEL_IVB_D_IDS(&intel_ivybridge_info),
+	INTEL_IVB_M_IDS(&intel_ivybridge_info),
+
+	INTEL_HSW_D_IDS(&intel_haswell_info),
+	INTEL_HSW_M_IDS(&intel_haswell_info),
+
+	INTEL_VLV_D_IDS(&intel_valleyview_info),
+	INTEL_VLV_M_IDS(&intel_valleyview_info),
+
+	INTEL_BDW_D_IDS(&intel_broadwell_info),
+	INTEL_BDW_M_IDS(&intel_broadwell_info),
+
+	INTEL_CHV_IDS(&intel_cherryview_info),
+
+	INTEL_SKL_IDS(&intel_skylake_info),
+};
+
+static struct drm_intel_device *
+_drm_intel_device_populate_info(struct _drm_intel_device *_dev)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(intel_devices); i++) {
+		const struct device_info_match *entry = &intel_devices[i];
+
+		if (_dev->devid != entry->device)
+			continue;
+
+		_dev->info = *(struct drm_intel_device_info *)entry->info;
+		return (struct drm_intel_device *)_dev;
+	}
+
+	free(_dev);
+	return NULL;
+}
+
+struct drm_intel_device *drm_intel_device_new_from_devid(uint16_t devid)
+{
+	struct _drm_intel_device *_dev;
+
+	_dev = calloc(1, sizeof(*_dev));
+	if (_dev == NULL)
+		return NULL;
+
+	_dev->fd = -1;
+	_dev->devid = devid;
+
+	return _drm_intel_device_populate_info(_dev);
+}
+
+/**
+ * Get the PCI ID for the device from the opened DRM fd. This can be overridden
+ * by setting the INTEL_DEVID_OVERRIDE environment variable to the desired ID.
+ */
+static uint16_t _drm_intel_device_get_devid(struct _drm_intel_device *_dev)
+{
+	int devid;
+	struct drm_i915_getparam gp;
+	int ret;
+
+	if (geteuid() == getuid()) {
+		char *devid_override;
+
+		devid_override = getenv("INTEL_DEVID_OVERRIDE");
+		if (devid_override) {
+			_dev->fd = -1;
+			return strtod(devid_override, NULL);
+		}
+	}
+
+	VG_CLEAR(devid);
+	VG_CLEAR(gp);
+	gp.param = I915_PARAM_CHIPSET_ID;
+	gp.value = &devid;
+	ret = drmIoctl(_dev->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+	if (ret)
+		return 0;
+
+	return devid;
+}
+
+struct drm_intel_device *drm_intel_device_new(int fd)
+{
+	struct _drm_intel_device *_dev;
+
+	_dev = calloc(1, sizeof(*_dev));
+	if (_dev == NULL)
+		return NULL;
+
+	_dev->fd = fd;
+	_dev->devid = _drm_intel_device_get_devid(_dev);
+
+	return _drm_intel_device_populate_info(_dev);
+}
+
+void drm_intel_device_free(struct drm_intel_device *dev)
+{
+	free(dev);
+}
+
+uint16_t drm_intel_device_get_devid(struct drm_intel_device *dev)
+{
+	struct _drm_intel_device *_dev = _to_dev(dev);
+
+	return _dev->devid;
+}
diff --git a/intel/intel_device.h b/intel/intel_device.h
new file mode 100644
index 0000000..513e09a
--- /dev/null
+++ b/intel/intel_device.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef __INTEL_DEVICE_H__
+#define __INTEL_DEVICE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* This is not an exhaustive list, but enough for our purposes */
+enum drm_intel_chip {
+
+	/* gen 2 */
+	DRM_INTEL_CHIP_I830,
+	DRM_INTEL_CHIP_I845,
+	DRM_INTEL_CHIP_I85X,
+	DRM_INTEL_CHIP_I865,
+
+	/* gen 3 */
+	DRM_INTEL_CHIP_I915,
+	DRM_INTEL_CHIP_I945,
+	DRM_INTEL_CHIP_G33,
+	DRM_INTEL_CHIP_PINEVIEW,
+
+	/* gen 4 */
+	DRM_INTEL_CHIP_I965,
+	DRM_INTEL_CHIP_IG4X,
+
+	/* gen 5 */
+	DRM_INTEL_CHIP_IRONLAKE,
+
+	/* gen 6 */
+	DRM_INTEL_CHIP_SANDYBRIDGE,
+
+	/* gen 7 */
+	DRM_INTEL_CHIP_IVYBRIDGE,
+	DRM_INTEL_CHIP_HASWELL,
+	DRM_INTEL_CHIP_VALLEYVIEW,
+
+	/* gen 8 */
+	DRM_INTEL_CHIP_BROADWELL,
+	DRM_INTEL_CHIP_CHERRYVIEW,
+
+	/* gen 9 */
+	DRM_INTEL_CHIP_SKYLAKE,
+};
+
+/*
+ * Note that this structure definition doesn't actually hold the internal
+ * fields of the real struct drm_intel_device device allocated by
+ * drm_intel_device_init(). This is to allow direct access to widely used
+ * fields like ->gen without having to go through a function call.
+ *
+ * This means that this structure shouldn't statically or stack allocated.
+ */
+struct drm_intel_device {
+	uint16_t chip, gen;
+};
+
+/*
+ * Allocate a drm_intel_device object from:
+ * - a PCI devid or,
+ * - an opened DRM file descriptor
+ *
+ * The version taking a fd is the preferred one as it allows run-time support
+ * from the kernel.
+ *
+ * The returned object has to be freed with drm_intel_device_free(). When being
+ * instantiated with a file descriptor, the object does not take ownership of
+ * the fd and so _free() will not close that fd.
+ */
+struct drm_intel_device *drm_intel_device_new(int fd);
+struct drm_intel_device *drm_intel_device_new_from_devid(uint16_t devid);
+void drm_intel_device_free(struct drm_intel_device *dev);
+
+/* Retrieve the PCI device id */
+uint16_t drm_intel_device_get_devid(struct drm_intel_device *dev);
+
+#endif /* __INTEL_DEVICE_H__ */
-- 
1.8.3.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 03/12] intel: Use drm_intel_device in the gem buffer manager
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
  2015-03-05 16:20 ` [PATCH 01/12] intel: Remove unused define IS_MOBILE() Damien Lespiau
  2015-03-05 16:20 ` [PATCH 02/12] intel: Introduce an drm_intel_device object Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 04/12] intel: Make drm_intel_decode use a drm_intel_device Damien Lespiau
                   ` (10 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_bufmgr_gem.c | 58 +++++++-----------------------------------------
 1 file changed, 8 insertions(+), 50 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 33d8fbc..72a6ab1 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -60,6 +60,7 @@
 #include "libdrm_lists.h"
 #include "intel_bufmgr.h"
 #include "intel_bufmgr_priv.h"
+#include "intel_device.h"
 #include "intel_chipset.h"
 #include "intel_aub.h"
 #include "string.h"
@@ -120,6 +121,7 @@ typedef struct _drm_intel_bufmgr_gem {
 
 	uint64_t gtt_size;
 	int available_fences;
+	struct drm_intel_device *dev;
 	int pci_device;
 	int gen;
 	unsigned int has_bsd : 1;
@@ -1763,6 +1765,7 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
 		}
 	}
 
+	drm_intel_device_free(bufmgr_gem->dev);
 	free(bufmgr);
 }
 
@@ -3071,37 +3074,6 @@ drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
 	drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
 }
 
-/**
- * Get the PCI ID for the device.  This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- */
-static int
-get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
-{
-	char *devid_override;
-	int devid = 0;
-	int ret;
-	drm_i915_getparam_t gp;
-
-	if (geteuid() == getuid()) {
-		devid_override = getenv("INTEL_DEVID_OVERRIDE");
-		if (devid_override) {
-			bufmgr_gem->no_exec = true;
-			return strtod(devid_override, NULL);
-		}
-	}
-
-	memclear(gp);
-	gp.param = I915_PARAM_CHIPSET_ID;
-	gp.value = &devid;
-	ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
-	if (ret) {
-		fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
-		fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
-	}
-	return devid;
-}
-
 drm_public int
 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
 {
@@ -3469,30 +3441,16 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 			(int)bufmgr_gem->gtt_size / 1024);
 	}
 
-	bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
-
-	if (IS_GEN2(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 2;
-	else if (IS_GEN3(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 3;
-	else if (IS_GEN4(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 4;
-	else if (IS_GEN5(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 5;
-	else if (IS_GEN6(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 6;
-	else if (IS_GEN7(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 7;
-	else if (IS_GEN8(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 8;
-	else if (IS_GEN9(bufmgr_gem->pci_device))
-		bufmgr_gem->gen = 9;
-	else {
+	bufmgr_gem->dev = drm_intel_device_new(fd);
+	if (bufmgr_gem->dev == NULL) {
 		free(bufmgr_gem);
 		bufmgr_gem = NULL;
 		goto exit;
 	}
 
+	bufmgr_gem->pci_device = drm_intel_device_get_devid(bufmgr_gem->dev);
+	bufmgr_gem->gen = bufmgr_gem->dev->gen;
+
 	if (IS_GEN3(bufmgr_gem->pci_device) &&
 	    bufmgr_gem->gtt_size > 256*1024*1024) {
 		/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 04/12] intel: Make drm_intel_decode use a drm_intel_device
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (2 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 03/12] intel: Use drm_intel_device in the gem buffer manager Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 05/12] intel: Use '||' for the boolean or Damien Lespiau
                   ` (9 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_decode.c | 31 ++++++++++++-------------------
 1 file changed, 12 insertions(+), 19 deletions(-)

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 7d5cbe5..9ada2fa 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -35,6 +35,7 @@
 
 #include "libdrm.h"
 #include "xf86drm.h"
+#include "intel_device.h"
 #include "intel_chipset.h"
 #include "intel_bufmgr.h"
 
@@ -43,6 +44,9 @@ struct drm_intel_decode {
 	/** stdio file where the output should land.  Defaults to stdout. */
 	FILE *out;
 
+	/** Description of the GPU */
+	struct drm_intel_device *dev;
+
 	/** PCI device ID. */
 	uint32_t devid;
 
@@ -3826,27 +3830,15 @@ drm_intel_decode_context_alloc(uint32_t devid)
 	if (!ctx)
 		return NULL;
 
+	ctx->dev = drm_intel_device_new_from_devid(devid);
+	if (!ctx->dev) {
+		free(ctx);
+		return NULL;
+	}
+
 	ctx->devid = devid;
 	ctx->out = stdout;
-
-	if (IS_GEN9(devid))
-		ctx->gen = 9;
-	else if (IS_GEN8(devid))
-		ctx->gen = 8;
-	else if (IS_GEN7(devid))
-		ctx->gen = 7;
-	else if (IS_GEN6(devid))
-		ctx->gen = 6;
-	else if (IS_GEN5(devid))
-		ctx->gen = 5;
-	else if (IS_GEN4(devid))
-		ctx->gen = 4;
-	else if (IS_9XX(devid))
-		ctx->gen = 3;
-	else {
-		assert(IS_GEN2(devid));
-		ctx->gen = 2;
-	}
+	ctx->gen = ctx->dev->gen;
 
 	return ctx;
 }
@@ -3854,6 +3846,7 @@ drm_intel_decode_context_alloc(uint32_t devid)
 drm_public void
 drm_intel_decode_context_free(struct drm_intel_decode *ctx)
 {
+	drm_intel_device_free(ctx->dev);
 	free(ctx);
 }
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 05/12] intel: Use '||' for the boolean or
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (3 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 04/12] intel: Make drm_intel_decode use a drm_intel_device Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 06/12] intel: Kill the IS_9XX() macro Damien Lespiau
                   ` (8 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

While the bitwise operator should do the right thing here, it's probably
better to use the logical or here, at least to not cause a 'wtf' when
reading the code.

At the same time, get rid of unnecessary '()'.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_bufmgr_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 72a6ab1..8570a30 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3494,8 +3494,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 		/* Kernel does not supports HAS_LLC query, fallback to GPU
 		 * generation detection and assume that we have LLC on GEN6/7
 		 */
-		bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
-				IS_GEN7(bufmgr_gem->pci_device));
+		bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->pci_device) ||
+				      IS_GEN7(bufmgr_gem->pci_device);
 	} else
 		bufmgr_gem->has_llc = *gp.value;
 
-- 
1.8.3.1

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^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 06/12] intel: Kill the IS_9XX() macro
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (4 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 05/12] intel: Use '||' for the boolean or Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 07/12] intel: Kill the IS_GEN4() macro Damien Lespiau
                   ` (7 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

IS_9XX() has grown to mean gen >= 3. It was only used in a single test:

  (IS_9XX && !IS_GEN3)

Which has then be replaced with gen >= 4.

The code in that area was idented a bit weirdly, so do a pass on that as
well.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_chipset.h |  9 ---------
 intel/intel_decode.c  | 13 +++++--------
 2 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 9a8df6a..a8a2b0e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -354,13 +354,4 @@
 
 #define IS_GEN9(devid)		IS_SKYLAKE(devid)
 
-#define IS_9XX(dev)		(IS_GEN3(dev) || \
-				 IS_GEN4(dev) || \
-				 IS_GEN5(dev) || \
-				 IS_GEN6(dev) || \
-				 IS_GEN7(dev) || \
-				 IS_GEN8(dev) || \
-				 IS_GEN9(dev))
-
-
 #endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 9ada2fa..2fd2cc5 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3949,15 +3949,12 @@ drm_intel_decode(struct drm_intel_decode *ctx)
 			index += decode_2d(ctx);
 			break;
 		case 0x3:
-			if (IS_9XX(devid) && !IS_GEN3(devid)) {
-				index +=
-				    decode_3d_965(ctx);
-			} else if (IS_GEN3(devid)) {
+			if (ctx->dev->gen >= 4)
+				index += decode_3d_965(ctx);
+			else if (IS_GEN3(devid))
 				index += decode_3d(ctx);
-			} else {
-				index +=
-				    decode_3d_i830(ctx);
-			}
+			else
+				index += decode_3d_i830(ctx);
 			break;
 		default:
 			instr_out(ctx, index, "UNKNOWN\n");
-- 
1.8.3.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 07/12] intel: Kill the IS_GEN4() macro
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (5 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 06/12] intel: Kill the IS_9XX() macro Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 08/12] intel: Remove direct usage of IS_915() Damien Lespiau
                   ` (6 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Turns out nobody was using it, nor the underlying defines.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_chipset.h | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index a8a2b0e..241d700 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,13 +181,6 @@
 #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
 #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
 
-#define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
-				 (devid) == PCI_CHIP_Q45_G || \
-				 (devid) == PCI_CHIP_G45_G || \
-				 (devid) == PCI_CHIP_G41_G)
-#define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
-
 #define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
 #define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
 
@@ -214,14 +207,6 @@
 
 #define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
 
-#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
-				 (devid) == PCI_CHIP_I965_Q || \
-				 (devid) == PCI_CHIP_I965_G_1 || \
-				 (devid) == PCI_CHIP_I965_GM || \
-				 (devid) == PCI_CHIP_I965_GME || \
-				 (devid) == PCI_CHIP_I946_GZ || \
-				 IS_G4X(devid))
-
 #define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
 
 #define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
-- 
1.8.3.1

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http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 08/12] intel: Remove direct usage of IS_915()
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (6 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 07/12] intel: Kill the IS_GEN4() macro Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument Damien Lespiau
                   ` (5 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

One more step towards getting rid of intel_chipset.h. The slightly
tricky bit here is that I don't want to leave defines like IS_CHIP() or
IS_GEN4() is a file that can potentially become a public header.
intel_device_priv.h was introduced then.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/Makefile.sources    |  1 +
 intel/intel_bufmgr_gem.c  |  6 +++---
 intel/intel_device_priv.h | 35 +++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 intel/intel_device_priv.h

diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 0077a17..2f8398b 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -7,6 +7,7 @@ LIBDRM_INTEL_FILES := \
 	intel_decode.c \
 	intel_device.c \
 	intel_device.h \
+	intel_device_priv.h \
 	intel_chipset.h \
 	mm.c \
 	mm.h
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 8570a30..58543a2 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -60,7 +60,7 @@
 #include "libdrm_lists.h"
 #include "intel_bufmgr.h"
 #include "intel_bufmgr_priv.h"
-#include "intel_device.h"
+#include "intel_device_priv.h"
 #include "intel_chipset.h"
 #include "intel_aub.h"
 #include "string.h"
@@ -338,7 +338,7 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
 		return ALIGN(pitch, 64);
 
 	if (*tiling_mode == I915_TILING_X
-			|| (IS_915(bufmgr_gem->pci_device)
+			|| (IS_CHIP(bufmgr_gem->dev, I915)
 			    && *tiling_mode == I915_TILING_Y))
 		tile_width = 512;
 	else
@@ -843,7 +843,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 		if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
 			height_alignment = 16;
 		else if (tiling == I915_TILING_X
-			|| (IS_915(bufmgr_gem->pci_device)
+			|| (IS_CHIP(bufmgr_gem->dev, I915)
 			    && tiling == I915_TILING_Y))
 			height_alignment = 8;
 		else if (tiling == I915_TILING_Y)
diff --git a/intel/intel_device_priv.h b/intel/intel_device_priv.h
new file mode 100644
index 0000000..87dc1dc
--- /dev/null
+++ b/intel/intel_device_priv.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef __INTEL_DEVICE_PRIV_H__
+#define __INTEL_DEVICE_PRIV_H__
+
+#include "intel_device.h"
+
+/*
+ * Shorthand defines. These are not namespaced and shouldn't be in a public
+ * header, hence a _priv.h one for internal use.
+ */
+#define IS_CHIP(dev, id)	((dev)->chip == DRM_INTEL_CHIP_ ## id)
+
+#endif /* __INTEL_DEVICE_PRIV_H__ */
-- 
1.8.3.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (7 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 08/12] intel: Remove direct usage of IS_915() Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 18:41   ` Ian Romanick
  2015-03-05 16:20 ` [PATCH 10/12] intel: Make test_decode fail gracefully the decode context is NULL Damien Lespiau
                   ` (4 subsequent siblings)
  13 siblings, 1 reply; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Time to switch over all the IS_GENX() macros to the new device object.
Nothing more than a mechanical search & replace here.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/intel_bufmgr_gem.c  |   7 +-
 intel/intel_chipset.h     | 158 ----------------------------------------------
 intel/intel_decode.c      |  41 ++++++------
 intel/intel_device_priv.h |   8 +++
 4 files changed, 31 insertions(+), 183 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 58543a2..011fa5b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3451,8 +3451,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 	bufmgr_gem->pci_device = drm_intel_device_get_devid(bufmgr_gem->dev);
 	bufmgr_gem->gen = bufmgr_gem->dev->gen;
 
-	if (IS_GEN3(bufmgr_gem->pci_device) &&
-	    bufmgr_gem->gtt_size > 256*1024*1024) {
+	if (IS_GEN3(bufmgr_gem->dev) && bufmgr_gem->gtt_size > 256*1024*1024) {
 		/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
 		 * be used for tiled blits. To simplify the accounting, just
 		 * substract the unmappable part (fixed to 256MB on all known
@@ -3494,8 +3493,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 		/* Kernel does not supports HAS_LLC query, fallback to GPU
 		 * generation detection and assume that we have LLC on GEN6/7
 		 */
-		bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->pci_device) ||
-				      IS_GEN7(bufmgr_gem->pci_device);
+		bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->dev) ||
+				      IS_GEN7(bufmgr_gem->dev);
 	} else
 		bufmgr_gem->has_llc = *gp.value;
 
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 241d700..134c877 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,162 +181,4 @@
 #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
 #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
 
-#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
-#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
-
-#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
-				 (devid) == PCI_CHIP_E7221_G || \
-				 (devid) == PCI_CHIP_I915_GM)
-
-#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
-				 (devid) == PCI_CHIP_I945_GME)
-
-#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
-				 (devid) == PCI_CHIP_I945_GM || \
-				 (devid) == PCI_CHIP_I945_GME || \
-				 IS_G33(devid))
-
-#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
-				 (devid) == PCI_CHIP_Q33_G || \
-				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
-				 (devid) == PCI_CHIP_845_G || \
-				 (devid) == PCI_CHIP_I855_GM || \
-				 (devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
-
-#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
-				 IS_HASWELL(devid) || \
-				 IS_VALLEYVIEW(devid))
-
-#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
-				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-
-#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
-				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
-				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
-				 (devid) == PCI_CHIP_VALLEYVIEW_3)
-
-#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
-#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
-#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
-
-#define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
-				 IS_HSW_GT2(devid) || \
-				 IS_HSW_GT3(devid))
-
-#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
-				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
-				((devid & 0x000f) == BDW_SPARE) ? 1 : \
-				((devid & 0x000f) == BDW_ULT) ? 1 : \
-				((devid & 0x000f) == BDW_IRIS) ? 1 : \
-				((devid & 0x000f) == BDW_SERVER) ? 1 : \
-				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
-				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
-
-#define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
-				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
-				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
-				 (devid) == PCI_CHIP_CHERRYVIEW_3)
-
-#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
-				 IS_CHERRYVIEW(devid))
-
-#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
-
-#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
-
-#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
-
-#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
-				 IS_SKL_GT2(devid) || \
-				 IS_SKL_GT3(devid))
-
-#define IS_GEN9(devid)		IS_SKYLAKE(devid)
-
 #endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2fd2cc5..abe689c 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -35,7 +35,7 @@
 
 #include "libdrm.h"
 #include "xf86drm.h"
-#include "intel_device.h"
+#include "intel_device_priv.h"
 #include "intel_chipset.h"
 #include "intel_bufmgr.h"
 
@@ -1277,7 +1277,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
 	const char *format, *zformat, *type;
 	uint32_t opcode;
 	uint32_t *data = ctx->data;
-	uint32_t devid = ctx->devid;
+	struct drm_intel_device *dev = ctx->dev;
 
 	struct {
 		uint32_t opcode;
@@ -1353,7 +1353,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
 		for (word = 0; word <= 8; word++) {
 			if (data[0] & (1 << (4 + word))) {
 				/* save vertex state for decode */
-				if (!IS_GEN2(devid)) {
+				if (!IS_GEN2(dev)) {
 					int tex_num;
 
 					if (word == 2) {
@@ -2029,7 +2029,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
 		}
 		return len;
 	case 0x01:
-		if (IS_GEN2(devid))
+		if (IS_GEN2(dev))
 			break;
 		instr_out(ctx, 0, "3DSTATE_SAMPLER_STATE\n");
 		instr_out(ctx, 1, "mask\n");
@@ -2254,7 +2254,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
 
 	for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) {
 		opcode_3d_1d = &opcodes_3d_1d[idx];
-		if (opcode_3d_1d->i830_only && !IS_GEN2(devid))
+		if (opcode_3d_1d->i830_only && !IS_GEN2(dev))
 			continue;
 
 		if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
@@ -3144,7 +3144,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 	unsigned int i, j, sba_len;
 	const char *desc1 = NULL;
 	uint32_t *data = ctx->data;
-	uint32_t devid = ctx->devid;
+	struct drm_intel_device *dev = ctx->dev;
 
 	struct {
 		uint32_t opcode;
@@ -3297,9 +3297,9 @@ decode_3d_965(struct drm_intel_decode *ctx)
 		instr_out(ctx, 0, "STATE_BASE_ADDRESS\n");
 		i++;
 
-		if (IS_GEN6(devid) || IS_GEN7(devid))
+		if (IS_GEN6(dev) || IS_GEN7(dev))
 			sba_len = 10;
-		else if (IS_GEN5(devid))
+		else if (IS_GEN5(dev))
 			sba_len = 8;
 		else
 			sba_len = 6;
@@ -3308,17 +3308,17 @@ decode_3d_965(struct drm_intel_decode *ctx)
 
 		state_base_out(ctx, i++, "general");
 		state_base_out(ctx, i++, "surface");
-		if (IS_GEN6(devid) || IS_GEN7(devid))
+		if (IS_GEN6(dev) || IS_GEN7(dev))
 			state_base_out(ctx, i++, "dynamic");
 		state_base_out(ctx, i++, "indirect");
-		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+		if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
 			state_base_out(ctx, i++, "instruction");
 
 		state_max_out(ctx, i++, "general");
-		if (IS_GEN6(devid) || IS_GEN7(devid))
+		if (IS_GEN6(dev) || IS_GEN7(dev))
 			state_max_out(ctx, i++, "dynamic");
 		state_max_out(ctx, i++, "indirect");
-		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+		if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
 			state_max_out(ctx, i++, "instruction");
 
 		return len;
@@ -3387,7 +3387,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 
 		for (i = 1; i < len;) {
 			int idx, access;
-			if (IS_GEN6(devid)) {
+			if (IS_GEN6(dev)) {
 				idx = 26;
 				access = 20;
 			} else {
@@ -3414,8 +3414,8 @@ decode_3d_965(struct drm_intel_decode *ctx)
 			instr_out(ctx, i,
 				  "buffer %d: %svalid, type 0x%04x, "
 				  "src offset 0x%04x bytes\n",
-				  data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
-				  data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
+				  data[i] >> ((IS_GEN6(dev) || IS_GEN7(dev)) ? 26 : 27),
+				  data[i] & (1 << ((IS_GEN6(dev) || IS_GEN7(dev)) ? 25 : 26)) ?
 				  "" : "in", (data[i] >> 16) & 0x1ff,
 				  data[i] & 0x07ff);
 			i++;
@@ -3599,7 +3599,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 
 	case 0x7905:
 		instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n");
-		if (IS_GEN5(devid) || IS_GEN6(devid))
+		if (IS_GEN5(dev) || IS_GEN6(dev))
 			instr_out(ctx, 1,
 				  "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
 				  get_965_surfacetype(data[1] >> 29),
@@ -3623,7 +3623,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 		if (len >= 6)
 			instr_out(ctx, 5, "\n");
 		if (len >= 7) {
-			if (IS_GEN6(devid))
+			if (IS_GEN6(dev))
 				instr_out(ctx, 6, "\n");
 			else
 				instr_out(ctx, 6,
@@ -3633,7 +3633,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 		return len;
 
 	case 0x7a00:
-		if (IS_GEN6(devid) || IS_GEN7(devid)) {
+		if (IS_GEN6(dev) || IS_GEN7(dev)) {
 			unsigned int i;
 			if (len != 4 && len != 5)
 				fprintf(out, "Bad count in PIPE_CONTROL\n");
@@ -3893,9 +3893,9 @@ drm_intel_decode(struct drm_intel_decode *ctx)
 {
 	int ret;
 	unsigned int index = 0;
-	uint32_t devid;
 	int size = ctx->base_count * 4;
 	void *temp;
+	struct drm_intel_device *dev = ctx->dev;
 
 	if (!ctx)
 		return;
@@ -3912,7 +3912,6 @@ drm_intel_decode(struct drm_intel_decode *ctx)
 	ctx->hw_offset = ctx->base_hw_offset;
 	ctx->count = ctx->base_count;
 
-	devid = ctx->devid;
 	head_offset = ctx->head;
 	tail_offset = ctx->tail;
 	out = ctx->out;
@@ -3951,7 +3950,7 @@ drm_intel_decode(struct drm_intel_decode *ctx)
 		case 0x3:
 			if (ctx->dev->gen >= 4)
 				index += decode_3d_965(ctx);
-			else if (IS_GEN3(devid))
+			else if (IS_GEN3(dev))
 				index += decode_3d(ctx);
 			else
 				index += decode_3d_i830(ctx);
diff --git a/intel/intel_device_priv.h b/intel/intel_device_priv.h
index 87dc1dc..d1bc523 100644
--- a/intel/intel_device_priv.h
+++ b/intel/intel_device_priv.h
@@ -31,5 +31,13 @@
  * header, hence a _priv.h one for internal use.
  */
 #define IS_CHIP(dev, id)	((dev)->chip == DRM_INTEL_CHIP_ ## id)
+#define IS_GEN2(dev)		((dev)->gen == 2)
+#define IS_GEN3(dev)		((dev)->gen == 3)
+#define IS_GEN4(dev)		((dev)->gen == 4)
+#define IS_GEN5(dev)		((dev)->gen == 5)
+#define IS_GEN6(dev)		((dev)->gen == 6)
+#define IS_GEN7(dev)		((dev)->gen == 7)
+#define IS_GEN8(dev)		((dev)->gen == 8)
+#define IS_GEN9(dev)		((dev)->gen == 9)
 
 #endif /* __INTEL_DEVICE_PRIV_H__ */
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
  2015-03-05 16:20 ` [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument Damien Lespiau
@ 2015-03-05 18:41   ` Ian Romanick
  2015-03-05 18:45     ` Damien Lespiau
  0 siblings, 1 reply; 18+ messages in thread
From: Ian Romanick @ 2015-03-05 18:41 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx; +Cc: dri-devel

On 03/05/2015 08:20 AM, Damien Lespiau wrote:
> Time to switch over all the IS_GENX() macros to the new device object.
> Nothing more than a mechanical search & replace here.

Hmm... why not just do the comparisons directly?  The macros seem
superfluous.

> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  intel/intel_bufmgr_gem.c  |   7 +-
>  intel/intel_chipset.h     | 158 ----------------------------------------------
>  intel/intel_decode.c      |  41 ++++++------
>  intel/intel_device_priv.h |   8 +++
>  4 files changed, 31 insertions(+), 183 deletions(-)
> 
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 58543a2..011fa5b 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -3451,8 +3451,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
>  	bufmgr_gem->pci_device = drm_intel_device_get_devid(bufmgr_gem->dev);
>  	bufmgr_gem->gen = bufmgr_gem->dev->gen;
>  
> -	if (IS_GEN3(bufmgr_gem->pci_device) &&
> -	    bufmgr_gem->gtt_size > 256*1024*1024) {
> +	if (IS_GEN3(bufmgr_gem->dev) && bufmgr_gem->gtt_size > 256*1024*1024) {
>  		/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
>  		 * be used for tiled blits. To simplify the accounting, just
>  		 * substract the unmappable part (fixed to 256MB on all known
> @@ -3494,8 +3493,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
>  		/* Kernel does not supports HAS_LLC query, fallback to GPU
>  		 * generation detection and assume that we have LLC on GEN6/7
>  		 */
> -		bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->pci_device) ||
> -				      IS_GEN7(bufmgr_gem->pci_device);
> +		bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->dev) ||
> +				      IS_GEN7(bufmgr_gem->dev);
>  	} else
>  		bufmgr_gem->has_llc = *gp.value;
>  
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 241d700..134c877 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -181,162 +181,4 @@
>  #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
>  #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
>  
> -#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
> -#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
> -
> -#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
> -				 (devid) == PCI_CHIP_E7221_G || \
> -				 (devid) == PCI_CHIP_I915_GM)
> -
> -#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
> -				 (devid) == PCI_CHIP_I945_GME)
> -
> -#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
> -				 (devid) == PCI_CHIP_I945_GM || \
> -				 (devid) == PCI_CHIP_I945_GME || \
> -				 IS_G33(devid))
> -
> -#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
> -				 (devid) == PCI_CHIP_Q33_G || \
> -				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
> -
> -#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
> -				 (devid) == PCI_CHIP_845_G || \
> -				 (devid) == PCI_CHIP_I855_GM || \
> -				 (devid) == PCI_CHIP_I865_G)
> -
> -#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
> -
> -#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
> -
> -#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
> -				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
> -
> -#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
> -				 IS_HASWELL(devid) || \
> -				 IS_VALLEYVIEW(devid))
> -
> -#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
> -				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
> -				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
> -				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
> -				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
> -				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
> -
> -#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
> -				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
> -				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
> -				 (devid) == PCI_CHIP_VALLEYVIEW_3)
> -
> -#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
> -#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
> -#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
> -				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
> -
> -#define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
> -				 IS_HSW_GT2(devid) || \
> -				 IS_HSW_GT3(devid))
> -
> -#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
> -				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
> -				((devid & 0x000f) == BDW_SPARE) ? 1 : \
> -				((devid & 0x000f) == BDW_ULT) ? 1 : \
> -				((devid & 0x000f) == BDW_IRIS) ? 1 : \
> -				((devid & 0x000f) == BDW_SERVER) ? 1 : \
> -				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
> -				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
> -
> -#define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
> -				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
> -				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
> -				 (devid) == PCI_CHIP_CHERRYVIEW_3)
> -
> -#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
> -				 IS_CHERRYVIEW(devid))
> -
> -#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
> -
> -#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
> -
> -#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
> -				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
> -
> -#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
> -				 IS_SKL_GT2(devid) || \
> -				 IS_SKL_GT3(devid))
> -
> -#define IS_GEN9(devid)		IS_SKYLAKE(devid)
> -
>  #endif /* _INTEL_CHIPSET_H */
> diff --git a/intel/intel_decode.c b/intel/intel_decode.c
> index 2fd2cc5..abe689c 100644
> --- a/intel/intel_decode.c
> +++ b/intel/intel_decode.c
> @@ -35,7 +35,7 @@
>  
>  #include "libdrm.h"
>  #include "xf86drm.h"
> -#include "intel_device.h"
> +#include "intel_device_priv.h"
>  #include "intel_chipset.h"
>  #include "intel_bufmgr.h"
>  
> @@ -1277,7 +1277,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
>  	const char *format, *zformat, *type;
>  	uint32_t opcode;
>  	uint32_t *data = ctx->data;
> -	uint32_t devid = ctx->devid;
> +	struct drm_intel_device *dev = ctx->dev;
>  
>  	struct {
>  		uint32_t opcode;
> @@ -1353,7 +1353,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
>  		for (word = 0; word <= 8; word++) {
>  			if (data[0] & (1 << (4 + word))) {
>  				/* save vertex state for decode */
> -				if (!IS_GEN2(devid)) {
> +				if (!IS_GEN2(dev)) {
>  					int tex_num;
>  
>  					if (word == 2) {
> @@ -2029,7 +2029,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
>  		}
>  		return len;
>  	case 0x01:
> -		if (IS_GEN2(devid))
> +		if (IS_GEN2(dev))
>  			break;
>  		instr_out(ctx, 0, "3DSTATE_SAMPLER_STATE\n");
>  		instr_out(ctx, 1, "mask\n");
> @@ -2254,7 +2254,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
>  
>  	for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) {
>  		opcode_3d_1d = &opcodes_3d_1d[idx];
> -		if (opcode_3d_1d->i830_only && !IS_GEN2(devid))
> +		if (opcode_3d_1d->i830_only && !IS_GEN2(dev))
>  			continue;
>  
>  		if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
> @@ -3144,7 +3144,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  	unsigned int i, j, sba_len;
>  	const char *desc1 = NULL;
>  	uint32_t *data = ctx->data;
> -	uint32_t devid = ctx->devid;
> +	struct drm_intel_device *dev = ctx->dev;
>  
>  	struct {
>  		uint32_t opcode;
> @@ -3297,9 +3297,9 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  		instr_out(ctx, 0, "STATE_BASE_ADDRESS\n");
>  		i++;
>  
> -		if (IS_GEN6(devid) || IS_GEN7(devid))
> +		if (IS_GEN6(dev) || IS_GEN7(dev))
>  			sba_len = 10;
> -		else if (IS_GEN5(devid))
> +		else if (IS_GEN5(dev))
>  			sba_len = 8;
>  		else
>  			sba_len = 6;
> @@ -3308,17 +3308,17 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  
>  		state_base_out(ctx, i++, "general");
>  		state_base_out(ctx, i++, "surface");
> -		if (IS_GEN6(devid) || IS_GEN7(devid))
> +		if (IS_GEN6(dev) || IS_GEN7(dev))
>  			state_base_out(ctx, i++, "dynamic");
>  		state_base_out(ctx, i++, "indirect");
> -		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
> +		if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
>  			state_base_out(ctx, i++, "instruction");
>  
>  		state_max_out(ctx, i++, "general");
> -		if (IS_GEN6(devid) || IS_GEN7(devid))
> +		if (IS_GEN6(dev) || IS_GEN7(dev))
>  			state_max_out(ctx, i++, "dynamic");
>  		state_max_out(ctx, i++, "indirect");
> -		if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
> +		if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
>  			state_max_out(ctx, i++, "instruction");
>  
>  		return len;
> @@ -3387,7 +3387,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  
>  		for (i = 1; i < len;) {
>  			int idx, access;
> -			if (IS_GEN6(devid)) {
> +			if (IS_GEN6(dev)) {
>  				idx = 26;
>  				access = 20;
>  			} else {
> @@ -3414,8 +3414,8 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  			instr_out(ctx, i,
>  				  "buffer %d: %svalid, type 0x%04x, "
>  				  "src offset 0x%04x bytes\n",
> -				  data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
> -				  data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
> +				  data[i] >> ((IS_GEN6(dev) || IS_GEN7(dev)) ? 26 : 27),
> +				  data[i] & (1 << ((IS_GEN6(dev) || IS_GEN7(dev)) ? 25 : 26)) ?
>  				  "" : "in", (data[i] >> 16) & 0x1ff,
>  				  data[i] & 0x07ff);
>  			i++;
> @@ -3599,7 +3599,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  
>  	case 0x7905:
>  		instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n");
> -		if (IS_GEN5(devid) || IS_GEN6(devid))
> +		if (IS_GEN5(dev) || IS_GEN6(dev))
>  			instr_out(ctx, 1,
>  				  "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
>  				  get_965_surfacetype(data[1] >> 29),
> @@ -3623,7 +3623,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  		if (len >= 6)
>  			instr_out(ctx, 5, "\n");
>  		if (len >= 7) {
> -			if (IS_GEN6(devid))
> +			if (IS_GEN6(dev))
>  				instr_out(ctx, 6, "\n");
>  			else
>  				instr_out(ctx, 6,
> @@ -3633,7 +3633,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
>  		return len;
>  
>  	case 0x7a00:
> -		if (IS_GEN6(devid) || IS_GEN7(devid)) {
> +		if (IS_GEN6(dev) || IS_GEN7(dev)) {
>  			unsigned int i;
>  			if (len != 4 && len != 5)
>  				fprintf(out, "Bad count in PIPE_CONTROL\n");
> @@ -3893,9 +3893,9 @@ drm_intel_decode(struct drm_intel_decode *ctx)
>  {
>  	int ret;
>  	unsigned int index = 0;
> -	uint32_t devid;
>  	int size = ctx->base_count * 4;
>  	void *temp;
> +	struct drm_intel_device *dev = ctx->dev;
>  
>  	if (!ctx)
>  		return;
> @@ -3912,7 +3912,6 @@ drm_intel_decode(struct drm_intel_decode *ctx)
>  	ctx->hw_offset = ctx->base_hw_offset;
>  	ctx->count = ctx->base_count;
>  
> -	devid = ctx->devid;
>  	head_offset = ctx->head;
>  	tail_offset = ctx->tail;
>  	out = ctx->out;
> @@ -3951,7 +3950,7 @@ drm_intel_decode(struct drm_intel_decode *ctx)
>  		case 0x3:
>  			if (ctx->dev->gen >= 4)
>  				index += decode_3d_965(ctx);
> -			else if (IS_GEN3(devid))
> +			else if (IS_GEN3(dev))
>  				index += decode_3d(ctx);
>  			else
>  				index += decode_3d_i830(ctx);
> diff --git a/intel/intel_device_priv.h b/intel/intel_device_priv.h
> index 87dc1dc..d1bc523 100644
> --- a/intel/intel_device_priv.h
> +++ b/intel/intel_device_priv.h
> @@ -31,5 +31,13 @@
>   * header, hence a _priv.h one for internal use.
>   */
>  #define IS_CHIP(dev, id)	((dev)->chip == DRM_INTEL_CHIP_ ## id)
> +#define IS_GEN2(dev)		((dev)->gen == 2)
> +#define IS_GEN3(dev)		((dev)->gen == 3)
> +#define IS_GEN4(dev)		((dev)->gen == 4)
> +#define IS_GEN5(dev)		((dev)->gen == 5)
> +#define IS_GEN6(dev)		((dev)->gen == 6)
> +#define IS_GEN7(dev)		((dev)->gen == 7)
> +#define IS_GEN8(dev)		((dev)->gen == 8)
> +#define IS_GEN9(dev)		((dev)->gen == 9)
>  
>  #endif /* __INTEL_DEVICE_PRIV_H__ */
> 

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
  2015-03-05 18:41   ` Ian Romanick
@ 2015-03-05 18:45     ` Damien Lespiau
  0 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 18:45 UTC (permalink / raw)
  To: Ian Romanick; +Cc: intel-gfx, dri-devel

On Thu, Mar 05, 2015 at 10:41:19AM -0800, Ian Romanick wrote:
> On 03/05/2015 08:20 AM, Damien Lespiau wrote:
> > Time to switch over all the IS_GENX() macros to the new device object.
> > Nothing more than a mechanical search & replace here.
> 
> Hmm... why not just do the comparisons directly?  The macros seem
> superfluous.

I asked myself the same question as well and then went for the solution
that wasn't going to change what was already there too much. I really
have no opinion either way.

-- 
Damien
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH 10/12] intel: Make test_decode fail gracefully the decode context is NULL
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (8 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 11/12] intel: Make test_decode not depend on intel_chipset.h Damien Lespiau
                   ` (3 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

If, for some reason, we couldn't create the decode context, exit,
instead of segfaulting.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/test_decode.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/intel/test_decode.c b/intel/test_decode.c
index 93f47ef..1ffd829 100644
--- a/intel/test_decode.c
+++ b/intel/test_decode.c
@@ -182,6 +182,11 @@ main(int argc, char **argv)
 	devid = infer_devid(argv[1]);
 
 	ctx = drm_intel_decode_context_alloc(devid);
+	if (!ctx) {
+		fprintf(stderr, "Couldn't create decode context for 0x%04x\n",
+			devid);
+		exit(1);
+	}
 
 	if (argc == 3) {
 		if (strcmp(argv[2], "-dump") == 0)
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 11/12] intel: Make test_decode not depend on intel_chipset.h
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (9 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 10/12] intel: Make test_decode fail gracefully the decode context is NULL Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 16:20 ` [PATCH 12/12] intel: Remove intel_chipset.h Damien Lespiau
                   ` (2 subsequent siblings)
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

We were pulling a few PCI ids, we can just hardcode them, it doesn't
change much.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/test_decode.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/intel/test_decode.c b/intel/test_decode.c
index 1ffd829..b9897b3 100644
--- a/intel/test_decode.c
+++ b/intel/test_decode.c
@@ -36,7 +36,6 @@
 
 #include "libdrm.h"
 #include "intel_bufmgr.h"
-#include "intel_chipset.h"
 
 #define HW_OFFSET 0x12300000
 
@@ -147,9 +146,9 @@ infer_devid(const char *batch_filename)
 		{ "945",  0x2772},
 		{ "gen4", 0x2a02 },
 		{ "gm45", 0x2a42 },
-		{ "gen5", PCI_CHIP_ILD_G },
-		{ "gen6", PCI_CHIP_SANDYBRIDGE_GT2 },
-		{ "gen7", PCI_CHIP_IVYBRIDGE_GT2 },
+		{ "gen5", 0x0042 },
+		{ "gen6", 0x0112 },
+		{ "gen7", 0x0162 },
 		{ "gen8", 0x1616 },
 		{ NULL, 0 },
 	};
-- 
1.8.3.1

_______________________________________________
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 12/12] intel: Remove intel_chipset.h
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (10 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 11/12] intel: Make test_decode not depend on intel_chipset.h Damien Lespiau
@ 2015-03-05 16:20 ` Damien Lespiau
  2015-03-05 18:44 ` [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Ian Romanick
  2015-03-06 14:10 ` Emil Velikov
  13 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-05 16:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel

Finally, we can remove this file now that everything is using
drm_intel_device.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 intel/Makefile.sources   |   1 -
 intel/intel_bufmgr_gem.c |   1 -
 intel/intel_chipset.h    | 184 -----------------------------------------------
 intel/intel_decode.c     |   1 -
 4 files changed, 187 deletions(-)
 delete mode 100644 intel/intel_chipset.h

diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 2f8398b..b58ca4f 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -8,7 +8,6 @@ LIBDRM_INTEL_FILES := \
 	intel_device.c \
 	intel_device.h \
 	intel_device_priv.h \
-	intel_chipset.h \
 	mm.c \
 	mm.h
 
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 011fa5b..d0119fc 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -61,7 +61,6 @@
 #include "intel_bufmgr.h"
 #include "intel_bufmgr_priv.h"
 #include "intel_device_priv.h"
-#include "intel_chipset.h"
 #include "intel_aub.h"
 #include "string.h"
 
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
deleted file mode 100644
index 134c877..0000000
--- a/intel/intel_chipset.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _INTEL_CHIPSET_H
-#define _INTEL_CHIPSET_H
-
-#define PCI_CHIP_I810			0x7121
-#define PCI_CHIP_I810_DC100		0x7123
-#define PCI_CHIP_I810_E			0x7125
-#define PCI_CHIP_I815			0x1132
-
-#define PCI_CHIP_I830_M			0x3577
-#define PCI_CHIP_845_G			0x2562
-#define PCI_CHIP_I855_GM		0x3582
-#define PCI_CHIP_I865_G			0x2572
-
-#define PCI_CHIP_I915_G			0x2582
-#define PCI_CHIP_E7221_G		0x258A
-#define PCI_CHIP_I915_GM		0x2592
-#define PCI_CHIP_I945_G			0x2772
-#define PCI_CHIP_I945_GM		0x27A2
-#define PCI_CHIP_I945_GME		0x27AE
-
-#define PCI_CHIP_Q35_G			0x29B2
-#define PCI_CHIP_G33_G			0x29C2
-#define PCI_CHIP_Q33_G			0x29D2
-
-#define PCI_CHIP_IGD_GM			0xA011
-#define PCI_CHIP_IGD_G			0xA001
-
-#define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
-#define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
-
-#define PCI_CHIP_I965_G			0x29A2
-#define PCI_CHIP_I965_Q			0x2992
-#define PCI_CHIP_I965_G_1		0x2982
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I965_GM		0x2A02
-#define PCI_CHIP_I965_GME		0x2A12
-
-#define PCI_CHIP_GM45_GM		0x2A42
-
-#define PCI_CHIP_IGD_E_G		0x2E02
-#define PCI_CHIP_Q45_G			0x2E12
-#define PCI_CHIP_G45_G			0x2E22
-#define PCI_CHIP_G41_G			0x2E32
-
-#define PCI_CHIP_ILD_G			0x0042
-#define PCI_CHIP_ILM_G			0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
-#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
-
-#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
-#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
-#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
-
-#define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2		0x0412
-#define PCI_CHIP_HASWELL_GT3		0x0422
-#define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2		0x0416
-#define PCI_CHIP_HASWELL_M_GT3		0x0426
-#define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
-#define PCI_CHIP_HASWELL_S_GT2		0x041A
-#define PCI_CHIP_HASWELL_S_GT3		0x042A
-#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
-#define PCI_CHIP_HASWELL_B_GT2		0x041B
-#define PCI_CHIP_HASWELL_B_GT3		0x042B
-#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
-#define PCI_CHIP_HASWELL_E_GT2		0x041E
-#define PCI_CHIP_HASWELL_E_GT3		0x042E
-#define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
-#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
-#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
-#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
-#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
-#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
-#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
-#define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
-#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
-#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
-#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
-#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
-#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
-#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
-#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
-#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
-#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
-#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
-#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
-#define BDW_SPARE			0x2
-#define BDW_ULT				0x6
-#define BDW_SERVER			0xa
-#define BDW_IRIS			0xb
-#define BDW_WORKSTATION			0xd
-#define BDW_ULX				0xe
-
-#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
-#define PCI_CHIP_VALLEYVIEW_1		0x0f31
-#define PCI_CHIP_VALLEYVIEW_2		0x0f32
-#define PCI_CHIP_VALLEYVIEW_3		0x0f33
-
-#define PCI_CHIP_CHERRYVIEW_0		0x22b0
-#define PCI_CHIP_CHERRYVIEW_1		0x22b1
-#define PCI_CHIP_CHERRYVIEW_2		0x22b2
-#define PCI_CHIP_CHERRYVIEW_3		0x22b3
-
-#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
-#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
-#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
-#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
-#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
-#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
-#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
-#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
-#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
-#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
-#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
-#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
-#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
-#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
-#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
-
-#endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index abe689c..d2e6934 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -36,7 +36,6 @@
 #include "libdrm.h"
 #include "xf86drm.h"
 #include "intel_device_priv.h"
-#include "intel_chipset.h"
 #include "intel_bufmgr.h"
 
 /* Struct for tracking drm_intel_decode state. */
-- 
1.8.3.1

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^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (11 preceding siblings ...)
  2015-03-05 16:20 ` [PATCH 12/12] intel: Remove intel_chipset.h Damien Lespiau
@ 2015-03-05 18:44 ` Ian Romanick
  2015-03-06 14:10 ` Emil Velikov
  13 siblings, 0 replies; 18+ messages in thread
From: Ian Romanick @ 2015-03-05 18:44 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx; +Cc: dri-devel

Based on light reading, patches 1, 5, 6, 7, 8, 10, and 11 are

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

I sent a comment on patch 9.  I'll try to look at the others in the next
few days... assuming nobody beats me to it.

I'm also going to send some similar Mesa patches that I'll CC you on.

On 03/05/2015 08:20 AM, Damien Lespiau wrote:
> A couple of things I wanted to do for the longest time:
>   
>   - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the
>     file when updating
>   - Start a new object, struct drm_intel_device where we could put common code
>     across several userspace projects. For instance it could be where we put
>     the "number of threads" logic we need to use in several 3d/gpgpu
>     states/instructions (that's a bit fiddly starting with CHV: we can't use
>     static tables anymore and need a runtime query to the kernel)
> 
> I tested it a bit so it can't be totally wrong:
> 
>   - I ran with this series on a couple of machines with no noticeable problem
>   - I check that the INTEL_DEVID_OVERRIDE env variable was still working (to
>     dump AUB files)
>   - make check, which exercises changes in the decoder path, still passes
> 

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^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
  2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
                   ` (12 preceding siblings ...)
  2015-03-05 18:44 ` [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Ian Romanick
@ 2015-03-06 14:10 ` Emil Velikov
  2015-03-06 14:35   ` Damien Lespiau
  13 siblings, 1 reply; 18+ messages in thread
From: Emil Velikov @ 2015-03-06 14:10 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx; +Cc: emil.l.velikov, dri-devel

On 05/03/15 16:20, Damien Lespiau wrote:
> A couple of things I wanted to do for the longest time:
>   
>   - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the
>     file when updating
>   - Start a new object, struct drm_intel_device where we could put common code
>     across several userspace projects. For instance it could be where we put
>     the "number of threads" logic we need to use in several 3d/gpgpu
>     states/instructions (that's a bit fiddly starting with CHV: we can't use
>     static tables anymore and need a runtime query to the kernel)
> 
Hi Damien,

So this paves the way to de-duplicate the device information stored in
beignet, libva-intel-driver, mesa, xf86-video-intel, other ?

That's great, thank you :-)
Emil
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^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
  2015-03-06 14:10 ` Emil Velikov
@ 2015-03-06 14:35   ` Damien Lespiau
  0 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-03-06 14:35 UTC (permalink / raw)
  To: Emil Velikov; +Cc: intel-gfx, dri-devel

On Fri, Mar 06, 2015 at 02:10:44PM +0000, Emil Velikov wrote:
> On 05/03/15 16:20, Damien Lespiau wrote:
> > A couple of things I wanted to do for the longest time:
> >   
> >   - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the
> >     file when updating
> >   - Start a new object, struct drm_intel_device where we could put common code
> >     across several userspace projects. For instance it could be where we put
> >     the "number of threads" logic we need to use in several 3d/gpgpu
> >     states/instructions (that's a bit fiddly starting with CHV: we can't use
> >     static tables anymore and need a runtime query to the kernel)
> > 
> Hi Damien,
> 
> So this paves the way to de-duplicate the device information stored in
> beignet, libva-intel-driver, mesa, xf86-video-intel, other ?

I don't expect xf86-video-intel to use this, but otherwise that's the
long term plan (will need a lot more work though).

-- 
Damien
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2015-03-06 14:35 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-03-05 16:20 [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Damien Lespiau
2015-03-05 16:20 ` [PATCH 01/12] intel: Remove unused define IS_MOBILE() Damien Lespiau
2015-03-05 16:20 ` [PATCH 02/12] intel: Introduce an drm_intel_device object Damien Lespiau
2015-03-05 16:20 ` [PATCH 03/12] intel: Use drm_intel_device in the gem buffer manager Damien Lespiau
2015-03-05 16:20 ` [PATCH 04/12] intel: Make drm_intel_decode use a drm_intel_device Damien Lespiau
2015-03-05 16:20 ` [PATCH 05/12] intel: Use '||' for the boolean or Damien Lespiau
2015-03-05 16:20 ` [PATCH 06/12] intel: Kill the IS_9XX() macro Damien Lespiau
2015-03-05 16:20 ` [PATCH 07/12] intel: Kill the IS_GEN4() macro Damien Lespiau
2015-03-05 16:20 ` [PATCH 08/12] intel: Remove direct usage of IS_915() Damien Lespiau
2015-03-05 16:20 ` [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument Damien Lespiau
2015-03-05 18:41   ` Ian Romanick
2015-03-05 18:45     ` Damien Lespiau
2015-03-05 16:20 ` [PATCH 10/12] intel: Make test_decode fail gracefully the decode context is NULL Damien Lespiau
2015-03-05 16:20 ` [PATCH 11/12] intel: Make test_decode not depend on intel_chipset.h Damien Lespiau
2015-03-05 16:20 ` [PATCH 12/12] intel: Remove intel_chipset.h Damien Lespiau
2015-03-05 18:44 ` [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h Ian Romanick
2015-03-06 14:10 ` Emil Velikov
2015-03-06 14:35   ` Damien Lespiau

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