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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code
Date: Fri, 06 Mar 2015 12:28:57 -0800	[thread overview]
Message-ID: <54FA0E09.3000106@virtuousgeek.org> (raw)
In-Reply-To: <20150306181402.GQ11371@intel.com>

On 03/06/2015 10:14 AM, Ville Syrjälä wrote:
> On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote:
>> On 03/05/2015 11:19 AM, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> I wonder if we should be warning if the wm values we end up with exceed
>> the mask size (the fact that you write them with a shift and mask made
>> me think of it), but that could be a follow on, or even put into the
>> calc code instead.  Anyway that's something we can do later after all
>> the atomic changes hit.
> 
> IIRC we always have enough bits up to any legal FIFO size, so the clamping
> done by vlv_compute_wm() should be enough. I should double check that though
> since that isn't the case on a bunch of the other platforms.
> 
> I think in general I'd really like magic register bitfield macros that
> scream whenever we overflow something by accident. But that's a much
> bigger topic. For one we'd have to parametrize all the macros rather than
> using raw shifts.

Yeah and that would have the added benefit of more readability.
Something for another day if/when we see underruns due to failed wm
programming in the future. :)

> 
>>
>> Does this fix any of our underrun bugs?  Should it have any references:
>> lines?
> 
> Those should probably be at the DDR DVFS disable patch since before that
> pretty much anything can happen. I was too lazy to trawl bugzilla though.
> Pretty much hoping QA can just go retest all display bugs once we get
> this landed.

Ok, sounds good.

Thanks,
Jesse

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  reply	other threads:[~2015-03-06 20:28 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-05 19:19 [PATCH v2 00/12] drm/i915: Redo VLV/CHV watermark code (v2) ville.syrjala
2015-03-05 19:19 ` [PATCH v2 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8 ville.syrjala
2015-03-09  3:39   ` Arun R Murthy
2015-03-05 19:19 ` [PATCH v2 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines ville.syrjala
2015-03-09  3:48   ` Arun R Murthy
2015-03-09 14:53     ` Ville Syrjälä
2015-03-05 19:19 ` [PATCH 03/12] drm/i915: Simplify VLV drain latency computation ville.syrjala
2015-03-05 19:19 ` [PATCH 04/12] drm/i915: Hide VLV DDL precision handling ville.syrjala
2015-03-09  4:02   ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 05/12] drm/i915: Reorganize VLV DDL setup ville.syrjala
2015-03-05 19:19 ` [PATCH v2 06/12] drm/i915: Pass plane to vlv_compute_drain_latency() ville.syrjala
2015-03-05 19:19 ` [PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV ville.syrjala
2015-03-05 19:19 ` [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled " ville.syrjala
2015-03-06 17:29   ` Daniel Vetter
2015-03-05 19:19 ` [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code ville.syrjala
2015-03-06 17:31   ` Jesse Barnes
2015-03-06 17:40     ` Daniel Vetter
2015-03-06 18:14     ` Ville Syrjälä
2015-03-06 20:28       ` Jesse Barnes [this message]
2015-03-10 10:26   ` Daniel Vetter
2015-03-10 11:27     ` Ville Syrjälä
2015-03-05 19:19 ` [PATCH v4 10/12] drm/i915: Program PFI credits for VLV ville.syrjala
2015-03-10 10:05   ` Purushothaman, Vijay A
2015-03-10 10:28     ` Daniel Vetter
2015-03-05 19:19 ` [PATCH v3 11/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV ville.syrjala
2015-03-09  4:23   ` Arun R Murthy
2015-03-05 19:19 ` [PATCH 12/12] drm/i915: Disable DDR DVFS " ville.syrjala
2015-03-06 17:31   ` Jesse Barnes
2015-03-09  4:44   ` Arun R Murthy
2015-03-09 15:00     ` Ville Syrjälä
2015-03-09 15:34       ` Daniel Vetter

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