From: "Purushothaman, Vijay A" <vijay.a.purushothaman@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV
Date: Mon, 09 Mar 2015 14:28:56 +0530 [thread overview]
Message-ID: <54FD60D0.7000103@linux.intel.com> (raw)
In-Reply-To: <1425319637-25733-1-git-send-email-ville.syrjala@linux.intel.com>
On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Supposedly CHV can sustain a pixel clock of up to 95% of
> cdclk, as opposed to the 90% limit that was used old older
> platforms. Update the cdclk selection code to allow for this.
>
> This will allow eg. HDMI 4k modes with their 297MHz pixel clock
> while still respecting the 320 MHz cdclk limit on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for forwarding the post si team confirmation. We were in the dark
about this as usual.
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Thanks,
Vijay
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3fe9598..94ff310 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> int max_pixclk)
> {
> int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
> + int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>
> /* FIXME: Punit isn't quite ready yet */
> if (IS_CHERRYVIEW(dev_priv->dev))
> @@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> * 200MHz
> * 267MHz
> * 320/333MHz (depends on HPLL freq)
> - * 400MHz
> - * So we check to see whether we're above 90% of the lower bin and
> - * adjust if needed.
> + * 400MHz (VLV only)
> + * So we check to see whether we're above 90% (VLV) or 95% (CHV)
> + * of the lower bin and adjust if needed.
> *
> * We seem to get an unstable or solid color picture at 200MHz.
> * Not sure what's wrong. For now use 200MHz only when all pipes
> * are off.
> */
> - if (max_pixclk > freq_320*9/10)
> + if (!IS_CHERRYVIEW(dev_priv) &&
> + max_pixclk > freq_320*limit/100)
> return 400000;
> - else if (max_pixclk > 266667*9/10)
> + else if (max_pixclk > 266667*limit/100)
> return freq_320;
> else if (max_pixclk > 0)
> return 266667;
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next prev parent reply other threads:[~2015-03-09 8:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-02 18:07 [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV ville.syrjala
2015-03-02 18:07 ` [PATCH 2/2] drm/i915: Fix chv cdclk support ville.syrjala
2015-03-03 20:55 ` shuang.he
2015-03-09 8:59 ` Purushothaman, Vijay A
2015-03-09 9:24 ` Mohan Marimuthu, Yogesh
2015-03-09 15:40 ` Daniel Vetter
2015-03-09 8:58 ` Purushothaman, Vijay A [this message]
2015-03-09 9:23 ` [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV Mohan Marimuthu, Yogesh
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