[PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

[PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Supposedly CHV can sustain a pixel clock of up to 95% of
cdclk, as opposed to the 90% limit that was used old older
platforms. Update the cdclk selection code to allow for this.

This will allow eg. HDMI 4k modes with their 297MHz pixel clock
while still respecting the 320 MHz cdclk limit on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..94ff310 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 				 int max_pixclk)
 {
 	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
+	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 
 	/* FIXME: Punit isn't quite ready yet */
 	if (IS_CHERRYVIEW(dev_priv->dev))
@@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 	 *   200MHz
 	 *   267MHz
 	 *   320/333MHz (depends on HPLL freq)
-	 *   400MHz
-	 * So we check to see whether we're above 90% of the lower bin and
-	 * adjust if needed.
+	 *   400MHz (VLV only)
+	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
+	 * of the lower bin and adjust if needed.
 	 *
 	 * We seem to get an unstable or solid color picture at 200MHz.
 	 * Not sure what's wrong. For now use 200MHz only when all pipes
 	 * are off.
 	 */
-	if (max_pixclk > freq_320*9/10)
+	if (!IS_CHERRYVIEW(dev_priv) &&
+	    max_pixclk > freq_320*limit/100)
 		return 400000;
-	else if (max_pixclk > 266667*9/10)
+	else if (max_pixclk > 266667*limit/100)
 		return freq_320;
 	else if (max_pixclk > 0)
 		return 266667;
-- 
2.0.5

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[PATCH 2/2] drm/i915: Fix chv cdclk support

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The specs seem to be full of misinformation wrt. the Punit register
0x36. Some versions still show the old VLV bit layout, some the new
layout, and all of them seem to tell us nonsense about the cdclk
value encoding.

Testing on actual hardware has shown that we simply need to program
the desired CCK divider into the Punit register using the new layout of
the bits. Doing that, the status bit change to indicate the same value,
and the CCK 0x6b register also changes accordingly to indicate that CCK
is now using the new divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 94ff310..ca49b6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
 	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
 
 	switch (cdclk) {
-	case 400000:
-		cmd = 3;
-		break;
 	case 333333:
 	case 320000:
-		cmd = 2;
-		break;
 	case 266667:
-		cmd = 1;
-		break;
 	case 200000:
-		cmd = 0;
 		break;
 	default:
 		MISSING_CASE(cdclk);
 		return;
 	}
 
+	/*
+	 * Specs are full of misinformation, but testing on actual
+	 * hardware has shown that we just need to write the desired
+	 * CCK divider into the Punit register.
+	 */
+	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 	val &= ~DSPFREQGUAR_MASK_CHV;
@@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
 	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 
-	/* FIXME: Punit isn't quite ready yet */
-	if (IS_CHERRYVIEW(dev_priv->dev))
-		return 400000;
-
 	/*
 	 * Really only a few cases to deal with, as only 4 CDclks are supported:
 	 *   200MHz
@@ -5606,10 +5601,6 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
 	u32 val;
 	int divider;
 
-	/* FIXME: Punit isn't quite ready yet */
-	if (IS_CHERRYVIEW(dev))
-		return 400000;
-
 	if (dev_priv->hpll_freq == 0)
 		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 
-- 
2.0.5

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Re: [PATCH 2/2] drm/i915: Fix chv cdclk support

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5872
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -7              278/278              271/278
ILK                                  308/308              308/308
SNB                 -1              284/284              283/284
IVB                                  380/380              380/380
BYT                                  294/294              294/294
HSW                                  387/387              387/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_fence_thrash_bo-write-verify-none      PASS(5)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-x      PASS(5)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      PASS(5)      FAIL(1)NO_RESULT(1)
 PNV  igt_gem_userptr_blits_coherency-sync      CRASH(5)NRUN(1)PASS(7)      CRASH(2)
 PNV  igt_gem_userptr_blits_coherency-unsync      NO_RESULT(1)CRASH(4)PASS(6)      CRASH(1)PASS(1)
*PNV  igt_gen3_render_linear_blits      FAIL(3)DMESG_WARN(1)PASS(7)      FAIL(1)NO_RESULT(1)
*PNV  igt_gen3_render_mixed_blits      FAIL(5)PASS(9)      FAIL(1)NO_RESULT(1)
*SNB  igt_gem_fence_thrash_bo-write-verify-y      PASS(5)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(16)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 2/2] drm/i915: Fix chv cdclk support

[Purushothaman, Vijay A]

On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The specs seem to be full of misinformation wrt. the Punit register
> 0x36. Some versions still show the old VLV bit layout, some the new
> layout, and all of them seem to tell us nonsense about the cdclk
> value encoding.
>
> Testing on actual hardware has shown that we simply need to program
> the desired CCK divider into the Punit register using the new layout of
> the bits. Doing that, the status bit change to indicate the same value,
> and the CCK 0x6b register also changes accordingly to indicate that CCK
> is now using the new divider.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Thanks,
Vijay


> ---
>   drivers/gpu/drm/i915/intel_display.c | 23 +++++++----------------
>   1 file changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 94ff310..ca49b6f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>   	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
>   
>   	switch (cdclk) {
> -	case 400000:
> -		cmd = 3;
> -		break;
>   	case 333333:
>   	case 320000:
> -		cmd = 2;
> -		break;
>   	case 266667:
> -		cmd = 1;
> -		break;
>   	case 200000:
> -		cmd = 0;
>   		break;
>   	default:
>   		MISSING_CASE(cdclk);
>   		return;
>   	}
>   
> +	/*
> +	 * Specs are full of misinformation, but testing on actual
> +	 * hardware has shown that we just need to write the desired
> +	 * CCK divider into the Punit register.
> +	 */
> +	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
> +
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
>   	val &= ~DSPFREQGUAR_MASK_CHV;
> @@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>   	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
>   	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>   
> -	/* FIXME: Punit isn't quite ready yet */
> -	if (IS_CHERRYVIEW(dev_priv->dev))
> -		return 400000;
> -
>   	/*
>   	 * Really only a few cases to deal with, as only 4 CDclks are supported:
>   	 *   200MHz
> @@ -5606,10 +5601,6 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
>   	u32 val;
>   	int divider;
>   
> -	/* FIXME: Punit isn't quite ready yet */
> -	if (IS_CHERRYVIEW(dev))
> -		return 400000;
> -
>   	if (dev_priv->hpll_freq == 0)
>   		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
>   

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Re: [PATCH 2/2] drm/i915: Fix chv cdclk support

[Mohan Marimuthu, Yogesh]

Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>

Thank you,
Yogesh

On 3/9/2015 2:29 PM, Purushothaman, Vijay A wrote:
> On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> The specs seem to be full of misinformation wrt. the Punit register
>> 0x36. Some versions still show the old VLV bit layout, some the new
>> layout, and all of them seem to tell us nonsense about the cdclk
>> value encoding.
>>
>> Testing on actual hardware has shown that we simply need to program
>> the desired CCK divider into the Punit register using the new layout of
>> the bits. Doing that, the status bit change to indicate the same value,
>> and the CCK 0x6b register also changes accordingly to indicate that CCK
>> is now using the new divider.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>
> Thanks,
> Vijay
>
>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 23 +++++++----------------
>>   1 file changed, 7 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 94ff310..ca49b6f 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct 
>> drm_device *dev, int cdclk)
>>       WARN_ON(dev_priv->display.get_display_clock_speed(dev) != 
>> dev_priv->vlv_cdclk_freq);
>>         switch (cdclk) {
>> -    case 400000:
>> -        cmd = 3;
>> -        break;
>>       case 333333:
>>       case 320000:
>> -        cmd = 2;
>> -        break;
>>       case 266667:
>> -        cmd = 1;
>> -        break;
>>       case 200000:
>> -        cmd = 0;
>>           break;
>>       default:
>>           MISSING_CASE(cdclk);
>>           return;
>>       }
>>   +    /*
>> +     * Specs are full of misinformation, but testing on actual
>> +     * hardware has shown that we just need to write the desired
>> +     * CCK divider into the Punit register.
>> +     */
>> +    cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
>> +
>>       mutex_lock(&dev_priv->rps.hw_lock);
>>       val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
>>       val &= ~DSPFREQGUAR_MASK_CHV;
>> @@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>       int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 
>> 333333 : 320000;
>>       int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>>   -    /* FIXME: Punit isn't quite ready yet */
>> -    if (IS_CHERRYVIEW(dev_priv->dev))
>> -        return 400000;
>> -
>>       /*
>>        * Really only a few cases to deal with, as only 4 CDclks are 
>> supported:
>>        *   200MHz
>> @@ -5606,10 +5601,6 @@ static int 
>> valleyview_get_display_clock_speed(struct drm_device *dev)
>>       u32 val;
>>       int divider;
>>   -    /* FIXME: Punit isn't quite ready yet */
>> -    if (IS_CHERRYVIEW(dev))
>> -        return 400000;
>> -
>>       if (dev_priv->hpll_freq == 0)
>>           dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
>
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Re: [PATCH 2/2] drm/i915: Fix chv cdclk support

[Daniel Vetter]

On Mon, Mar 09, 2015 at 02:54:56PM +0530, Mohan Marimuthu, Yogesh wrote:
> Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> 
> Thank you,
> Yogesh
> 
> On 3/9/2015 2:29 PM, Purushothaman, Vijay A wrote:
> >On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
> >>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >>The specs seem to be full of misinformation wrt. the Punit register
> >>0x36. Some versions still show the old VLV bit layout, some the new
> >>layout, and all of them seem to tell us nonsense about the cdclk
> >>value encoding.
> >>
> >>Testing on actual hardware has shown that we simply need to program
> >>the desired CCK divider into the Punit register using the new layout of
> >>the bits. Doing that, the status bit change to indicate the same value,
> >>and the CCK 0x6b register also changes accordingly to indicate that CCK
> >>is now using the new divider.
> >>
> >>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Both patches from this series merged, thanks.
-Daniel

> >
> >Thanks,
> >Vijay
> >
> >
> >>---
> >>  drivers/gpu/drm/i915/intel_display.c | 23 +++++++----------------
> >>  1 file changed, 7 insertions(+), 16 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>b/drivers/gpu/drm/i915/intel_display.c
> >>index 94ff310..ca49b6f 100644
> >>--- a/drivers/gpu/drm/i915/intel_display.c
> >>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>@@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct
> >>drm_device *dev, int cdclk)
> >>      WARN_ON(dev_priv->display.get_display_clock_speed(dev) !=
> >>dev_priv->vlv_cdclk_freq);
> >>        switch (cdclk) {
> >>-    case 400000:
> >>-        cmd = 3;
> >>-        break;
> >>      case 333333:
> >>      case 320000:
> >>-        cmd = 2;
> >>-        break;
> >>      case 266667:
> >>-        cmd = 1;
> >>-        break;
> >>      case 200000:
> >>-        cmd = 0;
> >>          break;
> >>      default:
> >>          MISSING_CASE(cdclk);
> >>          return;
> >>      }
> >>  +    /*
> >>+     * Specs are full of misinformation, but testing on actual
> >>+     * hardware has shown that we just need to write the desired
> >>+     * CCK divider into the Punit register.
> >>+     */
> >>+    cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
> >>+
> >>      mutex_lock(&dev_priv->rps.hw_lock);
> >>      val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> >>      val &= ~DSPFREQGUAR_MASK_CHV;
> >>@@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct
> >>drm_i915_private *dev_priv,
> >>      int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333
> >>: 320000;
> >>      int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
> >>  -    /* FIXME: Punit isn't quite ready yet */
> >>-    if (IS_CHERRYVIEW(dev_priv->dev))
> >>-        return 400000;
> >>-
> >>      /*
> >>       * Really only a few cases to deal with, as only 4 CDclks are
> >>supported:
> >>       *   200MHz
> >>@@ -5606,10 +5601,6 @@ static int
> >>valleyview_get_display_clock_speed(struct drm_device *dev)
> >>      u32 val;
> >>      int divider;
> >>  -    /* FIXME: Punit isn't quite ready yet */
> >>-    if (IS_CHERRYVIEW(dev))
> >>-        return 400000;
> >>-
> >>      if (dev_priv->hpll_freq == 0)
> >>          dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
> >
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> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

[Purushothaman, Vijay A]

On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Supposedly CHV can sustain a pixel clock of up to 95% of
> cdclk, as opposed to the 90% limit that was used old older
> platforms. Update the cdclk selection code to allow for this.
>
> This will allow eg. HDMI 4k modes with their 297MHz pixel clock
> while still respecting the 320 MHz cdclk limit on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for forwarding the post si team confirmation. We were in the dark 
about this as usual.

Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Thanks,
Vijay
> ---
>   drivers/gpu/drm/i915/intel_display.c | 12 +++++++-----
>   1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3fe9598..94ff310 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>   				 int max_pixclk)
>   {
>   	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
> +	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>   
>   	/* FIXME: Punit isn't quite ready yet */
>   	if (IS_CHERRYVIEW(dev_priv->dev))
> @@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>   	 *   200MHz
>   	 *   267MHz
>   	 *   320/333MHz (depends on HPLL freq)
> -	 *   400MHz
> -	 * So we check to see whether we're above 90% of the lower bin and
> -	 * adjust if needed.
> +	 *   400MHz (VLV only)
> +	 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
> +	 * of the lower bin and adjust if needed.
>   	 *
>   	 * We seem to get an unstable or solid color picture at 200MHz.
>   	 * Not sure what's wrong. For now use 200MHz only when all pipes
>   	 * are off.
>   	 */
> -	if (max_pixclk > freq_320*9/10)
> +	if (!IS_CHERRYVIEW(dev_priv) &&
> +	    max_pixclk > freq_320*limit/100)
>   		return 400000;
> -	else if (max_pixclk > 266667*9/10)
> +	else if (max_pixclk > 266667*limit/100)
>   		return freq_320;
>   	else if (max_pixclk > 0)
>   		return 266667;

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Re: [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

[Mohan Marimuthu, Yogesh]

Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>

Thank you,
Yogesh

On 3/9/2015 2:28 PM, Purushothaman, Vijay A wrote:
> On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Supposedly CHV can sustain a pixel clock of up to 95% of
>> cdclk, as opposed to the 90% limit that was used old older
>> platforms. Update the cdclk selection code to allow for this.
>>
>> This will allow eg. HDMI 4k modes with their 297MHz pixel clock
>> while still respecting the 320 MHz cdclk limit on CHV.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Thanks for forwarding the post si team confirmation. We were in the 
> dark about this as usual.
>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>
> Thanks,
> Vijay
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 12 +++++++-----
>>   1 file changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 3fe9598..94ff310 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>                    int max_pixclk)
>>   {
>>       int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 
>> 333333 : 320000;
>> +    int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>>         /* FIXME: Punit isn't quite ready yet */
>>       if (IS_CHERRYVIEW(dev_priv->dev))
>> @@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>        *   200MHz
>>        *   267MHz
>>        *   320/333MHz (depends on HPLL freq)
>> -     *   400MHz
>> -     * So we check to see whether we're above 90% of the lower bin and
>> -     * adjust if needed.
>> +     *   400MHz (VLV only)
>> +     * So we check to see whether we're above 90% (VLV) or 95% (CHV)
>> +     * of the lower bin and adjust if needed.
>>        *
>>        * We seem to get an unstable or solid color picture at 200MHz.
>>        * Not sure what's wrong. For now use 200MHz only when all pipes
>>        * are off.
>>        */
>> -    if (max_pixclk > freq_320*9/10)
>> +    if (!IS_CHERRYVIEW(dev_priv) &&
>> +        max_pixclk > freq_320*limit/100)
>>           return 400000;
>> -    else if (max_pixclk > 266667*9/10)
>> +    else if (max_pixclk > 266667*limit/100)
>>           return freq_320;
>>       else if (max_pixclk > 0)
>>           return 266667;
>
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