Re: [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV

["Mohan Marimuthu, Yogesh" <yogesh.mohan.marimuthu@intel.com>]

Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>

Thank you,
Yogesh

On 3/9/2015 2:28 PM, Purushothaman, Vijay A wrote:
> On 3/2/2015 11:37 PM, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Supposedly CHV can sustain a pixel clock of up to 95% of
>> cdclk, as opposed to the 90% limit that was used old older
>> platforms. Update the cdclk selection code to allow for this.
>>
>> This will allow eg. HDMI 4k modes with their 297MHz pixel clock
>> while still respecting the 320 MHz cdclk limit on CHV.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Thanks for forwarding the post si team confirmation. We were in the 
> dark about this as usual.
>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>
> Thanks,
> Vijay
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 12 +++++++-----
>>   1 file changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 3fe9598..94ff310 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4926,6 +4926,7 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>                    int max_pixclk)
>>   {
>>       int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 
>> 333333 : 320000;
>> +    int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>>         /* FIXME: Punit isn't quite ready yet */
>>       if (IS_CHERRYVIEW(dev_priv->dev))
>> @@ -4936,17 +4937,18 @@ static int valleyview_calc_cdclk(struct 
>> drm_i915_private *dev_priv,
>>        *   200MHz
>>        *   267MHz
>>        *   320/333MHz (depends on HPLL freq)
>> -     *   400MHz
>> -     * So we check to see whether we're above 90% of the lower bin and
>> -     * adjust if needed.
>> +     *   400MHz (VLV only)
>> +     * So we check to see whether we're above 90% (VLV) or 95% (CHV)
>> +     * of the lower bin and adjust if needed.
>>        *
>>        * We seem to get an unstable or solid color picture at 200MHz.
>>        * Not sure what's wrong. For now use 200MHz only when all pipes
>>        * are off.
>>        */
>> -    if (max_pixclk > freq_320*9/10)
>> +    if (!IS_CHERRYVIEW(dev_priv) &&
>> +        max_pixclk > freq_320*limit/100)
>>           return 400000;
>> -    else if (max_pixclk > 266667*9/10)
>> +    else if (max_pixclk > 266667*limit/100)
>>           return freq_320;
>>       else if (max_pixclk > 0)
>>           return 266667;
>
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