Re: [PATCH 5/7] drm/i915: Agressive downclocking on Baytrail

Deepak S
2015-03-18T08:17:21Z

On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
> Reuse the same reclocking strategy for Baytail as on its bigger brethren,
> Sandybridge and Ivybridge. In particular, this makes the device quicker
> to reclock (both up and down) though the tendency now is to downclock
> more aggressively to compensate for the RPS boosts.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Deepak S <deepak.s@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Conflicts:
> drivers/gpu/drm/i915/intel_pm.c
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++++-
> 4 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index efa98c9e5777..bfa6e11f802e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1028,6 +1028,9 @@ struct intel_gen6_power_mgmt {
> u8 rp0_freq; /* Non-overclocked max frequency. */
> u32 cz_freq;
>
> + u8 up_threshold; /* Current %busy required to uplock */
> + u8 down_threshold; /* Current %busy required to downclock */
> +
> int last_adj;
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8892dbdfb629..483079d96957 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1050,7 +1050,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
> if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
> if (!vlv_c0_above(dev_priv,
> &dev_priv->rps.down_ei, &now,
> - VLV_RP_DOWN_EI_THRESHOLD))
> + dev_priv->rps.down_threshold))
> events |= GEN6_PM_RP_DOWN_THRESHOLD;
> dev_priv->rps.down_ei = now;
> }
> @@ -1058,7 +1058,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
> if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
> if (vlv_c0_above(dev_priv,
> &dev_priv->rps.up_ei, &now,
> - VLV_RP_UP_EI_THRESHOLD))
> + dev_priv->rps.up_threshold))
> events |= GEN6_PM_RP_UP_THRESHOLD;
> dev_priv->rps.up_ei = now;
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ca24a2d4a823..13ec6c2b1fcf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -663,8 +663,6 @@ enum skl_disp_power_wells {
> #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
>
> #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
> -#define VLV_RP_UP_EI_THRESHOLD 90
> -#define VLV_RP_DOWN_EI_THRESHOLD 70
>
> /* vlv2 north clock has */
> #define CCK_FUSE_REG 0x8
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 55dc406cd195..972333d2211d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3722,10 +3722,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
> switch (new_power) {
> case LOW_POWER:
> /* Upclock if more than 95% busy over 16ms */
> + dev_priv->rps.up_threshold = 95;
> I915_WRITE(GEN6_RP_UP_EI, 12500);
> I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
>
> /* Downclock if less than 85% busy over 32ms */
> + dev_priv->rps.down_threshold = 85;
> I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
>
> @@ -3740,10 +3742,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>
> case BETWEEN:
> /* Upclock if more than 90% busy over 13ms */
> + dev_priv->rps.up_threshold = 90;
> I915_WRITE(GEN6_RP_UP_EI, 10250);
> I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
>
> /* Downclock if less than 75% busy over 32ms */
> + dev_priv->rps.down_threshold = 75;
> I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
>
> @@ -3758,10 +3762,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>
> case HIGH_POWER:
> /* Upclock if more than 85% busy over 10ms */
> + dev_priv->rps.up_threshold = 85;
> I915_WRITE(GEN6_RP_UP_EI, 8000);
> I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
>
> /* Downclock if less than 60% busy over 32ms */
> + dev_priv->rps.down_threshold = 60;
> I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
>
> @@ -3842,8 +3848,10 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
> "Odd GPU freq value\n"))
> val &= ~1;
>
> - if (val != dev_priv->rps.cur_freq)
> + if (val != dev_priv->rps.cur_freq) {
> vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> + gen6_set_rps_thresholds(dev_priv, val);

> If only for BYT, we might want to add a platform check before "gen6_set_rps_thresholds"
> + }
>
> I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
>
> @@ -3892,6 +3900,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> & GENFREQSTATUS) == 0, 100))
> DRM_ERROR("timed out waiting for Punit\n");
>
> + gen6_set_rps_thresholds(dev_priv, val);
> vlv_force_gfx_clock(dev_priv, false);
>
> I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));