Re: [PATCH 40/53] drm/i915: Update ring->add_request() to take a request structure

[Tomas Elf <tomas.elf@intel.com>]

On 19/02/2015 17:17, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Updated the various ring->add_request() implementations to take a request
> instead of a ring. This removes their reliance on the OLR to obtain the seqno
> value that the request should be tagged with.
>
> For: VIZ-5115
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem.c         |    2 +-
>   drivers/gpu/drm/i915/intel_ringbuffer.c |   26 ++++++++++++--------------
>   drivers/gpu/drm/i915/intel_ringbuffer.h |    2 +-
>   3 files changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e8577d7..4357cd3 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2453,7 +2453,7 @@ int __i915_add_request(struct drm_i915_gem_request *request,
>   	if (i915.enable_execlists)
>   		ret = ring->emit_request(ringbuf, request);
>   	else
> -		ret = ring->add_request(ring);
> +		ret = ring->add_request(request);
>   	if (ret)
>   		return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 470fa93..99f0dd1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1222,16 +1222,16 @@ static int gen6_signal(struct intel_engine_cs *signaller,
>
>   /**
>    * gen6_add_request - Update the semaphore mailbox registers
> - *
> - * @ring - ring that is adding a request
> - * @seqno - return seqno stuck into the ring
> + *
> + * @request - request to write to the ring
>    *
>    * Update the mailbox registers in the *other* rings with the current seqno.
>    * This acts like a signal in the canonical semaphore.
>    */
>   static int
> -gen6_add_request(struct intel_engine_cs *ring)
> +gen6_add_request(struct drm_i915_gem_request *req)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	int ret;
>
>   	if (ring->semaphore.signal)
> @@ -1244,8 +1244,7 @@ gen6_add_request(struct intel_engine_cs *ring)
>
>   	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
>   	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> -	intel_ring_emit(ring,
> -		    i915_gem_request_get_seqno(ring->outstanding_lazy_request));
> +	intel_ring_emit(ring, i915_gem_request_get_seqno(req));
>   	intel_ring_emit(ring, MI_USER_INTERRUPT);
>   	__intel_ring_advance(ring);
>
> @@ -1342,8 +1341,9 @@ do {									\
>   } while (0)
>
>   static int
> -pc_render_add_request(struct intel_engine_cs *ring)
> +pc_render_add_request(struct drm_i915_gem_request *req)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
>   	int ret;
>
> @@ -1363,8 +1363,7 @@ pc_render_add_request(struct intel_engine_cs *ring)
>   			PIPE_CONTROL_WRITE_FLUSH |
>   			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
>   	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> -	intel_ring_emit(ring,
> -		    i915_gem_request_get_seqno(ring->outstanding_lazy_request));
> +	intel_ring_emit(ring, i915_gem_request_get_seqno(req));
>   	intel_ring_emit(ring, 0);
>   	PIPE_CONTROL_FLUSH(ring, scratch_addr);
>   	scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
> @@ -1383,8 +1382,7 @@ pc_render_add_request(struct intel_engine_cs *ring)
>   			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>   			PIPE_CONTROL_NOTIFY);
>   	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> -	intel_ring_emit(ring,
> -		    i915_gem_request_get_seqno(ring->outstanding_lazy_request));
> +	intel_ring_emit(ring, i915_gem_request_get_seqno(req));
>   	intel_ring_emit(ring, 0);
>   	__intel_ring_advance(ring);
>
> @@ -1553,8 +1551,9 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
>   }
>
>   static int
> -i9xx_add_request(struct intel_engine_cs *ring)
> +i9xx_add_request(struct drm_i915_gem_request *req)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	int ret;
>
>   	ret = intel_ring_begin(ring, 4);
> @@ -1563,8 +1562,7 @@ i9xx_add_request(struct intel_engine_cs *ring)
>
>   	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
>   	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> -	intel_ring_emit(ring,
> -		    i915_gem_request_get_seqno(ring->outstanding_lazy_request));
> +	intel_ring_emit(ring, i915_gem_request_get_seqno(req));
>   	intel_ring_emit(ring, MI_USER_INTERRUPT);
>   	__intel_ring_advance(ring);
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 6f7c79c..d2391a9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -150,7 +150,7 @@ struct  intel_engine_cs {
>   	int __must_check (*flush)(struct drm_i915_gem_request *req,
>   				  u32	invalidate_domains,
>   				  u32	flush_domains);
> -	int		(*add_request)(struct intel_engine_cs *ring);
> +	int		(*add_request)(struct drm_i915_gem_request *req);
>   	/* Some chipsets are not quite as coherent as advertised and need
>   	 * an expensive kick to force a true read of the up-to-date seqno.
>   	 * However, the up-to-date seqno is not always required and the last
>

Reviewed-by: Tomas Elf <tomas.elf@intel.com>

Thanks,
Tomas
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