Re: [PATCH 01/11] drm/i915/skl: Added new macros

Ville Syrjälä
2015-03-11T19:12:49Z

On Fri, Mar 06, 2015 at 11:07:14AM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
>
> For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
> have changed slightly. Also on SKL, frequency is specified in
> units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
> platforms and the time values are expressed in units of 1.33 us,
> compared to 1.28 us for earlier platforms.
> Added new macros for the aforementioned changes.
>
> v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)
>
> v3: Removed the implicit use of dev_priv in GT_INTERVAL_FROM_US macro (Chris)
>
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b384b72..f676dc8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2414,6 +2414,7 @@ struct drm_i915_cmd_table {
> #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>
> #define GT_FREQUENCY_MULTIPLIER 50
> +#define GEN9_FREQ_SCALER 3
>
> #include "i915_trace.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 56b97c4..05ab344 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2427,6 +2427,12 @@ enum skl_disp_power_wells {
> #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
> #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
>
> +#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
> +#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> + INTERVAL_1_33_US(us) : \
> + INTERVAL_1_28_US(us))
> +
> /*
> * Logical Context regs
> */
> @@ -6080,6 +6086,7 @@ enum skl_disp_power_wells {
> #define GEN6_TURBO_DISABLE (1<<31)
> #define GEN6_FREQUENCY(x) ((x)<<25)
> #define HSW_FREQUENCY(x) ((x)<<24)
> +#define GEN9_FREQUENCY(x) ((x)<<23)
> #define GEN6_OFFSET(x) ((x)<<19)
> #define GEN6_AGGRESSIVE_TURBO (0<<15)
> #define GEN6_RC_VIDEO_FREQ 0xA00C
> @@ -6098,8 +6105,10 @@ enum skl_disp_power_wells {
> #define GEN6_RPSTAT1 0xA01C
> #define GEN6_CAGF_SHIFT 8
> #define HSW_CAGF_SHIFT 7
> +#define GEN9_CAGF_SHIFT 23
> #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
> #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
> +#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
> #define GEN6_RP_CONTROL 0xA024
> #define GEN6_RP_MEDIA_TURBO (1<<11)
> #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
> --
> 1.9.2
>
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--
Ville Syrjälä
Intel OTC