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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Daniel Vetter <daniel@ffwll.ch>,
	"Song, Ruiling" <ruiling.song@intel.com>
Cc: "Vetter, Daniel" <daniel.vetter@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Yang, Rong R" <rong.r.yang@intel.com>,
	"beignet@lists.freedesktop.org" <beignet@lists.freedesktop.org>,
	"Weinehall, David" <david.weinehall@intel.com>
Subject: Re: [Beignet] Preventing zero GPU virtual address allocation
Date: Mon, 16 Mar 2015 13:11:00 -0700	[thread overview]
Message-ID: <550738D4.6070907@virtuousgeek.org> (raw)
In-Reply-To: <20150316085214.GF21993@phenom.ffwll.local>

On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:29:24AM +0000, Song, Ruiling wrote:
>>
>>
>>> -----Original Message-----
>>> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel
>>> Vetter
>>> Sent: Saturday, March 14, 2015 1:14 AM
>>> To: Chris Wilson; Daniel Vetter; Weinehall, David; Zou, Nanhai; Song, Ruiling;
>>> Vetter, Daniel; intel-gfx@lists.freedesktop.org; Yang, Rong R;
>>> beignet@lists.freedesktop.org
>>> Subject: Re: [Beignet] [Intel-gfx] Preventing zero GPU virtual address
>>> allocation
>>>
>>> On Fri, Mar 13, 2015 at 04:58:47PM +0000, Chris Wilson wrote:
>>>> On Fri, Mar 13, 2015 at 10:27:38AM +0100, Daniel Vetter wrote:
>>>>> If supporting systems without full ppgtt is a requirement for you
>>>>> (still wonky on gen8 a bit, so might be a good strategy) then imo
>>>>> it's the PIN_BIAS idea I've laid out earlier in this thread. That
>>>>> one will work everywhere. softpin can unexpectedly fail without full
>>>>> ppgtt if the kernel decides to put something at a given spot, which
>>>>> imo means we should only expose it on full ppgtt systems.
>>>>>
>>>>> And PIN_BIAS should be fairly easy to wire up since the internal
>>>>> logic is all there already. So "just" needs an execbuf flag, igt
>>>>> test and appropriate userspace to set that new bit.
>>>>
>>>> It doesn't though. To provide the guarantee userspace is asking for
>>>> (which is that address 0 goes to a special, preferrably inaccessible,
>>>> page), you have to evict the first N pages in the GGTT. That is just
>>>> as likely to fail with an execbuffer flag as it would with an execobject flag.
>>>
>>> Afaiui userspace only needs the guarantee that NULL is never a valid address.
>>> Which means it's never a valid address for its own buffer objects. I don't
>>> think it cares one bit what's actually there, it's not mandatory to fault
>>> apparently. And faulting is what's not possible.
>> Yes, This is what exactly what we need, that is make NULL as an invalid address. It's just like C language.
>> But I have some more comment. The buffer object used in opencl may be allocated in libva/opengl and shared for opencl usage through some opencl extension.
>> Afaiui, this would implicitly require libva/mesa also avoid zero-address buffer object allocation.
>> Will libdrm re-bind such kind of shared buffer object to a new graphics virtual address?
>> So that PIN_BIAS is also effective on the shared buffer, right?
> 
> Yeah we'll rebind if needed. We can make this an execbuf or context flag,
> in either case anything that gets executed by ocl will be moved around if
> it accidentally ended up at the wrong place. The only exception is if a
> buffer is pinned already, i.e. if you're doing direct rendering to the
> frontbuffer. That will give you an EBUSY, but otoh that also shouldn't
> ever happen really.

Oh and we may need to re-introduce the ppgtt zero page reservation
anyway due to bugs, but that's another topic...

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      parent reply	other threads:[~2015-03-16 20:11 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-05  2:56 Preventing zero GPU virtual address allocation Song, Ruiling
2015-03-05 12:52 ` [Intel-gfx] " Daniel Vetter
2015-03-05 13:01   ` Chris Wilson
2015-03-05 15:27     ` [Intel-gfx] " Daniel Vetter
2015-03-05 21:07       ` Chris Wilson
2015-03-09 15:46         ` Jesse Barnes
2015-03-09 15:49           ` Jesse Barnes
2015-03-06  2:11       ` [Intel-gfx] " Zou, Nanhai
2015-03-06  8:39         ` [Beignet] " Chris Wilson
2015-03-09  2:34           ` Zou, Nanhai
2015-03-09 12:02             ` [Intel-gfx] " Chris Wilson
2015-03-10  1:57               ` Zou, Nanhai
2015-03-13  9:10               ` [Beignet] " David Weinehall
2015-03-13  9:18                 ` [Intel-gfx] " Chris Wilson
2015-03-13  9:27                 ` Daniel Vetter
2015-03-13 16:58                   ` [Beignet] " Chris Wilson
2015-03-13 17:13                     ` [Intel-gfx] " Daniel Vetter
2015-03-13 17:34                       ` [Beignet] " Chris Wilson
2015-03-13 17:49                         ` [Intel-gfx] " Daniel Vetter
2015-03-16  2:29                       ` [Beignet] " Song, Ruiling
2015-03-16  8:52                         ` Daniel Vetter
2015-03-16 20:10                           ` Jesse Barnes
2015-03-17  1:19                             ` [Intel-gfx] " Zhigang Gong
2015-03-17  2:29                             ` Zou, Nanhai
2015-03-17 15:13                               ` [Beignet] " Jesse Barnes
2015-03-19  3:22                                 ` [Intel-gfx] " Song, Ruiling
2015-03-19 10:09                                   ` [Beignet] " David Weinehall
2015-03-19 14:58                                     ` Daniel Vetter
2015-03-20  3:01                                       ` Song, Ruiling
2015-03-17 10:01                             ` Daniel Vetter
2015-03-16 20:11                           ` Jesse Barnes [this message]

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