* [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8
@ 2015-03-25 13:42 Mika Kuoppala
2015-03-25 13:42 ` [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG Mika Kuoppala
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Mika Kuoppala @ 2015-03-25 13:42 UTC (permalink / raw)
To: intel-gfx
Add ERROR decodings for gen8
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
tools/intel_error_decode.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 035b17f..fb4a2a4 100644
--- a/tools/intel_error_decode.c
+++ b/tools/intel_error_decode.c
@@ -288,10 +288,29 @@ static void print_snb_error(unsigned int reg)
printf(" Cacheline containing a PD was marked as invalid\n");
}
+static void print_bdw_error(unsigned int reg, unsigned int devid)
+{
+ print_ivb_error(reg, devid);
+
+ if (reg & (1 << 10))
+ printf(" Non WB memory type for Advanced Context\n");
+ if (reg & (1 << 11))
+ printf(" PASID not enabled\n");
+ if (reg & (1 << 12))
+ printf(" PASID boundary violation\n");
+ if (reg & (1 << 13))
+ printf(" PASID not valid\n");
+ if (reg & (1 << 14))
+ printf(" PASID was zero for untranslated request\n");
+ if (reg & (1 << 15))
+ printf(" Context was not marked as present when doing DMA\n");
+}
+
static void
print_error(unsigned int reg, unsigned int devid)
{
switch (intel_gen(devid)) {
+ case 8: return print_bdw_error(reg, devid);
case 7: return print_ivb_error(reg, devid);
case 6: return print_snb_error(reg);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG 2015-03-25 13:42 [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Mika Kuoppala @ 2015-03-25 13:42 ` Mika Kuoppala 2015-03-25 16:13 ` Mika Kuoppala 2015-03-25 13:42 ` [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings Mika Kuoppala 2015-03-25 16:46 ` [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Michel Thierry 2 siblings, 1 reply; 7+ messages in thread From: Mika Kuoppala @ 2015-03-25 13:42 UTC (permalink / raw) To: intel-gfx Add decodings for FAULT_REG Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- tools/intel_error_decode.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index fb4a2a4..553307f 100644 --- a/tools/intel_error_decode.c +++ b/tools/intel_error_decode.c @@ -380,6 +380,27 @@ print_fence(unsigned int devid, uint64_t fence) } } +static void +print_fault_reg(unsigned devid, uint32_t reg) +{ + const char *type[] = { "Page", "Invalid PD", + "Unloaded PD", "Invalid and Unloaded PD" }; + const char *engine[] = { "GFX", "MFX0", "MFX1", "VEBX", "BLT" }; + + if (reg & (1 << 0)) + printf(" Valid\n"); + else + return; + + printf(" %s (%s)\n", type[reg >> 1 & 0x3], + reg & (1 << 11) ? "GGTT" : "PPGTT"); + printf(" Engine %s (Source ID %d)\n", engine[reg >> 12 & 0x3], + reg >> 3 & 0xff); + + if (intel_gen(devid) < 8) + printf(" Address 0x%08x\n", reg & ~((1 << 12)-1)); +} + #define MAX_RINGS 10 /* I really hope this never... */ uint32_t head[MAX_RINGS]; int head_ndx = 0; @@ -520,6 +541,10 @@ read_data_file(FILE *file) if (matched == 2) print_fence(devid, fence); + matched = sscanf(line, " FAULT_REG: 0x%08x\n", ®); + if (matched == 1 && reg) + print_fault_reg(devid, reg); + continue; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG 2015-03-25 13:42 ` [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG Mika Kuoppala @ 2015-03-25 16:13 ` Mika Kuoppala 2015-03-25 16:46 ` Michel Thierry 0 siblings, 1 reply; 7+ messages in thread From: Mika Kuoppala @ 2015-03-25 16:13 UTC (permalink / raw) To: intel-gfx Add decodings for FAULT_REG v2: fix fault encodings and ignore addr type for gen8+ (Michel) fix engine mask Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- tools/intel_error_decode.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index fb4a2a4..5fccefa 100644 --- a/tools/intel_error_decode.c +++ b/tools/intel_error_decode.c @@ -380,6 +380,44 @@ print_fence(unsigned int devid, uint64_t fence) } } +static void +print_fault_reg(unsigned devid, uint32_t reg) +{ + const char *gen7_types[] = { "Page", + "Invalid PD", + "Unloaded PD", + "Invalid and Unloaded PD" }; + + const char *gen8_types[] = { "PTE", + "PDE", + "PDPE", + "PML4E" }; + + const char *engine[] = { "GFX", "MFX0", "MFX1", "VEBX", + "BLT", "Unknown", "Unknown", "Unknown" }; + + if (intel_gen(devid) < 7) + return; + + if (reg & (1 << 0)) + printf(" Valid\n"); + else + return; + + if (intel_gen(devid) < 8) + printf(" %s Fault (%s)\n", gen7_types[reg >> 1 & 0x3], + reg & (1 << 11) ? "GGTT" : "PPGTT"); + else + printf(" Invalid %s Fault\n", gen8_types[reg >> 1 & 0x3]); + + if (intel_gen(devid) < 8) + printf(" Address 0x%08x\n", reg & ~((1 << 12)-1)); + else + printf(" Engine %s\n", engine[reg >> 12 & 0x7]); + + printf(" Source ID %d\n", reg >> 3 & 0xff); +} + #define MAX_RINGS 10 /* I really hope this never... */ uint32_t head[MAX_RINGS]; int head_ndx = 0; @@ -520,6 +558,10 @@ read_data_file(FILE *file) if (matched == 2) print_fence(devid, fence); + matched = sscanf(line, " FAULT_REG: 0x%08x\n", ®); + if (matched == 1 && reg) + print_fault_reg(devid, reg); + continue; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG 2015-03-25 16:13 ` Mika Kuoppala @ 2015-03-25 16:46 ` Michel Thierry 0 siblings, 0 replies; 7+ messages in thread From: Michel Thierry @ 2015-03-25 16:46 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx@lists.freedesktop.org On 3/25/2015 4:13 PM, Mika Kuoppala wrote: > Add decodings for FAULT_REG > > v2: fix fault encodings and ignore addr type for gen8+ (Michel) > fix engine mask > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > tools/intel_error_decode.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c > index fb4a2a4..5fccefa 100644 > --- a/tools/intel_error_decode.c > +++ b/tools/intel_error_decode.c > @@ -380,6 +380,44 @@ print_fence(unsigned int devid, uint64_t fence) > } > } > > +static void > +print_fault_reg(unsigned devid, uint32_t reg) > +{ > + const char *gen7_types[] = { "Page", > + "Invalid PD", > + "Unloaded PD", > + "Invalid and Unloaded PD" }; > + > + const char *gen8_types[] = { "PTE", > + "PDE", > + "PDPE", > + "PML4E" }; > + > + const char *engine[] = { "GFX", "MFX0", "MFX1", "VEBX", > + "BLT", "Unknown", "Unknown", "Unknown" }; > + > + if (intel_gen(devid) < 7) > + return; > + > + if (reg & (1 << 0)) > + printf(" Valid\n"); > + else > + return; > + > + if (intel_gen(devid) < 8) > + printf(" %s Fault (%s)\n", gen7_types[reg >> 1 & 0x3], > + reg & (1 << 11) ? "GGTT" : "PPGTT"); > + else > + printf(" Invalid %s Fault\n", gen8_types[reg >> 1 & 0x3]); > + > + if (intel_gen(devid) < 8) > + printf(" Address 0x%08x\n", reg & ~((1 << 12)-1)); > + else > + printf(" Engine %s\n", engine[reg >> 12 & 0x7]); > + > + printf(" Source ID %d\n", reg >> 3 & 0xff); > +} > + > #define MAX_RINGS 10 /* I really hope this never... */ > uint32_t head[MAX_RINGS]; > int head_ndx = 0; > @@ -520,6 +558,10 @@ read_data_file(FILE *file) > if (matched == 2) > print_fence(devid, fence); > > + matched = sscanf(line, " FAULT_REG: 0x%08x\n", ®); > + if (matched == 1 && reg) > + print_fault_reg(devid, reg); > + > continue; > } > > -- > 1.9.1 > v2 looks good. Reviewed-by: Michel Thierry <michel.thierry@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings 2015-03-25 13:42 [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Mika Kuoppala 2015-03-25 13:42 ` [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG Mika Kuoppala @ 2015-03-25 13:42 ` Mika Kuoppala 2015-03-25 16:47 ` Michel Thierry 2015-03-25 16:46 ` [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Michel Thierry 2 siblings, 1 reply; 7+ messages in thread From: Mika Kuoppala @ 2015-03-25 13:42 UTC (permalink / raw) To: intel-gfx These two registers contains the 48bit fault address. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- tools/intel_error_decode.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index 553307f..7c32fc3 100644 --- a/tools/intel_error_decode.c +++ b/tools/intel_error_decode.c @@ -401,6 +401,19 @@ print_fault_reg(unsigned devid, uint32_t reg) printf(" Address 0x%08x\n", reg & ~((1 << 12)-1)); } +static void +print_fault_data(unsigned devid, uint32_t data1, uint32_t data0) +{ + uint64_t address; + + if (intel_gen(devid) < 8) + return; + + address = ((uint64_t)(data0) << 12) | ((uint64_t)data1 & 0xf) << 44; + printf(" Address 0x%016" PRIx64 " %s\n", address, + data1 & (1 << 4) ? "GGTT" : "PPGTT"); +} + #define MAX_RINGS 10 /* I really hope this never... */ uint32_t head[MAX_RINGS]; int head_ndx = 0; @@ -482,7 +495,7 @@ read_data_file(FILE *file) matched = sscanf(line, "%08x : %08x", &offset, &value); if (matched != 2) { - unsigned int reg; + unsigned int reg, reg2; /* display reg section is after the ringbuffers, don't mix them */ decode(decode_ctx, is_batch, ring_name, gtt_offset, @@ -545,6 +558,10 @@ read_data_file(FILE *file) if (matched == 1 && reg) print_fault_reg(devid, reg); + matched = sscanf(line, " FAULT_TLB_DATA: 0x%08x 0x%08x\n", ®, ®2); + if (matched == 2) + print_fault_data(devid, reg, reg2); + continue; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings 2015-03-25 13:42 ` [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings Mika Kuoppala @ 2015-03-25 16:47 ` Michel Thierry 0 siblings, 0 replies; 7+ messages in thread From: Michel Thierry @ 2015-03-25 16:47 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx@lists.freedesktop.org On 3/25/2015 1:42 PM, Mika Kuoppala wrote: > These two registers contains the 48bit fault address. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > tools/intel_error_decode.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c > index 553307f..7c32fc3 100644 > --- a/tools/intel_error_decode.c > +++ b/tools/intel_error_decode.c > @@ -401,6 +401,19 @@ print_fault_reg(unsigned devid, uint32_t reg) > printf(" Address 0x%08x\n", reg & ~((1 << 12)-1)); > } The code above is different in v2 of the previous patch, so it won't apply cleanly... > > +static void > +print_fault_data(unsigned devid, uint32_t data1, uint32_t data0) > +{ > + uint64_t address; > + > + if (intel_gen(devid) < 8) > + return; > + > + address = ((uint64_t)(data0) << 12) | ((uint64_t)data1 & 0xf) << 44; > + printf(" Address 0x%016" PRIx64 " %s\n", address, > + data1 & (1 << 4) ? "GGTT" : "PPGTT"); > +} > + > #define MAX_RINGS 10 /* I really hope this never... */ > uint32_t head[MAX_RINGS]; > int head_ndx = 0; > @@ -482,7 +495,7 @@ read_data_file(FILE *file) > > matched = sscanf(line, "%08x : %08x", &offset, &value); > if (matched != 2) { > - unsigned int reg; > + unsigned int reg, reg2; > > /* display reg section is after the ringbuffers, don't mix them */ > decode(decode_ctx, is_batch, ring_name, gtt_offset, > @@ -545,6 +558,10 @@ read_data_file(FILE *file) > if (matched == 1 && reg) > print_fault_reg(devid, reg); > > + matched = sscanf(line, " FAULT_TLB_DATA: 0x%08x 0x%08x\n", ®, ®2); > + if (matched == 2) > + print_fault_data(devid, reg, reg2); > + > continue; > } > > -- > 1.9.1 > Anyway, Reviewed-by: Michel Thierry <michel.thierry@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 2015-03-25 13:42 [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Mika Kuoppala 2015-03-25 13:42 ` [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG Mika Kuoppala 2015-03-25 13:42 ` [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings Mika Kuoppala @ 2015-03-25 16:46 ` Michel Thierry 2 siblings, 0 replies; 7+ messages in thread From: Michel Thierry @ 2015-03-25 16:46 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx@lists.freedesktop.org On 3/25/2015 1:42 PM, Mika Kuoppala wrote: > Add ERROR decodings for gen8 > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > tools/intel_error_decode.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c > index 035b17f..fb4a2a4 100644 > --- a/tools/intel_error_decode.c > +++ b/tools/intel_error_decode.c > @@ -288,10 +288,29 @@ static void print_snb_error(unsigned int reg) > printf(" Cacheline containing a PD was marked as invalid\n"); > } > > +static void print_bdw_error(unsigned int reg, unsigned int devid) > +{ > + print_ivb_error(reg, devid); > + > + if (reg & (1 << 10)) > + printf(" Non WB memory type for Advanced Context\n"); > + if (reg & (1 << 11)) > + printf(" PASID not enabled\n"); > + if (reg & (1 << 12)) > + printf(" PASID boundary violation\n"); > + if (reg & (1 << 13)) > + printf(" PASID not valid\n"); > + if (reg & (1 << 14)) > + printf(" PASID was zero for untranslated request\n"); > + if (reg & (1 << 15)) > + printf(" Context was not marked as present when doing DMA\n"); > +} > + > static void > print_error(unsigned int reg, unsigned int devid) > { > switch (intel_gen(devid)) { > + case 8: return print_bdw_error(reg, devid); > case 7: return print_ivb_error(reg, devid); > case 6: return print_snb_error(reg); > } > -- > 1.9.1 > Looks good (I don't expect to see these PASID errors soon). Reviewed-by: Michel Thierry <michel.thierry@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-03-25 16:47 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-03-25 13:42 [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Mika Kuoppala 2015-03-25 13:42 ` [PATCH 2/3] tools/intel_error_decode: Add decodings for FAULT_REG Mika Kuoppala 2015-03-25 16:13 ` Mika Kuoppala 2015-03-25 16:46 ` Michel Thierry 2015-03-25 13:42 ` [PATCH 3/3] tools/intel_error_decode: Add gen8+ fault data encodings Mika Kuoppala 2015-03-25 16:47 ` Michel Thierry 2015-03-25 16:46 ` [PATCH 1/3] tools/intel_error_decode: Add ERROR decodings for gen8 Michel Thierry
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