[PATCH v3] drm/i915: DP link training optimization

[PATCH v3] drm/i915: DP link training optimization

[Mika Kahola]

This is patch series optimizes DP link training by reusing
the link parameter settings if DP link has bee previously
trained. In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.

The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.

The second patch is a generalization to cover all cases.

Mika Kahola (1):
  drm/i915: DP link training optimization

 drivers/gpu/drm/i915/intel_dp.c  | 29 ++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 27 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH v3 1/2] drm/i915: DP link training optimization

[Mika Kahola]

This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.

In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.

V2:
- flag that indicates if DP link is trained and valid
  renamed from 'link_trained' to 'train_set_valid'
- removed routine 'intel_dp_reuse_link_train'

V3:
- rebased against the latest drm-intel-nightly

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 29 ++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 937ba31..15adafc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,7 +3547,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
 			uint8_t dp_train_pat)
 {
-	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+	if (!intel_dp->train_set_valid)
+		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp, DP);
 	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
 }
@@ -3660,6 +3661,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
+		/*
+		 * if we used previously trained voltage and pre-emphasis values
+		 * and we don't get clock recovery, reset link training values
+		 */
+		if (intel_dp->train_set_valid) {
+			DRM_DEBUG_KMS("clock recovery not ok, reset");
+			/* clear the flag as we are not reusing train set */
+			intel_dp->train_set_valid = false;
+			if (!intel_dp_reset_link_train(intel_dp, &DP,
+						       DP_TRAINING_PATTERN_1 |
+						       DP_LINK_SCRAMBLING_DISABLE)) {
+				DRM_ERROR("failed to enable link training\n");
+				return;
+			}
+			continue;
+		}
+
 		/* Check to see if we've tried the max voltage */
 		for (i = 0; i < intel_dp->lane_count; i++)
 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -3737,6 +3755,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+			intel_dp->train_set_valid = false;
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
 						training_pattern |
@@ -3752,6 +3771,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
 		/* Try 5 times, then try clock recovery if that fails */
 		if (tries > 5) {
+			intel_dp->train_set_valid = false;
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
 						training_pattern |
@@ -3773,9 +3793,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
 	intel_dp->DP = DP;
 
-	if (channel_eq)
+	if (channel_eq) {
+		intel_dp->train_set_valid = is_edp(intel_dp);
 		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
-
+	}
 }
 
 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
@@ -4822,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	intel_display_power_get(dev_priv, power_domain);
 
 	if (long_hpd) {
+		/* indicate that we need to restart link training */
+		intel_dp->train_set_valid = false;
 
 		if (HAS_PCH_SPLIT(dev)) {
 			if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 23a42a4..62bd08b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -739,6 +739,7 @@ struct intel_dp {
 				     bool has_aux_irq,
 				     int send_bytes,
 				     uint32_t aux_clock_divider);
+	bool train_set_valid;
 
 	/* Displayport compliance testing */
 	unsigned long compliance_test_type;
-- 
1.9.1

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[PATCH v3 2/2] drm/i915: DP link training optimization

[Mika Kahola]

This patch adds DP link training optimization by reusing the
previously trained values.

v2:
- rebase

V3:
- rebase

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 15adafc..bb1a8d0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	intel_dp->DP = DP;
 
 	if (channel_eq) {
-		intel_dp->train_set_valid = is_edp(intel_dp);
+		intel_dp->train_set_valid = true;
 		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
 	}
 }
-- 
1.9.1

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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Sivakumar Thulasimani]

On 4/28/2015 12:13 PM, Mika Kahola wrote:
> This patch adds DP link training optimization by reusing the
> previously trained values.
>
> v2:
> - rebase
>
> V3:
> - rebase
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 15adafc..bb1a8d0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   	intel_dp->DP = DP;
>   
>   	if (channel_eq) {
> -		intel_dp->train_set_valid = is_edp(intel_dp);
> +		intel_dp->train_set_valid = true;
>   		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
>   	}
>   }
any reason why this is split into a separate patch ?
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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Mika Kahola]

On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
> 
> On 4/28/2015 12:13 PM, Mika Kahola wrote:
> > This patch adds DP link training optimization by reusing the
> > previously trained values.
> >
> > v2:
> > - rebase
> >
> > V3:
> > - rebase
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_dp.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 15adafc..bb1a8d0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >   	intel_dp->DP = DP;
> >   
> >   	if (channel_eq) {
> > -		intel_dp->train_set_valid = is_edp(intel_dp);
> > +		intel_dp->train_set_valid = true;
> >   		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> >   	}
> >   }
> any reason why this is split into a separate patch ?
I discussed this with Jani and we agreed that one option would be to
apply this optimization only for the eDP case. This second patch is for
the possibility to cover the general DP.

-Mika-


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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Sivakumar Thulasimani]

On 4/28/2015 1:44 PM, Mika Kahola wrote:
> On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
>> On 4/28/2015 12:13 PM, Mika Kahola wrote:
>>> This patch adds DP link training optimization by reusing the
>>> previously trained values.
>>>
>>> v2:
>>> - rebase
>>>
>>> V3:
>>> - rebase
>>>
>>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_dp.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index 15adafc..bb1a8d0 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>>>    	intel_dp->DP = DP;
>>>    
>>>    	if (channel_eq) {
>>> -		intel_dp->train_set_valid = is_edp(intel_dp);
>>> +		intel_dp->train_set_valid = true;
>>>    		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
>>>    	}
>>>    }
>> any reason why this is split into a separate patch ?
> I discussed this with Jani and we agreed that one option would be to
> apply this optimization only for the eDP case. This second patch is for
> the possibility to cover the general DP.
>
> -Mika-
>
>
might be a nit pick so up to you to consider this or not :). since DP is 
part of the second patch, better to reset "train_set_valid" for long 
pulse HPD in the second patch as well. HPD is not enabled for eDP as of now.

-- 
regards,
Sivakumar


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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Mika Kahola]

On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
> 
> 
> On 4/28/2015 1:44 PM, Mika Kahola wrote:
> > On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
> >> On 4/28/2015 12:13 PM, Mika Kahola wrote:
> >>> This patch adds DP link training optimization by reusing the
> >>> previously trained values.
> >>>
> >>> v2:
> >>> - rebase
> >>>
> >>> V3:
> >>> - rebase
> >>>
> >>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/intel_dp.c | 2 +-
> >>>    1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >>> index 15adafc..bb1a8d0 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>> @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >>>    	intel_dp->DP = DP;
> >>>    
> >>>    	if (channel_eq) {
> >>> -		intel_dp->train_set_valid = is_edp(intel_dp);
> >>> +		intel_dp->train_set_valid = true;
> >>>    		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> >>>    	}
> >>>    }
> >> any reason why this is split into a separate patch ?
> > I discussed this with Jani and we agreed that one option would be to
> > apply this optimization only for the eDP case. This second patch is for
> > the possibility to cover the general DP.
> >
> > -Mika-
> >
> >
> might be a nit pick so up to you to consider this or not :). since DP is 
> part of the second patch, better to reset "train_set_valid" for long 
> pulse HPD in the second patch as well. HPD is not enabled for eDP as of now.
> 
So, you mean that the second patch could be written as independent of
the first patch? In that way you could choose which patch you apply and
you wouldn't have to apply the both patches to get the DP case covered.


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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Sivakumar Thulasimani]

On 4/28/2015 3:12 PM, Mika Kahola wrote:
> On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
>>
>> On 4/28/2015 1:44 PM, Mika Kahola wrote:
>>> On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
>>>> On 4/28/2015 12:13 PM, Mika Kahola wrote:
>>>>> This patch adds DP link training optimization by reusing the
>>>>> previously trained values.
>>>>>
>>>>> v2:
>>>>> - rebase
>>>>>
>>>>> V3:
>>>>> - rebase
>>>>>
>>>>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/i915/intel_dp.c | 2 +-
>>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>>>> index 15adafc..bb1a8d0 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>>>> @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>>>>>     	intel_dp->DP = DP;
>>>>>     
>>>>>     	if (channel_eq) {
>>>>> -		intel_dp->train_set_valid = is_edp(intel_dp);
>>>>> +		intel_dp->train_set_valid = true;
>>>>>     		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
>>>>>     	}
>>>>>     }
>>>> any reason why this is split into a separate patch ?
>>> I discussed this with Jani and we agreed that one option would be to
>>> apply this optimization only for the eDP case. This second patch is for
>>> the possibility to cover the general DP.
>>>
>>> -Mika-
>>>
>>>
>> might be a nit pick so up to you to consider this or not :). since DP is
>> part of the second patch, better to reset "train_set_valid" for long
>> pulse HPD in the second patch as well. HPD is not enabled for eDP as of now.
>>
> So, you mean that the second patch could be written as independent of
> the first patch? In that way you could choose which patch you apply and
> you wouldn't have to apply the both patches to get the DP case covered.
>
>
nope, i was referring to the following change alone.

@@ -4822,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
  	intel_display_power_get(dev_priv, power_domain);
  
  	if (long_hpd) {
+		/* indicate that we need to restart link training */
+		intel_dp->train_set_valid = false;
  
  
to be specific, if 2nd patch is to enable this optimization for DP, the above change will belong here as well. eDP never has HPD enabled so it will never be hit for eDP only scenario.

-- 
regards,
Sivakumar

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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[Mika Kahola]

On Tue, 2015-04-28 at 15:18 +0530, Sivakumar Thulasimani wrote:
> On 4/28/2015 3:12 PM, Mika Kahola wrote:
> > On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
> >>
> >> On 4/28/2015 1:44 PM, Mika Kahola wrote:
> >>> On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
> >>>> On 4/28/2015 12:13 PM, Mika Kahola wrote:
> >>>>> This patch adds DP link training optimization by reusing the
> >>>>> previously trained values.
> >>>>>
> >>>>> v2:
> >>>>> - rebase
> >>>>>
> >>>>> V3:
> >>>>> - rebase
> >>>>>
> >>>>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >>>>> ---
> >>>>>     drivers/gpu/drm/i915/intel_dp.c | 2 +-
> >>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >>>>> index 15adafc..bb1a8d0 100644
> >>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>>>> @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >>>>>     	intel_dp->DP = DP;
> >>>>>     
> >>>>>     	if (channel_eq) {
> >>>>> -		intel_dp->train_set_valid = is_edp(intel_dp);
> >>>>> +		intel_dp->train_set_valid = true;
> >>>>>     		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> >>>>>     	}
> >>>>>     }
> >>>> any reason why this is split into a separate patch ?
> >>> I discussed this with Jani and we agreed that one option would be to
> >>> apply this optimization only for the eDP case. This second patch is for
> >>> the possibility to cover the general DP.
> >>>
> >>> -Mika-
> >>>
> >>>
> >> might be a nit pick so up to you to consider this or not :). since DP is
> >> part of the second patch, better to reset "train_set_valid" for long
> >> pulse HPD in the second patch as well. HPD is not enabled for eDP as of now.
> >>
> > So, you mean that the second patch could be written as independent of
> > the first patch? In that way you could choose which patch you apply and
> > you wouldn't have to apply the both patches to get the DP case covered.
> >
> >
> nope, i was referring to the following change alone.
> 
> @@ -4822,6 +4843,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>   	intel_display_power_get(dev_priv, power_domain);
>   
>   	if (long_hpd) {
> +		/* indicate that we need to restart link training */
> +		intel_dp->train_set_valid = false;
>   
>   
> to be specific, if 2nd patch is to enable this optimization for DP, the above change will belong here as well. eDP never has HPD enabled so it will never be hit for eDP only scenario.
> 
Ok, now I'm following you. I rephrase the patch set so the HPD is taken
into consideration on this second patch as well. 


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Re: [PATCH v3 2/2] drm/i915: DP link training optimization

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6274
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  301/301              301/301
SNB                                  318/318              318/318
IVB                                  345/345              345/345
BYT                 -1              285/285              284/285
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@kms_setmode@invalid-clone-exclusive-crtc      PASS(7)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found
WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
Note: You need to pay more attention to line start with '*'
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