Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing

[Nick Hoath <nicholas.hoath@intel.com>]

On 29/04/2015 13:26, Deak, Imre wrote:
> On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>>   2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 91eef06..d34432b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells {
>>   #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
>>   #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
>>   #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
>> +#define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
>>   #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
>>
>>   #define GEN9_HALF_SLICE_CHICKEN5	0xe188
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 5aad253..eebee73 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
>>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>>   			  STALL_DOP_GATING_DISABLE);
>>
>> +	/* WaDisableSbeCacheDispatchPortSharing:bxt */
>> +	if (INTEL_REVID(dev) <= BXT_REVID_B0) {
>> +		WA_SET_BIT_MASKED(
>> +			GEN7_HALF_SLICE_CHICKEN1,
>> +			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>> +	}
>> +
>
> This looks ok, but according to the WA DB it should also be added for
> SKL (<=F0) in gen9_init_workarounds.
>

That would work against the concept of keeping these patches as 
bisectable as possible - Enabling these WAs for other SoCs should be 
done as another patch/patchset.

>>   	return 0;
>>   }
>>
>
>

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