Re: [PATCH v4] drm/i915/chv: Set min freq to efficient frequency on chv

Deepak S
2015-05-09T05:37:36Z

On Friday 08 May 2015 10:09 PM, Ville Syrjälä wrote:
> On Fri, May 08, 2015 at 08:43:12PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
>> Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
>> frequency to RPn, punit is failing to change the input voltage to
>> minimum :(
> As I mentioned I've been unable to reproduce that particular problem
> on my BSW. Perhaps add a note about that in the commit message.
>
Issue is Vgg_in voltage not getting dropped :(. Vnn observation is same as what your seeing.
We saw this issue on CHV platform and confirmed by punit team.
Let me update the commit msg.

>> Since Punit validates the rps range [RPe, RP0]. This patch
>> removes unused cherryview_rps_min_freq function.
> But I can accept that we should stick to the validated range, so I
> can slap an r-b on the patch anyway:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> v2: Change commit message
>>
>> v3: set min_freq before idle_freq (chris)
>>
>> v4: Squash 'Remove unused rps min function' patch
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 21 ++-------------------
>> 1 file changed, 2 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 852f756..b6b14a4 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4689,24 +4689,6 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
>> return rp1;
>> }
>>
>> -static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>> -{
>> - struct drm_device *dev = dev_priv->dev;
>> - u32 val, rpn;
>> -
>> - if (dev->pdev->revision >= 0x20) {
>> - val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
>> - rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
>> - FB_GFX_FREQ_FUSE_MASK);
>> - } else { /* For pre-production hardware */
>> - val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
>> - rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
>> - PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
>> - }
>> -
>> - return rpn;
>> -}
>> -
>> static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
>> {
>> u32 val, rp1;
>> @@ -4958,7 +4940,8 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>> intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
>> dev_priv->rps.rp1_freq);
>>
>> - dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>> + /* PUnit validated range is only [RPe, RP0] */
>> + dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
>> DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>> intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>> dev_priv->rps.min_freq);
>> --
>> 1.9.1