Re: [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN

["Kannan, Vandana" <vandana.kannan@intel.com>]

On 5/7/2015 2:57 PM, Imre Deak wrote:
> On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
>> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
>> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>>
>> VCO calculated based on the formula:
>> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
>> Fast Clock = Desired Output / 2
>> VCO = Fast Clock * P1 * P2
>>
>> Prop_coeff, int_coeff, and tdctargetcnt modified according to above
>> calculation.
>>
>> BUN 2: Port PLLs require additional programming at certain frequencies -
>> DCO amplitude in PORT_PLL_10
>>
>> Review comments from Siva which were addressed in the initial version of the
>> patch.
>> 	- Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
>> 	- Calculate for HDMI
>> 	- Correct values for vco = 5.4
>> 	- return in case of invalid vco range
>>
>> v2: Imre's review comments addressed
>> 	- change dcoampovr_en to dcoampovr_en_h
>> 	- change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
>> 	- Correct lane stagger value for 324MHz
>> 	- Make coef common for HDMI and DP
>> 	- remove superfluous comments
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>>   drivers/gpu/drm/i915/i915_reg.h  |  6 ++++
>>   drivers/gpu/drm/i915/intel_ddi.c | 69 ++++++++++++++++++++++++++++++----------
>>   3 files changed, 60 insertions(+), 17 deletions(-)

[...]

>>   /* pre-calculated values for DP linkrates */
>>   static struct bxt_clk_div bxt_dp_clk_val[7] = {
>> -	/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> -	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
>> -	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
>> -	/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> -	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
>> -	/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> -	/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>> +	/* 162 */ {4, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
>> +	/* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0, 15, 0xd},
>> +	/* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0, 15, 0x18},
>> +	/* 216 */ {3, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
>> +	/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 3, 9, 1, 15, 0xd},
>> +	/* 324 */ {4, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18},
>> +	/* 432 */ {3, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18}
>
> We calculate all of prop_coef, int_coef, gain_ctl, targ_cnt,
> dcoapovr_en_h, dco_amp, so no need to have fixed values for these. The
> corresponding fields should be removed from bxt_clk_div and replaced
> with local vars in bxt_ddi_pll_select.
>
Agree.
Made changes separately and thought of sending as another patch a little 
later, but I'll include the changes in this patch and resend.

Thanks,
Vandana
>>   };
>>
>>   static bool
>> @@ -1359,6 +1361,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   {
>>   	struct intel_shared_dpll *pll;
>>   	struct bxt_clk_div clk_div = {0};
>> +	int vco = 0;
>>
>>   	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>>   		intel_clock_t best_clock;
>> @@ -1382,11 +1385,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   		clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
>>   		clk_div.m2_frac_en = clk_div.m2_frac != 0;
>>
>> -		/* FIXME: set coef, gain, targcnt based on freq band */
>> -		clk_div.prop_coef = 5;
>> -		clk_div.int_coef = 11;
>> -		clk_div.gain_ctl = 2;
>> -		clk_div.targ_cnt = 9;
>> +		vco = best_clock.vco;
>>   		if (clock > 270000)
>>   			clk_div.lanestagger = 0x18;
>>   		else if (clock > 135000)
>> @@ -1416,6 +1415,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   			clk_div = bxt_dp_clk_val[0];
>>   			DRM_ERROR("Unknown link rate\n");
>>   		}
>> +		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>> +	}
>> +

[...]

>>   	/* Recalibrate with new settings */
>>   	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
>> @@ -2433,6 +2469,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>>   	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
>>   	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
>>   	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
>> +	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
>>   	/*
>>   	 * While we write to the group register to program all lanes at once we
>>   	 * can read only lane registers. We configure all lanes the same way, so
>
>
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