drm/i915/hsw/bdw: Enable resource streamer

drm/i915/hsw/bdw: Enable resource streamer

[Abdiel Janulgue]

This is a re-spin of my resource streamer patchset from a year ago.
The resource streamer is a hw-feature that helps in reducing commands
submitted by the CPU.

We have finally have the Mesa optimization that requires the use of
this interface.

Abdiel Janulgue (2):
      drm/i915/hsw/bdw: Expose I915_EXEC_RESOURCE_STREAMER flag
      drm/i915/hsw/bdw: Enable resource streamer bits on MI_BATCH_BUFFER_START

 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c    |  6 ++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h    |  1 +
 include/uapi/drm/i915_drm.h                |  7 ++++++-
 5 files changed, 26 insertions(+), 3 deletions(-)

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[PATCH 1/2] drm/i915/hsw/bdw: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

Ensures that the batch buffer is executed by the resource streamer

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h    |  1 +
 include/uapi/drm/i915_drm.h                |  7 ++++++-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a3190e79..afbd3c16 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1474,6 +1474,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 	} else
 		ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
 
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 "
+				  "and above\n");
+			return -EINVAL;
+		}
+		if (ring->id != RCS) {
+			DRM_DEBUG("RS is not available on %s)\n",
+				 ring->name);
+			return -EINVAL;
+		}
+
+		dispatch_flags |= I915_DISPATCH_RS;
+	}
+
 	if (!intel_ring_initialized(ring)) {
 		DRM_DEBUG("execbuf with invalid ring: %d\n",
 			  (int)(args->flags & I915_EXEC_RING_MASK));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c761fe0..3521bc0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -167,6 +167,7 @@ struct  intel_engine_cs {
 					       unsigned dispatch_flags);
 #define I915_DISPATCH_SECURE 0x1
 #define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_RS     0x4
 	void		(*cleanup)(struct intel_engine_cs *ring);
 
 	/* GEN8 signal/wait table - never trust comments!
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 551b673..a4c1a5c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -760,7 +760,12 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_BSD_RING1		(1<<13)
 #define I915_EXEC_BSD_RING2		(2<<13)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ *  the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER     (1<<16)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER <<1)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.9.1

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[PATCH 2/2] drm/i915/hsw/bdw: Enable resource streamer bits on MI_BATCH_BUFFER_START

[Abdiel Janulgue]

Adds support for executing the resource streamer on BDW

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..238bb25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -356,6 +356,7 @@
 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
 #define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
 #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
+#define   MI_BATCH_RESOURCE_STREAMER (1<<10)
 
 #define MI_PREDICATE_SRC0	(0x2400)
 #define MI_PREDICATE_SRC1	(0x2408)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 441e250..9045144 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2385,7 +2385,8 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 		return ret;
 
 	/* FIXME(BDW): Address space and security selectors. */
-	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
+			(dispatch_flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0));
 	intel_ring_emit(ring, lower_32_bits(offset));
 	intel_ring_emit(ring, upper_32_bits(offset));
 	intel_ring_emit(ring, MI_NOOP);
@@ -2408,7 +2409,8 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 	intel_ring_emit(ring,
 			MI_BATCH_BUFFER_START |
 			(dispatch_flags & I915_DISPATCH_SECURE ?
-			 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
+			 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
+			(dispatch_flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0));
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
 	intel_ring_advance(ring);
-- 
1.9.1

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Re: drm/i915/hsw/bdw: Enable resource streamer

[Chris Wilson]

On Mon, May 11, 2015 at 12:01:10PM +0300, Abdiel Janulgue wrote:
> This is a re-spin of my resource streamer patchset from a year ago.
> The resource streamer is a hw-feature that helps in reducing commands
> submitted by the CPU.

Did you check that the contexts we allocate are large enough to hold the
extra RS state? I can't remember if the size we settled on was
sufficient or not...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: drm/i915/hsw/bdw: Enable resource streamer

[Abdiel Janulgue]

On 05/11/2015 12:26 PM, Chris Wilson wrote:
> On Mon, May 11, 2015 at 12:01:10PM +0300, Abdiel Janulgue wrote:
>> This is a re-spin of my resource streamer patchset from a year ago.
>> The resource streamer is a hw-feature that helps in reducing commands
>> submitted by the CPU.
> 
> Did you check that the contexts we allocate are large enough to hold the
> extra RS state? I can't remember if the size we settled on was
> sufficient or not...
> -Chris
> 

I checked HSW_CXT_TOTAL_SIZE and GEN8_CXT_TOTAL_SIZE to the values in
Bspec, the sizes does indeed contain the resource streamer dwords. So I
guess the answer is it's sufficient.

-Abdiel
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Re: [PATCH 1/2] drm/i915/hsw/bdw: Expose I915_EXEC_RESOURCE_STREAMER flag

[Chris Wilson]

On Mon, May 11, 2015 at 12:01:11PM +0300, Abdiel Janulgue wrote:
> Ensures that the batch buffer is executed by the resource streamer
> 
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |  1 +
>  include/uapi/drm/i915_drm.h                |  7 ++++++-
>  3 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index a3190e79..afbd3c16 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1474,6 +1474,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>  	} else
>  		ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
>  
> +	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
> +		if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
> +			DRM_DEBUG("RS is only allowed for Haswell, Gen8 "
> +				  "and above\n");
> +			return -EINVAL;
> +		}
> +		if (ring->id != RCS) {
> +			DRM_DEBUG("RS is not available on %s)\n",
> +				 ring->name);
> +			return -EINVAL;
> +		}
> +
> +		dispatch_flags |= I915_DISPATCH_RS;
> +	}
> +
>  	if (!intel_ring_initialized(ring)) {

Please don't split the conversion from args->flags to ring from its
subsequent EINVAL check.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH 1/2] drm/i915/hsw/bdw: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

On 05/12/2015 12:49 PM, Chris Wilson wrote:
> On Mon, May 11, 2015 at 12:01:11PM +0300, Abdiel Janulgue wrote:
>> Ensures that the batch buffer is executed by the resource streamer
>>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/intel_ringbuffer.h    |  1 +
>>  include/uapi/drm/i915_drm.h                |  7 ++++++-
>>  3 files changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> index a3190e79..afbd3c16 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> @@ -1474,6 +1474,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>>  	} else
>>  		ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
>>  
>> +	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
>> +		if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
>> +			DRM_DEBUG("RS is only allowed for Haswell, Gen8 "
>> +				  "and above\n");
>> +			return -EINVAL;
>> +		}
>> +		if (ring->id != RCS) {
>> +			DRM_DEBUG("RS is not available on %s)\n",
>> +				 ring->name);
>> +			return -EINVAL;
>> +		}
>> +
>> +		dispatch_flags |= I915_DISPATCH_RS;
>> +	}
>> +
>>  	if (!intel_ring_initialized(ring)) {
> 
> Please don't split the conversion from args->flags to ring from its
> subsequent EINVAL check.
> -Chris
> 

I'll include this change in the next version.
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[PATCH 1/2] drm/i915/hsw/bdw: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

Ensures that the batch buffer is executed by the resource streamer

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h    |  1 +
 include/uapi/drm/i915_drm.h                |  7 ++++++-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a3190e79..f937ad0 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1485,6 +1485,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 "
+				  "and above\n");
+			return -EINVAL;
+		}
+		if (ring->id != RCS) {
+			DRM_DEBUG("RS is not available on %s)\n",
+				 ring->name);
+			return -EINVAL;
+		}
+
+		dispatch_flags |= I915_DISPATCH_RS;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	ret = i915_mutex_lock_interruptible(dev);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c761fe0..3521bc0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -167,6 +167,7 @@ struct  intel_engine_cs {
 					       unsigned dispatch_flags);
 #define I915_DISPATCH_SECURE 0x1
 #define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_RS     0x4
 	void		(*cleanup)(struct intel_engine_cs *ring);
 
 	/* GEN8 signal/wait table - never trust comments!
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 551b673..a4c1a5c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -760,7 +760,12 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_BSD_RING1		(1<<13)
 #define I915_EXEC_BSD_RING2		(2<<13)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ *  the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER     (1<<16)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER <<1)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.9.1

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