Re: [PATCH 66/89] drm/i915/skl: Implementation of SKL DPLL programming

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

Hi,

On 09/04/2014 12:27 PM, Damien Lespiau wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@intel.com>
>
> This patch implements SKL DPLL programming that includes:
>          - DPLL allocation
>          - wide range PLL calculation and programming
>          - DP link rate programming
>          - DDI to DPLL mapping
>
> v2: Incorporated following changes
>          - Added vfunc for function required outside
>          - Fixed multiple comments in WRPLL calculation
>
> v3: - Fix the DCO computation
>      - Move the initialization up to not clobber the computed values
>      - Use the correct macro for DP link rate programming.
>      - Use wait_for() to wait for the PLL locked bit
>
> v4: Rebase on top of nigthly (Damien)
>
> v5: A few code cleanups in the WRPLL computation (Damien)
>      - Use uint32_t when possible
>      - Use abs_diff() in the WRPLL computation
>      - Make the 64bits divisions use div64_u64()
>      - Fix typo in dco_central_feq_deviation (freq)
>      - Replace the chain of breaks with a goto
>
> v6: Port of the patch to work on top of the shared DPLLs (Damien)
> v7: Don't try to handle eDP in ddi_pll_select() (Damien)

[snip]

> +static bool
> +skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> +		   struct intel_encoder *intel_encoder,
> +		   int clock)
> +{
> +	struct intel_shared_dpll *pll;
> +	uint32_t ctrl1, cfgcr1, cfgcr2;
> +
> +	/*
> +	 * See comment in intel_dpll_hw_state to understand why we always use 0
> +	 * as the DPLL id in this function.
> +	 */
> +
> +	ctrl1 = DPLL_CTRL1_OVERRIDE(0);
> +
> +	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> +		struct skl_wrpll_params wrpll_params = { 0, };
> +
> +		ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
> +
> +		skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
> +
> +		cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
> +			 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
> +			 wrpll_params.dco_integer;
> +
> +		cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
> +			 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
> +			 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
> +			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
> +			 wrpll_params.central_freq;
> +	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> +		struct drm_encoder *encoder = &intel_encoder->base;
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		switch (intel_dp->link_bw) {
> +		case DP_LINK_BW_1_62:
> +			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
> +			break;
> +		case DP_LINK_BW_2_7:
> +			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
> +			break;
> +		case DP_LINK_BW_5_4:
> +			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
> +			break;
> +		}
> +
> +		cfgcr1 = cfgcr2 = 0;
> +	} else /* eDP */
> +		return true;
>
> +	intel_crtc->config.dpll_hw_state.ctrl1 = ctrl1;
> +	intel_crtc->config.dpll_hw_state.cfgcr1 = cfgcr1;
> +	intel_crtc->config.dpll_hw_state.cfgcr2 = cfgcr2;

The return before updating the dpll_hw_state in the eDP case interacts with:

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Tue Apr 21 17:13:21 2015 +0300

     drm/i915: Preserve shared DPLL information in new pipe_config

And results with a bunch of:

[drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 
(expected 0x00000000, found 0x00000001)

On boot and afterwards.

Not sure what is the fix so maybe someone knows?

Regards,

Tvrtko
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