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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/12] drm/i915: Write the SDVO reg twice on IBX
Date: Thu, 21 May 2015 12:20:43 -0700	[thread overview]
Message-ID: <555E300B.80308@virtuousgeek.org> (raw)
In-Reply-To: <1430835458-11187-8-git-send-email-ville.syrjala@linux.intel.com>

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On IBX the SDVO/HDMI register write may be masked when enabling the
> port, so it may need to written twice. The HDMI code does this, but
> the SDVO code does not. Add the workaround to the SDVO code as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0a06257..e3e9c98 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
>  		I915_WRITE(intel_sdvo->sdvo_reg, val);
>  		POSTING_READ(intel_sdvo->sdvo_reg);
> +		/*
> +		 * HW workaround, need to write this twice for issue
> +		 * that may result in first write getting masked.
> +		 */
> +		if (HAS_PCH_IBX(dev)) {
> +			I915_WRITE(intel_sdvo->sdvo_reg, val);
> +			POSTING_READ(intel_sdvo->sdvo_reg);
> +		}
>  		return;
>  	}
>  
> 

This must be the missing fix to all our SDVO problems.  (One can hope.)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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  reply	other threads:[~2015-05-21 19:27 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-05 14:17 [PATCH 00/12] drm/i915: PCH modeset sequence fixes ville.syrjala
2015-05-05 14:17 ` [PATCH 01/12] drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() ville.syrjala
2015-05-21 19:04   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 02/12] drm/i915: Remove the double register write " ville.syrjala
2015-05-21 19:04   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 03/12] drm/i915: Clarfify the DP code platform checks ville.syrjala
2015-05-21 19:10   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 04/12] drm/i915: Clean up the CPT DP .get_hw_state() port readout ville.syrjala
2015-05-21 19:16   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 05/12] drm/i915: Fix DP enhanced framing for CPT ville.syrjala
2015-05-21 19:19   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 06/12] drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox() ville.syrjala
2015-05-06 11:30   ` Daniel Vetter
2015-05-05 14:17 ` [PATCH 07/12] drm/i915: Write the SDVO reg twice on IBX ville.syrjala
2015-05-21 19:20   ` Jesse Barnes [this message]
2015-05-05 14:17 ` [PATCH 08/12] drm/i915: Fix the IBX transcoder B workarounds ville.syrjala
2015-05-21 19:23   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 09/12] drm/i915: Disable HDMI port after the pipe on PCH platforms ville.syrjala
2015-05-21 19:24   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 10/12] drm/i915: Disable SDVO " ville.syrjala
2015-05-21 19:26   ` Jesse Barnes
2015-05-21 21:24     ` Daniel Vetter
2015-05-05 14:17 ` [PATCH 11/12] drm/i915: Disable CRT port after " ville.syrjala
2015-05-21 19:26   ` Jesse Barnes
2015-05-05 14:17 ` [PATCH 12/12] drm/i915: Disable FDI RX/TX before the ports ville.syrjala
2015-05-21 19:27   ` Jesse Barnes

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