Re: [PATCH 11/21] drm/i915/gtt: Introduce fill_page_dma()

Daniel Vetter
2015-06-15T10:13:27Z

On Tue, Jun 02, 2015 at 06:01:27PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 02, 2015 at 03:51:26PM +0100, Michel Thierry wrote:
> > On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
> > > When we setup page directories and tables, we point the entries
> > > to a to the next level scratch structure. Make this generic
> > > by introducing a fill_page_dma which maps and flushes. We also
> > > need 32 bit variant for legacy gens.
> > >
> > > v2: Fix flushes and handle valleyview (Ville)
> > >
> > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_gem_gtt.c | 71 +++++++++++++++++++------------------
> > > 1 file changed, 37 insertions(+), 34 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index f747bd3..d020b5e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -330,6 +330,31 @@ static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
> > > memset(p, 0, sizeof(*p));
> > > }
> > >
> > > +static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> > > + const uint64_t val)
> > > +{
> > > + int i;
> > > + uint64_t * const vaddr = kmap_atomic(p->page);
> > > +
> > > + for (i = 0; i < 512; i++)
> > > + vaddr[i] = val;
> > > +
> > > + if (!HAS_LLC(dev) && !IS_VALLEYVIEW(dev))
> > > + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> >
> > Cherryview returns true to IS_VALLEYVIEW().
> >
> > You can use(!HAS_LLC && IS_CHERRYVIEW) instead to flush in chv, but not
> > in vlv... But to make it bxt-proof, (!HAS_LLC && INTEL_INFO(dev)->gen >=
> > 8) is probably better.
>
> Has someone actually confirmed that BXT needs the clflush?

Ping on this one ... I'd like to know the answer ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation