From mboxrd@z Thu Jan 1 00:00:00 1970 From: Edgardo Gho Subject: Pegatron BYT-T1 eDP/LVDS resolution problem (VBT vs EDID) Date: Wed, 17 Jun 2015 17:14:26 -0400 Message-ID: <5581E332.7080908@telikin.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0357739070==" Return-path: Received: from p3plsmtpa06-05.prod.phx3.secureserver.net (p3plsmtpa06-05.prod.phx3.secureserver.net [173.201.192.106]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F6986E093 for ; Wed, 17 Jun 2015 14:21:36 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0357739070== Content-Type: multipart/alternative; boundary="------------090907070607060908030302" This is a multi-part message in MIME format. --------------090907070607060908030302 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Hi, I have an AIO computer with a Pegatron BYT-T1 motherboard. Looks like a cheap motherboard (using J1900). It has an innolux 1366x768 panel (LVDS). The Motherboard also has LVDS written on the connector. I'm running kernel 4.0.5 on it (tinycore custom kernel) and xrandr displays the port as eDP1 (not LVDS). From what I can tell the panel is LVDS so I'm a little confused why the kernel picks it up as eDP. The CPU is valleyview. The problem I have is this: When drm/i915 reads the EDID on eDP1, it gets a bunch of stuff (including 1920x1080) and sets the resolution to that. But the panel supports 1366x768 as max. That seems to be saved on VBT since if I use vga=0x37f I get 1366x768 on fb. But when drm reads 1920x1080 from EDID it sets that and the panel goes into a weird mode (displaying colors) which I believe is a testing mode. I could try to fix the EDID, and also could generate one and use the drm_kms_helper to pass a binary EDID. What I don't understand is where is this EDID coming from. LVDS supports EDID read? I don't see any i2c cable on the LVDS cable so I don't understand how it can be reading the EDID. Is the EDID saved on BIOS somehow? I changed the code as suggested by this thread: VLV: eDP: panel timings / resolution data from VBT, not via i2c from eDP EDID http://www.spinics.net/lists/intel-gfx/msg64312.html and I'm not letting edp read the EDID, so it fallbacks to VBT and everything works great. But I'm still not convinced that the EDID data comes from the LVDS Panel (since it should have different info) Hope anyone can share some insights on what is going on. Thanks -- Edgardo Gho edgardo.g@telikin.com --------------090907070607060908030302 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hi,
I have an AIO computer with a Pegatron BYT-T1 motherboard. Looks like a cheap motherboard (using J1900).
It has an innolux 1366x768 panel (LVDS). The Motherboard also has LVDS written on the connector.
I'm running kernel 4.0.5 on it (tinycore custom kernel) and xrandr displays the port as eDP1 (not LVDS).
From what I can tell the panel is LVDS so I'm a little confused why the kernel picks it up as eDP. The CPU is valleyview.

The problem I have is this:
When drm/i915 reads the EDID on eDP1, it gets a bunch of stuff (including 1920x1080) and sets the resolution to that.
But the panel supports 1366x768 as max. That seems to be saved on VBT since if I use vga=3D0x37f I get 1366x768 on fb.
But when drm reads 1920x1080 from EDID it sets that and the panel goes into a weird mode (displaying colors) which I believe is a testing mode.

I could try to fix the EDID, and also could generate one and use the drm_kms_helper to pass a binary EDID.
What I don't understand is where is this EDID coming from. LVDS supports EDID read? I don't see any i2c cable on the LVDS cable so I don't understand how it can be reading the EDID.
Is the EDID saved on BIOS somehow?

I changed the code as suggested by this thread:
VLV: eDP: panel timings / resolution data from VBT,=C2=A0=C2=A0=C2=A0= not via i2c from eDP EDID
http://www.spinics.net/lists/intel-gfx/msg643= 12.html

and I'm not letting edp read the EDID, so it fallbacks to VBT and everything works great.
But I'm still not convinced that the EDID data comes from the LVDS Panel (since it should have different info)

Hope anyone can share some insights on what is going on.
Thanks
--=20
Edgardo Gho
edgardo.g@telikin.com
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