Re: [PATCH v6 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

Daniel Vetter
2015-06-22T15:38:35Z

On Fri, Jun 19, 2015 at 07:12:21PM +0100, Chris Wilson wrote:
> On Fri, Jun 19, 2015 at 06:37:13PM +0100, Arun Siluvery wrote:
> > In Indirect context w/a batch buffer,
> > +WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
> >
> > v2: Add LRI commands to set/reset bit that invalidates coherent lines,
> > update WA to include programming restrictions and exclude CHV as
> > it is not required (Ville)
> >
> > v3: Avoid unnecessary read when it can be done by reading register once (Chris).
> >
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Dave Gordon <david.s.gordon@intel.com>
> > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

Merged up to this patch, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation