[PATCH resend 1/5] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START

[PATCH resend 1/5] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START

[Abdiel Janulgue]

Adds support for enabling the resource streamer on the legacy
ringbuffer for HSW and GEN8.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..238bb25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -356,6 +356,7 @@
 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
 #define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
 #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
+#define   MI_BATCH_RESOURCE_STREAMER (1<<10)
 
 #define MI_PREDICATE_SRC0	(0x2400)
 #define MI_PREDICATE_SRC1	(0x2408)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 441e250..715cb2a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2385,7 +2385,9 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 		return ret;
 
 	/* FIXME(BDW): Address space and security selectors. */
-	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
+			(dispatch_flags & I915_DISPATCH_RS ?
+			 MI_BATCH_RESOURCE_STREAMER : 0));
 	intel_ring_emit(ring, lower_32_bits(offset));
 	intel_ring_emit(ring, upper_32_bits(offset));
 	intel_ring_emit(ring, MI_NOOP);
@@ -2408,7 +2410,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 	intel_ring_emit(ring,
 			MI_BATCH_BUFFER_START |
 			(dispatch_flags & I915_DISPATCH_SECURE ?
-			 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
+			 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
+			(dispatch_flags & I915_DISPATCH_RS ?
+			 MI_BATCH_RESOURCE_STREAMER : 0));
 	/* bit0-7 is the length on GEN6+ */
 	intel_ring_emit(ring, offset);
 	intel_ring_advance(ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c761fe0..3521bc0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -167,6 +167,7 @@ struct  intel_engine_cs {
 					       unsigned dispatch_flags);
 #define I915_DISPATCH_SECURE 0x1
 #define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_RS     0x4
 	void		(*cleanup)(struct intel_engine_cs *ring);
 
 	/* GEN8 signal/wait table - never trust comments!
-- 
1.9.1

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[PATCH resend 2/5] drm/i915: Enable Resource Streamer state save/restore on MI_SET_CONTEXT

[Abdiel Janulgue]

Also clarify comments on context size that the extra state for
Resource Streamer is included.

v2: Don't remove the extended save/restore enabled for older
    platforms. (Ville)
    Use new MI_SET_CONTEXT defines for HSW RS save/restore state
    instead of extended save/restore. (Daniel)

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 4 +++-
 drivers/gpu/drm/i915/i915_reg.h         | 5 ++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f3e84c4..a29dbcd 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -509,7 +509,9 @@ mi_set_context(struct intel_engine_cs *ring,
 	}
 
 	/* These flags are for resource streamer on HSW+ */
-	if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
+	if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
+		flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
+	else if (INTEL_INFO(ring->dev)->gen < 8)
 		flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
 
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 238bb25..2b1321d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -316,6 +316,8 @@
 #define   MI_RESTORE_EXT_STATE_EN	(1<<2)
 #define   MI_FORCE_RESTORE		(1<<1)
 #define   MI_RESTORE_INHIBIT		(1<<0)
+#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
+#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
 #define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
 #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
@@ -2498,7 +2500,8 @@ enum skl_disp_power_wells {
  * valid. Now, docs explain in dwords what is in the context object. The full
  * size is 70720 bytes, however, the power context and execlist context will
  * never be saved (power context is stored elsewhere, and execlists don't work
- * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
+ * on HSW) - so the final size, including the extra state required for the
+ * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
  */
 #define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
 /* Same as Haswell, but 72064 bytes now. */
-- 
1.9.1

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[PATCH resend 3/5] drm/i915: Enable resource streamer on Execlists

[Abdiel Janulgue]

GEN8 and above uses Execlists by default instead of the legacy
ringbuffer for batch execution. This patch enables the resource
streamer bits when required.

Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com>
This version also adds the required bits to enable GEN8 Resource
Streamer context save and restore for Execlists.

Cc: ville.syrjala@linux.intel.com
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++--
 drivers/gpu/drm/i915/intel_lrc.h | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fcb074b..b015e96 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1172,7 +1172,10 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
 		return ret;
 
 	/* FIXME(BDW): Address space and security selectors. */
-	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
+				(ppgtt<<8) |
+				(dispatch_flags & I915_DISPATCH_RS ?
+				 MI_BATCH_RESOURCE_STREAMER : 0));
 	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
 	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
 	intel_logical_ring_emit(ringbuf, MI_NOOP);
@@ -1726,7 +1729,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
 	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
 	reg_state[CTX_CONTEXT_CONTROL+1] =
 		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
-				CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+				   CTX_CTRL_RS_CTX_ENABLE);
 	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
 	reg_state[CTX_RING_HEAD+1] = 0;
 	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index adb731e4..de6087a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -32,6 +32,7 @@
 #define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
 #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
+#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
 #define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
 
-- 
1.9.1

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Re: [PATCH resend 3/5] drm/i915: Enable resource streamer on Execlists

[Siluvery, Arun]

On 16/06/2015 11:39, Abdiel Janulgue wrote:
> GEN8 and above uses Execlists by default instead of the legacy
> ringbuffer for batch execution. This patch enables the resource
> streamer bits when required.
>
> Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com>
> This version also adds the required bits to enable GEN8 Resource
> Streamer context save and restore for Execlists.
>
> Cc: ville.syrjala@linux.intel.com
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++--
>   drivers/gpu/drm/i915/intel_lrc.h | 1 +
>   2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..b015e96 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1172,7 +1172,10 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
>   		return ret;
>
>   	/* FIXME(BDW): Address space and security selectors. */
> -	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> +	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> +				(ppgtt<<8) |
> +				(dispatch_flags & I915_DISPATCH_RS ?
> +				 MI_BATCH_RESOURCE_STREAMER : 0));
>   	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
>   	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
>   	intel_logical_ring_emit(ringbuf, MI_NOOP);
> @@ -1726,7 +1729,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
>   	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
>   	reg_state[CTX_CONTEXT_CONTROL+1] =
>   		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
> -				CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> +				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
> +				   CTX_CTRL_RS_CTX_ENABLE);
>   	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
>   	reg_state[CTX_RING_HEAD+1] = 0;
>   	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index adb731e4..de6087a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -32,6 +32,7 @@
>   #define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
>   #define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
>   #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
> +#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
>   #define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
>   #define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)
>
>
looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>

regards
Arun

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[PATCH resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

This will let userspace know whether Resource Streamer is supported
in the kernel.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 68e0c85..10d4ead 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -163,6 +163,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 		if (!value)
 			return -ENODEV;
 		break;
+	case I915_PARAM_HAS_RESOURCE_STREAMER:
+		value = 1;
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 551b673..40ab1c8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -350,6 +350,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_REVISION              32
 #define I915_PARAM_SUBSLICE_TOTAL	 33
 #define I915_PARAM_EU_TOTAL		 34
+#define I915_PARAM_HAS_RESOURCE_STREAMER 35
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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[PATCH v2 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

This will let userspace know whether Resource Streamer is supported
in the kernel.

v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
    I915_PARAM_HAS_GPU_RESET.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 88795d2..e7ad30f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -168,6 +168,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 			i915.reset &&
 			intel_has_gpu_reset(dev);
 		break;
+	case I915_PARAM_HAS_RESOURCE_STREAMER:
+               value = 1;
+               break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f88cc1c..51137bd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -355,6 +355,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_SUBSLICE_TOTAL	 33
 #define I915_PARAM_EU_TOTAL		 34
 #define I915_PARAM_HAS_GPU_RESET	 35
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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Re: [PATCH v2 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Chris Wilson]

On Tue, Jun 16, 2015 at 03:02:58PM +0300, Abdiel Janulgue wrote:
> This will let userspace know whether Resource Streamer is supported
> in the kernel.
> 
> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
>     I915_PARAM_HAS_GPU_RESET.
> 
> Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>  include/uapi/drm/i915_drm.h     | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 88795d2..e7ad30f 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -168,6 +168,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>  			i915.reset &&
>  			intel_has_gpu_reset(dev);
>  		break;
> +	case I915_PARAM_HAS_RESOURCE_STREAMER:
> +               value = 1;

Really, we support the resource streamer on all platforms in all
configurations? I think you jest!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[PATCH v3 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

This will let userspace know whether Resource Streamer is supported
in the kernel.

v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
    I915_PARAM_HAS_GPU_RESET.
v3: Only advertise RS support for hardware that supports it.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 88795d2..4f55f51 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -168,6 +168,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 			i915.reset &&
 			intel_has_gpu_reset(dev);
 		break;
+	case I915_PARAM_HAS_RESOURCE_STREAMER:
+		value = IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8;
+               break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f88cc1c..51137bd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -355,6 +355,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_SUBSLICE_TOTAL	 33
 #define I915_PARAM_EU_TOTAL		 34
 #define I915_PARAM_HAS_GPU_RESET	 35
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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Re: [PATCH v3 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
> This will let userspace know whether Resource Streamer is supported
> in the kernel.
> 
> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
>     I915_PARAM_HAS_GPU_RESET.
> v3: Only advertise RS support for hardware that supports it.

Ping. Any status on this one?

> 
> Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>  include/uapi/drm/i915_drm.h     | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 88795d2..4f55f51 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -168,6 +168,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>  			i915.reset &&
>  			intel_has_gpu_reset(dev);
>  		break;
> +	case I915_PARAM_HAS_RESOURCE_STREAMER:
> +		value = IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8;
> +               break;
>  	default:
>  		DRM_DEBUG("Unknown parameter %d\n", param->param);
>  		return -EINVAL;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index f88cc1c..51137bd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -355,6 +355,7 @@ typedef struct drm_i915_irq_wait {
>  #define I915_PARAM_SUBSLICE_TOTAL	 33
>  #define I915_PARAM_EU_TOTAL		 34
>  #define I915_PARAM_HAS_GPU_RESET	 35
> +#define I915_PARAM_HAS_RESOURCE_STREAMER 36
>  
>  typedef struct drm_i915_getparam {
>  	int param;
> 
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Re: [PATCH v3 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

On 06/24/2015 09:30 AM, Abdiel Janulgue wrote:
> 
> 
> On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
>> This will let userspace know whether Resource Streamer is supported
>> in the kernel.
>>
>> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
>>     I915_PARAM_HAS_GPU_RESET.
>> v3: Only advertise RS support for hardware that supports it.
> 
> Ping. Any status on this one?

Chris?

> 
>>
>> Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
>> Cc: Kenneth Graunke <kenneth@whitecape.org>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>>  include/uapi/drm/i915_drm.h     | 1 +
>>  2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index 88795d2..4f55f51 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -168,6 +168,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>>  			i915.reset &&
>>  			intel_has_gpu_reset(dev);
>>  		break;
>> +	case I915_PARAM_HAS_RESOURCE_STREAMER:
>> +		value = IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8;
>> +               break;
>>  	default:
>>  		DRM_DEBUG("Unknown parameter %d\n", param->param);
>>  		return -EINVAL;
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index f88cc1c..51137bd 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -355,6 +355,7 @@ typedef struct drm_i915_irq_wait {
>>  #define I915_PARAM_SUBSLICE_TOTAL	 33
>>  #define I915_PARAM_EU_TOTAL		 34
>>  #define I915_PARAM_HAS_GPU_RESET	 35
>> +#define I915_PARAM_HAS_RESOURCE_STREAMER 36
>>  
>>  typedef struct drm_i915_getparam {
>>  	int param;
>>
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Re: [PATCH v3 resend 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Chris Wilson]

On Mon, Jun 29, 2015 at 10:52:22AM +0300, Abdiel Janulgue wrote:
> 
> 
> On 06/24/2015 09:30 AM, Abdiel Janulgue wrote:
> > 
> > 
> > On 06/16/2015 03:41 PM, Abdiel Janulgue wrote:
> >> This will let userspace know whether Resource Streamer is supported
> >> in the kernel.
> >>
> >> v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
> >>     I915_PARAM_HAS_GPU_RESET.
> >> v3: Only advertise RS support for hardware that supports it.
> > 
> > Ping. Any status on this one?
> 
> Chris?

Run it through indent, and I'm happy with it. I think we should make it
a HAS_RESOURCE_STREAMER() macro so we can share the definition between
here and execbuf validation, but that's icing on the cake.
-Chris

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[PATCH v4 4/5] drm/i915: add I915_PARAM_HAS_RESOURCE_STREAMER to i915_getparam

[Abdiel Janulgue]

This will let userspace know whether Resource Streamer is supported
in the kernel.

v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
    I915_PARAM_HAS_GPU_RESET.
v3: Only advertise RS support for hardware that supports it.
v4: Add HAS_RESOURCE_STREAMER() macro (Chris)

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 include/uapi/drm/i915_drm.h     | 1 +
 3 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c5349fa..a42f165 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -167,6 +167,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 		value = i915.enable_hangcheck &&
 			intel_has_gpu_reset(dev);
 		break;
+	case I915_PARAM_HAS_RESOURCE_STREAMER:
+		value = HAS_RESOURCE_STREAMER(dev);
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea9caf2..9968663 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2520,6 +2520,9 @@ struct drm_i915_cmd_table {
 
 #define HAS_CSR(dev)	(IS_SKYLAKE(dev))
 
+#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
+				    INTEL_INFO(dev)->gen >= 8)
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f88cc1c..51137bd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -355,6 +355,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_SUBSLICE_TOTAL	 33
 #define I915_PARAM_EU_TOTAL		 34
 #define I915_PARAM_HAS_GPU_RESET	 35
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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[PATCH resend 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

Ensures that the batch buffer is executed by the resource streamer

v2: Don't skip 1<<15 for the exec flags (Jani Nikula)

Testcase: igt/gem_exec_params
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++++++++++
 include/uapi/drm/i915_drm.h                |  7 ++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a3190e79..ae064f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1485,6 +1485,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
+			return -EINVAL;
+		}
+		if (ring->id != RCS) {
+			DRM_DEBUG("RS is not available on %s\n",
+				 ring->name);
+			return -EINVAL;
+		}
+
+		dispatch_flags |= I915_DISPATCH_RS;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	ret = i915_mutex_lock_interruptible(dev);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 40ab1c8..debccd34 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -761,7 +761,12 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_BSD_RING1		(1<<13)
 #define I915_EXEC_BSD_RING2		(2<<13)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ *  the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER     (1<<15)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.9.1

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[PATCH v3 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

Ensures that the batch buffer is executed by the resource streamer

v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)

Testcase: igt/gem_exec_params
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++++++++++
 include/uapi/drm/i915_drm.h                |  7 ++++++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 600db74..83577c6 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1490,6 +1490,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
+	if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+		if (!HAS_RESOURCE_STREAMER(dev)) {
+			DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
+			return -EINVAL;
+		}
+		if (ring->id != RCS) {
+			DRM_DEBUG("RS is not available on %s\n",
+				 ring->name);
+			return -EINVAL;
+		}
+
+		dispatch_flags |= I915_DISPATCH_RS;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	ret = i915_mutex_lock_interruptible(dev);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 51137bd..e7c29f1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -766,7 +766,12 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_BSD_RING1		(1<<13)
 #define I915_EXEC_BSD_RING2		(2<<13)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ *  the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER     (1<<15)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
-- 
1.9.1

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Re: [PATCH v3 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Chris Wilson]

On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
> Ensures that the batch buffer is executed by the resource streamer
> 
> v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
> v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)
> 
> Testcase: igt/gem_exec_params
> Cc: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

This no longer applies (unrecognised base). Honestly, I would prefer 4&5
squashed together, or 4 after 5 so that we do not declare
HAS_RESOURCE_STREAMER before we accept the RS execbuf.

Minor bit of patch reordering, but the code in 4 looks ok, so
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # for 4/5
-Chris

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Re: [PATCH v3 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Daniel Vetter]

On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
> On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
> > Ensures that the batch buffer is executed by the resource streamer
> > 
> > v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
> > v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)
> > 
> > Testcase: igt/gem_exec_params
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> 
> This no longer applies (unrecognised base). Honestly, I would prefer 4&5
> squashed together, or 4 after 5 so that we do not declare
> HAS_RESOURCE_STREAMER before we accept the RS execbuf.
> 
> Minor bit of patch reordering, but the code in 4 looks ok, so
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # for 4/5

Yeah I just reordered 5 to go before 4. Series merged to dinq, thanks.
Abdiel can you pls push the corresponding igts (or ask Thomas to do it for
you)?
-Daniel
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Re: [PATCH v3 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Abdiel Janulgue]

On 07/06/2015 11:28 AM, Daniel Vetter wrote:
> On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
>> On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
>>> Ensures that the batch buffer is executed by the resource streamer
>>>
>>> v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
>>> v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)
>>>
>>> Testcase: igt/gem_exec_params
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>>
>> This no longer applies (unrecognised base). Honestly, I would prefer 4&5
>> squashed together, or 4 after 5 so that we do not declare
>> HAS_RESOURCE_STREAMER before we accept the RS execbuf.
>>
>> Minor bit of patch reordering, but the code in 4 looks ok, so
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # for 4/5
> 
> Yeah I just reordered 5 to go before 4. Series merged to dinq, thanks.
> Abdiel can you pls push the corresponding igts (or ask Thomas to do it for
> you)?

Thank you! I don't have commit rights in igt, but here is the patch:
http://lists.freedesktop.org/archives/intel-gfx/2015-June/068799.html

-Abdiel
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Re: [PATCH v3 5/5] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag

[Thomas Wood]

On 6 July 2015 at 09:46, Abdiel Janulgue
<abdiel.janulgue@linux.intel.com> wrote:
>
>
> On 07/06/2015 11:28 AM, Daniel Vetter wrote:
>> On Thu, Jul 02, 2015 at 11:15:40AM +0100, Chris Wilson wrote:
>>> On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
>>>> Ensures that the batch buffer is executed by the resource streamer
>>>>
>>>> v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
>>>> v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)
>>>>
>>>> Testcase: igt/gem_exec_params
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>>>
>>> This no longer applies (unrecognised base). Honestly, I would prefer 4&5
>>> squashed together, or 4 after 5 so that we do not declare
>>> HAS_RESOURCE_STREAMER before we accept the RS execbuf.
>>>
>>> Minor bit of patch reordering, but the code in 4 looks ok, so
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # for 4/5
>>
>> Yeah I just reordered 5 to go before 4. Series merged to dinq, thanks.
>> Abdiel can you pls push the corresponding igts (or ask Thomas to do it for
>> you)?
>
> Thank you! I don't have commit rights in igt, but here is the patch:
> http://lists.freedesktop.org/archives/intel-gfx/2015-June/068799.html

Pushed, thanks.

>
> -Abdiel
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Re: [PATCH resend 1/5] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START

[Chris Wilson]

On Tue, Jun 16, 2015 at 01:39:40PM +0300, Abdiel Janulgue wrote:
> Adds support for enabling the resource streamer on the legacy
> ringbuffer for HSW and GEN8.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

I've run a few examples with RS-enabled mesa and kernel, and nothing
fell over. I didn't see any significant changes on a hsw-gt2 either with
the current patches.

As far as the kernel goes for feature enablement, it looks ready.
-Chris

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