From: Clint Taylor <clinton.a.taylor@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/10] drm/i915: Split atomic wm update to pre and post variants
Date: Fri, 26 Jun 2015 13:22:57 -0700 [thread overview]
Message-ID: <558DB4A1.2040202@intel.com> (raw)
In-Reply-To: <1435172410-9834-3-git-send-email-ville.syrjala@linux.intel.com>
On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Try to update the watermarks on the right side of the plane update. This
> is just a temporary hack until we get the proper two part update into
> place. However in the meantime this might have some chance of at least
> working.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> 2 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 29c584c..1a1c686 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4713,6 +4713,9 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
>
> intel_frontbuffer_flip(dev, atomic->fb_bits);
>
> + if (crtc->atomic.update_wm_post)
> + intel_update_watermarks(&crtc->base);
> +
> if (atomic->update_fbc) {
> mutex_lock(&dev->struct_mutex);
> intel_fbc_update(dev);
> @@ -11641,8 +11644,12 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> plane->base.id, was_visible, visible,
> turn_off, turn_on, mode_changed);
>
> - if (intel_wm_need_update(plane, plane_state))
> - intel_crtc->atomic.update_wm = true;
> + if (turn_on)
> + intel_crtc->atomic.update_wm_pre = true;
> + else if (turn_off)
> + intel_crtc->atomic.update_wm_post = true;
> + else if (intel_wm_need_update(plane, plane_state))
> + intel_crtc->atomic.update_wm_pre = true;
>
> if (visible)
> intel_crtc->atomic.fb_bits |=
> @@ -11800,7 +11807,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> intel_crtc_check_initial_planes(crtc, crtc_state);
>
> if (mode_changed)
> - intel_crtc->atomic.update_wm = !crtc_state->active;
> + intel_crtc->atomic.update_wm_post = !crtc_state->active;
>
> if (mode_changed && crtc_state->enable &&
> dev_priv->display.crtc_compute_clock &&
> @@ -13729,7 +13736,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc)
> if (!needs_modeset(crtc->state))
> intel_pre_plane_update(intel_crtc);
>
> - if (intel_crtc->atomic.update_wm)
> + if (intel_crtc->atomic.update_wm_pre)
> intel_update_watermarks(crtc);
>
> intel_runtime_pm_get(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index de2cc26..fefaf01 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -499,7 +499,7 @@ struct intel_crtc_atomic_commit {
> bool wait_for_flips;
> bool disable_fbc;
> bool pre_disable_primary;
> - bool update_wm;
> + bool update_wm_pre, update_wm_post;
> unsigned disabled_planes;
>
> /* Sleepable operations to perform after commit */
>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>
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next prev parent reply other threads:[~2015-06-26 20:25 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-24 19:00 [PATCH 00/10] drm/i915: Another WM rewrite to enable DDR DVFS on CHV ville.syrjala
2015-06-24 19:00 ` [PATCH 01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr() ville.syrjala
2015-06-26 20:22 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 02/10] drm/i915: Split atomic wm update to pre and post variants ville.syrjala
2015-06-26 20:22 ` Clint Taylor [this message]
2015-06-24 19:00 ` [PATCH 03/10] drm/i915: Read wm values from hardware at init on CHV ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite ville.syrjala
2015-06-26 17:56 ` Clint Taylor
2015-06-26 19:48 ` Ville Syrjälä
2015-06-26 20:21 ` Clint Taylor
2015-06-29 8:03 ` Jani Nikula
2015-06-29 8:54 ` Daniel Vetter
2015-06-24 19:00 ` [PATCH 05/10] drm/i915: Compute display FIFO split dynamically for CHV ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 06/10] drm/i915: Use the memory latency based WM computation on VLV too ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-07-01 19:13 ` [PATCH v2 " ville.syrjala
2015-07-01 19:36 ` Paulo Zanoni
2015-07-01 20:38 ` Matt Roper
2015-06-24 19:00 ` [PATCH 08/10] drm/i915: Don't do PM5/DDR DVFS with multiple pipes ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 09/10] drm/i915: Add debugfs knobs for VLVCHV memory latency values ville.syrjala
2015-06-26 20:24 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV ville.syrjala
2015-06-26 20:24 ` Clint Taylor
2015-06-29 9:00 ` Daniel Vetter
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