* [PATCH 2/4] drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround
2015-07-03 16:53 [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Arun Siluvery
@ 2015-07-03 16:53 ` Arun Siluvery
2015-07-03 16:53 ` [PATCH 3/4] drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround Arun Siluvery
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2015-07-03 16:53 UTC (permalink / raw)
To: intel-gfx
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++------
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 927f395..152b4f6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1274,9 +1274,19 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
uint32_t *const batch,
uint32_t *offset)
{
- /* FIXME: Replace me with WA */
- DRM_ERROR("No WA available to init in indirect ctx batch buffer");
- return -EINVAL;
+ struct drm_device *dev = ring->dev;
+ uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+
+ /* WaDisableCtxRestoreArbitration:skl,bxt */
+ if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
+ (IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0)))
+ wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
+
+ /* Pad to end of cacheline */
+ while (index % CACHELINE_DWORDS)
+ wa_ctx_emit(batch, MI_NOOP);
+
+ return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}
static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
@@ -1284,9 +1294,17 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
uint32_t *const batch,
uint32_t *offset)
{
- /* FIXME: Replace me with WA */
- DRM_ERROR("No WA available to init in per ctx batch buffer");
- return -EINVAL;
+ struct drm_device *dev = ring->dev;
+ uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+
+ /* WaDisableCtxRestoreArbitration:skl,bxt */
+ if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
+ (IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0)))
+ wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+
+ wa_ctx_emit(batch, MI_BATCH_BUFFER_END);
+
+ return wa_ctx_end(wa_ctx, *offset = index, 1);
}
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround
2015-07-03 16:53 [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Arun Siluvery
2015-07-03 16:53 ` [PATCH 2/4] drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround Arun Siluvery
@ 2015-07-03 16:53 ` Arun Siluvery
2015-07-03 16:53 ` [PATCH 4/4] drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken Arun Siluvery
2015-07-03 16:57 ` [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Chris Wilson
3 siblings, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2015-07-03 16:53 UTC (permalink / raw)
To: intel-gfx
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
This patch depends on https://patchwork.kernel.org/patch/6715321/, which is
already reviewed by Chris, temporary dependency untill it gets merged.
drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 152b4f6..c4cac4d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1282,6 +1282,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
(IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0)))
wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
+ /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
+ index = gen8_emit_flush_coherentl3_wa(ring, batch, index);
+ if (index < 0)
+ return index;
+
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, MI_NOOP);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
2015-07-03 16:53 [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Arun Siluvery
2015-07-03 16:53 ` [PATCH 2/4] drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround Arun Siluvery
2015-07-03 16:53 ` [PATCH 3/4] drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround Arun Siluvery
@ 2015-07-03 16:53 ` Arun Siluvery
2015-07-03 16:57 ` [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Chris Wilson
3 siblings, 0 replies; 6+ messages in thread
From: Arun Siluvery @ 2015-07-03 16:53 UTC (permalink / raw)
To: intel-gfx
In Indirect context w/a batch buffer,
+WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c4cac4d..beb1cb3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1302,6 +1302,15 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+ /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
+ if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
+ (IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0))) {
+ wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1));
+ wa_ctx_emit(batch, GEN9_SLICE_COMMON_ECO_CHICKEN0);
+ wa_ctx_emit(batch, _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
+ wa_ctx_emit(batch, MI_NOOP);
+ }
+
/* WaDisableCtxRestoreArbitration:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == SKL_REVID_A0)))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index af7c12e..c567862 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -946,8 +946,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
- WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
- DISABLE_PIXEL_MASK_CAMMING);
+ /*
+ * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14] to be set,
+ * but that register is write only hence it is set
+ * in per ctx batch buffer
+ */
}
if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9
2015-07-03 16:53 [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Arun Siluvery
` (2 preceding siblings ...)
2015-07-03 16:53 ` [PATCH 4/4] drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken Arun Siluvery
@ 2015-07-03 16:57 ` Chris Wilson
2015-07-03 17:11 ` Siluvery, Arun
3 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2015-07-03 16:57 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx
On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote:
> This patch only enables support for Gen9, the actual WA will be
> initialized in subsequent patches.
>
> The WARN that we use to warn user if WA batch support is not available
> for a particular Gen is replaced with DRM_ERROR as warning here doesn't
> really add much value.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++++++---
> 1 file changed, 38 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 23ff018..927f395 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1269,6 +1269,26 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
> return wa_ctx_end(wa_ctx, *offset = index, 1);
> }
>
> +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
> + struct i915_wa_ctx_bb *wa_ctx,
> + uint32_t *const batch,
> + uint32_t *offset)
> +{
> + /* FIXME: Replace me with WA */
Do the same int index = wa_ctx_begin();
wa_ctx_emit(MI_BATCH_BUFFER_END) (and MI_NOOP for perctx)
return wa_ctx_end()
you did for gen8. That way the series doesn't suddenly break halfway
through (or just after the first patch) and we can check the
infrastructure in situ, and the actual wa separately later.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9
2015-07-03 16:57 ` [PATCH 1/4] drm/i915: Enable WA batch buffers for Gen9 Chris Wilson
@ 2015-07-03 17:11 ` Siluvery, Arun
0 siblings, 0 replies; 6+ messages in thread
From: Siluvery, Arun @ 2015-07-03 17:11 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 03/07/2015 17:57, Chris Wilson wrote:
> On Fri, Jul 03, 2015 at 05:53:38PM +0100, Arun Siluvery wrote:
>> This patch only enables support for Gen9, the actual WA will be
>> initialized in subsequent patches.
>>
>> The WARN that we use to warn user if WA batch support is not available
>> for a particular Gen is replaced with DRM_ERROR as warning here doesn't
>> really add much value.
>>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++++++---
>> 1 file changed, 38 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 23ff018..927f395 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1269,6 +1269,26 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
>> return wa_ctx_end(wa_ctx, *offset = index, 1);
>> }
>>
>> +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
>> + struct i915_wa_ctx_bb *wa_ctx,
>> + uint32_t *const batch,
>> + uint32_t *offset)
>> +{
>> + /* FIXME: Replace me with WA */
>
> Do the same int index = wa_ctx_begin();
>
> wa_ctx_emit(MI_BATCH_BUFFER_END) (and MI_NOOP for perctx)
>
> return wa_ctx_end()
>
> you did for gen8. That way the series doesn't suddenly break halfway
> through (or just after the first patch) and we can check the
> infrastructure in situ, and the actual wa separately later.
(forgot to reply-all)
right, will update it along with other review comments, thanks.
regards
Arun
> -Chris
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread