* [PATCH] drm/i915/bxt: BUNs related to port PLL @ 2015-07-01 4:36 Vandana Kannan 2015-07-01 4:21 ` Jindal, Sonika 2015-07-02 21:02 ` [PATCH] " shuang.he 0 siblings, 2 replies; 15+ messages in thread From: Vandana Kannan @ 2015-07-01 4:36 UTC (permalink / raw) To: intel-gfx This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 7 +++---- drivers/gpu/drm/i915/intel_display.c | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 42c1487..677096d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1495,8 +1495,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, } dco_amp = 15; - dcoampovr_en_h = 0; - if (vco >= 6200000 && vco <= 6480000) { + dcoampovr_en_h = 1; + if (vco >= 6200000 && vco <= 6700000) { prop_coef = 4; int_coef = 9; gain_ctl = 3; @@ -1550,8 +1550,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll8 = targ_cnt; - if (dcoampovr_en_h) - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index eb665d7..e04be45 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { static const intel_limit_t intel_limits_bxt = { /* FIXME: find real dot limits */ .dot = { .min = 0, .max = INT_MAX }, - .vco = { .min = 4800000, .max = 6480000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, /* FIXME: find real m2 limits */ -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915/bxt: BUNs related to port PLL 2015-07-01 4:36 [PATCH] drm/i915/bxt: BUNs related to port PLL Vandana Kannan @ 2015-07-01 4:21 ` Jindal, Sonika 2015-07-01 4:50 ` Kannan, Vandana 2015-07-02 21:02 ` [PATCH] " shuang.he 1 sibling, 1 reply; 15+ messages in thread From: Jindal, Sonika @ 2015-07-01 4:21 UTC (permalink / raw) To: Vandana Kannan, intel-gfx On 7/1/2015 10:06 AM, Vandana Kannan wrote: > This patch contains changes based on 2 updates to the spec: > Port PLL VCO restriction raised up to 6700. > Port PLL now needs DCO amp override enable for all VCO frequencies. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 7 +++---- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 2 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 42c1487..677096d 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1495,8 +1495,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > } > > dco_amp = 15; > - dcoampovr_en_h = 0; > - if (vco >= 6200000 && vco <= 6480000) { > + dcoampovr_en_h = 1; You dont need this variable now.. > + if (vco >= 6200000 && vco <= 6700000) { > prop_coef = 4; > int_coef = 9; > gain_ctl = 3; > @@ -1550,8 +1550,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > > crtc_state->dpll_hw_state.pll8 = targ_cnt; > > - if (dcoampovr_en_h) > - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; > + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; > > crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index eb665d7..e04be45 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { > static const intel_limit_t intel_limits_bxt = { > /* FIXME: find real dot limits */ > .dot = { .min = 0, .max = INT_MAX }, > - .vco = { .min = 4800000, .max = 6480000 }, > + .vco = { .min = 4800000, .max = 6700000 }, > .n = { .min = 1, .max = 1 }, > .m1 = { .min = 2, .max = 2 }, > /* FIXME: find real m2 limits */ > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915/bxt: BUNs related to port PLL 2015-07-01 4:21 ` Jindal, Sonika @ 2015-07-01 4:50 ` Kannan, Vandana 2015-07-01 5:34 ` [PATCH v2] " Vandana Kannan 0 siblings, 1 reply; 15+ messages in thread From: Kannan, Vandana @ 2015-07-01 4:50 UTC (permalink / raw) To: Jindal, Sonika, intel-gfx On 7/1/2015 9:51 AM, Jindal, Sonika wrote: > > > On 7/1/2015 10:06 AM, Vandana Kannan wrote: >> This patch contains changes based on 2 updates to the spec: >> Port PLL VCO restriction raised up to 6700. >> Port PLL now needs DCO amp override enable for all VCO frequencies. >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> --- >> drivers/gpu/drm/i915/intel_ddi.c | 7 +++---- >> drivers/gpu/drm/i915/intel_display.c | 2 +- >> 2 files changed, 4 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c >> b/drivers/gpu/drm/i915/intel_ddi.c >> index 42c1487..677096d 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -1495,8 +1495,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> } >> >> dco_amp = 15; >> - dcoampovr_en_h = 0; >> - if (vco >= 6200000 && vco <= 6480000) { >> + dcoampovr_en_h = 1; > You dont need this variable now.. > Agreed, will make the change. - Vandana >> + if (vco >= 6200000 && vco <= 6700000) { >> prop_coef = 4; >> int_coef = 9; >> gain_ctl = 3; >> @@ -1550,8 +1550,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> >> crtc_state->dpll_hw_state.pll8 = targ_cnt; >> >> - if (dcoampovr_en_h) >> - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; >> + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; >> >> crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c >> b/drivers/gpu/drm/i915/intel_display.c >> index eb665d7..e04be45 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { >> static const intel_limit_t intel_limits_bxt = { >> /* FIXME: find real dot limits */ >> .dot = { .min = 0, .max = INT_MAX }, >> - .vco = { .min = 4800000, .max = 6480000 }, >> + .vco = { .min = 4800000, .max = 6700000 }, >> .n = { .min = 1, .max = 1 }, >> .m1 = { .min = 2, .max = 2 }, >> /* FIXME: find real m2 limits */ >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2] drm/i915/bxt: BUNs related to port PLL 2015-07-01 4:50 ` Kannan, Vandana @ 2015-07-01 5:34 ` Vandana Kannan 2015-07-01 9:31 ` Jindal, Sonika ` (2 more replies) 0 siblings, 3 replies; 15+ messages in thread From: Vandana Kannan @ 2015-07-01 5:34 UTC (permalink / raw) To: intel-gfx This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++---------- drivers/gpu/drm/i915/intel_display.c | 2 +- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 42c1487..1eadc14 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1445,6 +1445,8 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = { {432000, 3, 1, 32, 1677722, 1, 1} }; +#define BXT_DCO_AMPLITUDE 15 + static bool bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, @@ -1455,7 +1457,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct bxt_clk_div clk_div = {0}; int vco = 0; uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; - uint32_t dcoampovr_en_h, dco_amp, lanestagger; + uint32_t lanestagger; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1494,9 +1496,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; } - dco_amp = 15; - dcoampovr_en_h = 0; - if (vco >= 6200000 && vco <= 6480000) { + if (vco >= 6200000 && vco <= 6700000) { prop_coef = 4; int_coef = 9; gain_ctl = 3; @@ -1507,8 +1507,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, int_coef = 11; gain_ctl = 3; targ_cnt = 9; - if (vco >= 4800000 && vco < 5400000) - dcoampovr_en_h = 1; } else if (vco == 5400000) { prop_coef = 3; int_coef = 8; @@ -1550,10 +1548,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll8 = targ_cnt; - if (dcoampovr_en_h) - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; - - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP(BXT_DCO_AMPLITUDE) + | PORT_PLL_DCO_AMP_OVR_EN_H; crtc_state->dpll_hw_state.pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index eb665d7..e04be45 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { static const intel_limit_t intel_limits_bxt = { /* FIXME: find real dot limits */ .dot = { .min = 0, .max = INT_MAX }, - .vco = { .min = 4800000, .max = 6480000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, /* FIXME: find real m2 limits */ -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2] drm/i915/bxt: BUNs related to port PLL 2015-07-01 5:34 ` [PATCH v2] " Vandana Kannan @ 2015-07-01 9:31 ` Jindal, Sonika 2015-07-01 10:18 ` Sivakumar Thulasimani 2015-07-02 23:39 ` [PATCH v2] " shuang.he 2 siblings, 0 replies; 15+ messages in thread From: Jindal, Sonika @ 2015-07-01 9:31 UTC (permalink / raw) To: Kannan, Vandana, intel-gfx@lists.freedesktop.org Looks good to me.. Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> -----Original Message----- From: Kannan, Vandana Sent: Wednesday, July 1, 2015 11:04 AM To: intel-gfx@lists.freedesktop.org Cc: Thulasimani, Sivakumar; Jindal, Sonika; Deak, Imre; Kannan, Vandana Subject: [PATCH v2] drm/i915/bxt: BUNs related to port PLL This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++---------- drivers/gpu/drm/i915/intel_display.c | 2 +- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 42c1487..1eadc14 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1445,6 +1445,8 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = { {432000, 3, 1, 32, 1677722, 1, 1} }; +#define BXT_DCO_AMPLITUDE 15 + static bool bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, @@ -1455,7 +1457,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct bxt_clk_div clk_div = {0}; int vco = 0; uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; - uint32_t dcoampovr_en_h, dco_amp, lanestagger; + uint32_t lanestagger; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1494,9 +1496,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; } - dco_amp = 15; - dcoampovr_en_h = 0; - if (vco >= 6200000 && vco <= 6480000) { + if (vco >= 6200000 && vco <= 6700000) { prop_coef = 4; int_coef = 9; gain_ctl = 3; @@ -1507,8 +1507,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, int_coef = 11; gain_ctl = 3; targ_cnt = 9; - if (vco >= 4800000 && vco < 5400000) - dcoampovr_en_h = 1; } else if (vco == 5400000) { prop_coef = 3; int_coef = 8; @@ -1550,10 +1548,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll8 = targ_cnt; - if (dcoampovr_en_h) - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; - - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP(BXT_DCO_AMPLITUDE) + | PORT_PLL_DCO_AMP_OVR_EN_H; crtc_state->dpll_hw_state.pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index eb665d7..e04be45 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { static const intel_limit_t intel_limits_bxt = { /* FIXME: find real dot limits */ .dot = { .min = 0, .max = INT_MAX }, - .vco = { .min = 4800000, .max = 6480000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, /* FIXME: find real m2 limits */ -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2] drm/i915/bxt: BUNs related to port PLL 2015-07-01 5:34 ` [PATCH v2] " Vandana Kannan 2015-07-01 9:31 ` Jindal, Sonika @ 2015-07-01 10:18 ` Sivakumar Thulasimani 2015-07-01 10:42 ` Kannan, Vandana 2015-07-02 23:39 ` [PATCH v2] " shuang.he 2 siblings, 1 reply; 15+ messages in thread From: Sivakumar Thulasimani @ 2015-07-01 10:18 UTC (permalink / raw) To: Vandana Kannan, intel-gfx On 7/1/2015 11:04 AM, Vandana Kannan wrote: > This patch contains changes based on 2 updates to the spec: > Port PLL VCO restriction raised up to 6700. > Port PLL now needs DCO amp override enable for all VCO frequencies. > > v2: Sonika's review comment addressed > - dcoampovr_en_h variable not required > Based on a discussion with Siva, the following changes have been made. > - replace dco_amp var with #define BXT_DCO_AMPLITUDE > - set pll10 in a single assignment > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++---------- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 2 files changed, 7 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 42c1487..1eadc14 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1445,6 +1445,8 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = { > {432000, 3, 1, 32, 1677722, 1, 1} > }; > > +#define BXT_DCO_AMPLITUDE 15 > + can this be moved to i915_reg.h along with other #defines relating to PORT_PLL_10_A? > static bool > bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_crtc_state *crtc_state, > @@ -1455,7 +1457,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > struct bxt_clk_div clk_div = {0}; > int vco = 0; > uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; > - uint32_t dcoampovr_en_h, dco_amp, lanestagger; > + uint32_t lanestagger; > > if (intel_encoder->type == INTEL_OUTPUT_HDMI) { > intel_clock_t best_clock; > @@ -1494,9 +1496,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; > } > > - dco_amp = 15; > - dcoampovr_en_h = 0; > - if (vco >= 6200000 && vco <= 6480000) { > + if (vco >= 6200000 && vco <= 6700000) { > prop_coef = 4; > int_coef = 9; > gain_ctl = 3; > @@ -1507,8 +1507,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > int_coef = 11; > gain_ctl = 3; > targ_cnt = 9; > - if (vco >= 4800000 && vco < 5400000) > - dcoampovr_en_h = 1; > } else if (vco == 5400000) { > prop_coef = 3; > int_coef = 8; > @@ -1550,10 +1548,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > > crtc_state->dpll_hw_state.pll8 = targ_cnt; > > - if (dcoampovr_en_h) > - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; > - > - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); > + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP(BXT_DCO_AMPLITUDE) > + | PORT_PLL_DCO_AMP_OVR_EN_H; > > crtc_state->dpll_hw_state.pcsdw12 = > LANESTAGGER_STRAP_OVRD | lanestagger; > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index eb665d7..e04be45 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { > static const intel_limit_t intel_limits_bxt = { > /* FIXME: find real dot limits */ > .dot = { .min = 0, .max = INT_MAX }, > - .vco = { .min = 4800000, .max = 6480000 }, > + .vco = { .min = 4800000, .max = 6700000 }, > .n = { .min = 1, .max = 1 }, > .m1 = { .min = 2, .max = 2 }, > /* FIXME: find real m2 limits */ -- regards, Sivakumar _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2] drm/i915/bxt: BUNs related to port PLL 2015-07-01 10:18 ` Sivakumar Thulasimani @ 2015-07-01 10:42 ` Kannan, Vandana 2015-07-01 11:32 ` [PATCH v3] " Vandana Kannan 0 siblings, 1 reply; 15+ messages in thread From: Kannan, Vandana @ 2015-07-01 10:42 UTC (permalink / raw) To: Sivakumar Thulasimani, intel-gfx On 7/1/2015 3:48 PM, Sivakumar Thulasimani wrote: > > > On 7/1/2015 11:04 AM, Vandana Kannan wrote: >> This patch contains changes based on 2 updates to the spec: >> Port PLL VCO restriction raised up to 6700. >> Port PLL now needs DCO amp override enable for all VCO frequencies. >> >> v2: Sonika's review comment addressed >> - dcoampovr_en_h variable not required >> Based on a discussion with Siva, the following changes have been made. >> - replace dco_amp var with #define BXT_DCO_AMPLITUDE >> - set pll10 in a single assignment >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> --- >> drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++---------- >> drivers/gpu/drm/i915/intel_display.c | 2 +- >> 2 files changed, 7 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c >> b/drivers/gpu/drm/i915/intel_ddi.c >> index 42c1487..1eadc14 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -1445,6 +1445,8 @@ static const struct bxt_clk_div bxt_dp_clk_val[] >> = { >> {432000, 3, 1, 32, 1677722, 1, 1} >> }; >> +#define BXT_DCO_AMPLITUDE 15 >> + > can this be moved to i915_reg.h along with other #defines relating to > PORT_PLL_10_A? Hi Siva, Since the requirement of BXT_DCO_AMPLITUDE is local to this function/file, I added it here instead of i915_reg.h. Following the other #defines in this file, like REF_MIN, REF_MAX. - Vandana >> static bool >> bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> struct intel_crtc_state *crtc_state, >> @@ -1455,7 +1457,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> struct bxt_clk_div clk_div = {0}; >> int vco = 0; >> uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; >> - uint32_t dcoampovr_en_h, dco_amp, lanestagger; >> + uint32_t lanestagger; >> if (intel_encoder->type == INTEL_OUTPUT_HDMI) { >> intel_clock_t best_clock; >> @@ -1494,9 +1496,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; >> } >> - dco_amp = 15; >> - dcoampovr_en_h = 0; >> - if (vco >= 6200000 && vco <= 6480000) { >> + if (vco >= 6200000 && vco <= 6700000) { >> prop_coef = 4; >> int_coef = 9; >> gain_ctl = 3; >> @@ -1507,8 +1507,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> int_coef = 11; >> gain_ctl = 3; >> targ_cnt = 9; >> - if (vco >= 4800000 && vco < 5400000) >> - dcoampovr_en_h = 1; >> } else if (vco == 5400000) { >> prop_coef = 3; >> int_coef = 8; >> @@ -1550,10 +1548,8 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> crtc_state->dpll_hw_state.pll8 = targ_cnt; >> - if (dcoampovr_en_h) >> - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; >> - >> - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); >> + crtc_state->dpll_hw_state.pll10 = >> PORT_PLL_DCO_AMP(BXT_DCO_AMPLITUDE) >> + | PORT_PLL_DCO_AMP_OVR_EN_H; >> crtc_state->dpll_hw_state.pcsdw12 = >> LANESTAGGER_STRAP_OVRD | lanestagger; >> diff --git a/drivers/gpu/drm/i915/intel_display.c >> b/drivers/gpu/drm/i915/intel_display.c >> index eb665d7..e04be45 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { >> static const intel_limit_t intel_limits_bxt = { >> /* FIXME: find real dot limits */ >> .dot = { .min = 0, .max = INT_MAX }, >> - .vco = { .min = 4800000, .max = 6480000 }, >> + .vco = { .min = 4800000, .max = 6700000 }, >> .n = { .min = 1, .max = 1 }, >> .m1 = { .min = 2, .max = 2 }, >> /* FIXME: find real m2 limits */ > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-01 10:42 ` Kannan, Vandana @ 2015-07-01 11:32 ` Vandana Kannan 2015-07-01 11:11 ` Sivakumar Thulasimani 2015-07-04 11:01 ` shuang.he 0 siblings, 2 replies; 15+ messages in thread From: Vandana Kannan @ 2015-07-01 11:32 UTC (permalink / raw) To: intel-gfx This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment v3: Move DCO amplitude default value to i915_reg.h. Suggested by Siva. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2] --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 15 +++++---------- drivers/gpu/drm/i915/intel_display.c | 2 +- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ac985c5..d1b8928 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1211,6 +1211,7 @@ enum skl_disp_power_wells { #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe /* PORT_PLL_10_A */ #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) +#define PORT_PLL_DCO_AMP_DEFAULT 15 #define PORT_PLL_DCO_AMP_MASK 0x3c00 #define PORT_PLL_DCO_AMP(x) (x<<10) #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 42c1487..9c05cc0 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1455,7 +1455,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct bxt_clk_div clk_div = {0}; int vco = 0; uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; - uint32_t dcoampovr_en_h, dco_amp, lanestagger; + uint32_t lanestagger; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1494,9 +1494,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; } - dco_amp = 15; - dcoampovr_en_h = 0; - if (vco >= 6200000 && vco <= 6480000) { + if (vco >= 6200000 && vco <= 6700000) { prop_coef = 4; int_coef = 9; gain_ctl = 3; @@ -1507,8 +1505,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, int_coef = 11; gain_ctl = 3; targ_cnt = 9; - if (vco >= 4800000 && vco < 5400000) - dcoampovr_en_h = 1; } else if (vco == 5400000) { prop_coef = 3; int_coef = 8; @@ -1550,10 +1546,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll8 = targ_cnt; - if (dcoampovr_en_h) - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; - - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); + crtc_state->dpll_hw_state.pll10 = + PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) + | PORT_PLL_DCO_AMP_OVR_EN_H; crtc_state->dpll_hw_state.pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index eb665d7..e04be45 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { static const intel_limit_t intel_limits_bxt = { /* FIXME: find real dot limits */ .dot = { .min = 0, .max = INT_MAX }, - .vco = { .min = 4800000, .max = 6480000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, /* FIXME: find real m2 limits */ -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-01 11:32 ` [PATCH v3] " Vandana Kannan @ 2015-07-01 11:11 ` Sivakumar Thulasimani 2015-07-03 4:53 ` Kannan, Vandana 2015-07-04 11:01 ` shuang.he 1 sibling, 1 reply; 15+ messages in thread From: Sivakumar Thulasimani @ 2015-07-01 11:11 UTC (permalink / raw) To: Vandana Kannan; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3843 bytes --] thanks for the changes. Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> On 7/1/2015 5:02 PM, Vandana Kannan wrote: > This patch contains changes based on 2 updates to the spec: > Port PLL VCO restriction raised up to 6700. > Port PLL now needs DCO amp override enable for all VCO frequencies. > > v2: Sonika's review comment addressed > - dcoampovr_en_h variable not required > Based on a discussion with Siva, the following changes have been made. > - replace dco_amp var with #define BXT_DCO_AMPLITUDE > - set pll10 in a single assignment > > v3: > Move DCO amplitude default value to i915_reg.h. Suggested by Siva. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2] > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 15 +++++---------- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 3 files changed, 7 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ac985c5..d1b8928 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1211,6 +1211,7 @@ enum skl_disp_power_wells { > #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe > /* PORT_PLL_10_A */ > #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) > +#define PORT_PLL_DCO_AMP_DEFAULT 15 > #define PORT_PLL_DCO_AMP_MASK 0x3c00 > #define PORT_PLL_DCO_AMP(x) (x<<10) > #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 42c1487..9c05cc0 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1455,7 +1455,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > struct bxt_clk_div clk_div = {0}; > int vco = 0; > uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; > - uint32_t dcoampovr_en_h, dco_amp, lanestagger; > + uint32_t lanestagger; > > if (intel_encoder->type == INTEL_OUTPUT_HDMI) { > intel_clock_t best_clock; > @@ -1494,9 +1494,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; > } > > - dco_amp = 15; > - dcoampovr_en_h = 0; > - if (vco >= 6200000 && vco <= 6480000) { > + if (vco >= 6200000 && vco <= 6700000) { > prop_coef = 4; > int_coef = 9; > gain_ctl = 3; > @@ -1507,8 +1505,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > int_coef = 11; > gain_ctl = 3; > targ_cnt = 9; > - if (vco >= 4800000 && vco < 5400000) > - dcoampovr_en_h = 1; > } else if (vco == 5400000) { > prop_coef = 3; > int_coef = 8; > @@ -1550,10 +1546,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > > crtc_state->dpll_hw_state.pll8 = targ_cnt; > > - if (dcoampovr_en_h) > - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; > - > - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); > + crtc_state->dpll_hw_state.pll10 = > + PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) > + | PORT_PLL_DCO_AMP_OVR_EN_H; > > crtc_state->dpll_hw_state.pcsdw12 = > LANESTAGGER_STRAP_OVRD | lanestagger; > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index eb665d7..e04be45 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { > static const intel_limit_t intel_limits_bxt = { > /* FIXME: find real dot limits */ > .dot = { .min = 0, .max = INT_MAX }, > - .vco = { .min = 4800000, .max = 6480000 }, > + .vco = { .min = 4800000, .max = 6700000 }, > .n = { .min = 1, .max = 1 }, > .m1 = { .min = 2, .max = 2 }, > /* FIXME: find real m2 limits */ -- regards, Sivakumar [-- Attachment #1.2: Type: text/html, Size: 4629 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-01 11:11 ` Sivakumar Thulasimani @ 2015-07-03 4:53 ` Kannan, Vandana 2015-07-06 8:08 ` Kannan, Vandana 0 siblings, 1 reply; 15+ messages in thread From: Kannan, Vandana @ 2015-07-03 4:53 UTC (permalink / raw) To: Sivakumar Thulasimani, intel-gfx Hi, Any other review comments on this patch? Do let me know. Siva and Sonika have given their R-b. Thanks, Vandana On 7/1/2015 4:41 PM, Sivakumar Thulasimani wrote: > thanks for the changes. > > Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> > > > > On 7/1/2015 5:02 PM, Vandana Kannan wrote: >> This patch contains changes based on 2 updates to the spec: >> Port PLL VCO restriction raised up to 6700. >> Port PLL now needs DCO amp override enable for all VCO frequencies. >> >> v2: Sonika's review comment addressed >> - dcoampovr_en_h variable not required >> Based on a discussion with Siva, the following changes have been made. >> - replace dco_amp var with #define BXT_DCO_AMPLITUDE >> - set pll10 in a single assignment >> >> v3: >> Move DCO amplitude default value to i915_reg.h. Suggested by Siva. >> >> Signed-off-by: Vandana Kannan<vandana.kannan@intel.com> >> Reviewed-by: Sonika Jindal<sonika.jindal@intel.com> [v2] >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_ddi.c | 15 +++++---------- >> drivers/gpu/drm/i915/intel_display.c | 2 +- >> 3 files changed, 7 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index ac985c5..d1b8928 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1211,6 +1211,7 @@ enum skl_disp_power_wells { >> #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe >> /* PORT_PLL_10_A */ >> #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) >> +#define PORT_PLL_DCO_AMP_DEFAULT 15 >> #define PORT_PLL_DCO_AMP_MASK 0x3c00 >> #define PORT_PLL_DCO_AMP(x) (x<<10) >> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 42c1487..9c05cc0 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -1455,7 +1455,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> struct bxt_clk_div clk_div = {0}; >> int vco = 0; >> uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; >> - uint32_t dcoampovr_en_h, dco_amp, lanestagger; >> + uint32_t lanestagger; >> >> if (intel_encoder->type == INTEL_OUTPUT_HDMI) { >> intel_clock_t best_clock; >> @@ -1494,9 +1494,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; >> } >> >> - dco_amp = 15; >> - dcoampovr_en_h = 0; >> - if (vco >= 6200000 && vco <= 6480000) { >> + if (vco >= 6200000 && vco <= 6700000) { >> prop_coef = 4; >> int_coef = 9; >> gain_ctl = 3; >> @@ -1507,8 +1505,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> int_coef = 11; >> gain_ctl = 3; >> targ_cnt = 9; >> - if (vco >= 4800000 && vco < 5400000) >> - dcoampovr_en_h = 1; >> } else if (vco == 5400000) { >> prop_coef = 3; >> int_coef = 8; >> @@ -1550,10 +1546,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> >> crtc_state->dpll_hw_state.pll8 = targ_cnt; >> >> - if (dcoampovr_en_h) >> - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; >> - >> - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); >> + crtc_state->dpll_hw_state.pll10 = >> + PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) >> + | PORT_PLL_DCO_AMP_OVR_EN_H; >> >> crtc_state->dpll_hw_state.pcsdw12 = >> LANESTAGGER_STRAP_OVRD | lanestagger; >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index eb665d7..e04be45 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { >> static const intel_limit_t intel_limits_bxt = { >> /* FIXME: find real dot limits */ >> .dot = { .min = 0, .max = INT_MAX }, >> - .vco = { .min = 4800000, .max = 6480000 }, >> + .vco = { .min = 4800000, .max = 6700000 }, >> .n = { .min = 1, .max = 1 }, >> .m1 = { .min = 2, .max = 2 }, >> /* FIXME: find real m2 limits */ > > -- > regards, > Sivakumar > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-03 4:53 ` Kannan, Vandana @ 2015-07-06 8:08 ` Kannan, Vandana 2015-07-06 8:21 ` Daniel Vetter 0 siblings, 1 reply; 15+ messages in thread From: Kannan, Vandana @ 2015-07-06 8:08 UTC (permalink / raw) To: Sivakumar Thulasimani, intel-gfx, Vetter, Daniel Hi Daniel, Is there any other change required in this patch to consider before merge? Please let me know. - Vandana On 7/3/2015 10:23 AM, Kannan, Vandana wrote: > Hi, > > Any other review comments on this patch? Do let me know. > Siva and Sonika have given their R-b. > > Thanks, > Vandana > > On 7/1/2015 4:41 PM, Sivakumar Thulasimani wrote: >> thanks for the changes. >> >> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> >> >> >> >> On 7/1/2015 5:02 PM, Vandana Kannan wrote: >>> This patch contains changes based on 2 updates to the spec: >>> Port PLL VCO restriction raised up to 6700. >>> Port PLL now needs DCO amp override enable for all VCO frequencies. >>> >>> v2: Sonika's review comment addressed >>> - dcoampovr_en_h variable not required >>> Based on a discussion with Siva, the following changes have been made. >>> - replace dco_amp var with #define BXT_DCO_AMPLITUDE >>> - set pll10 in a single assignment >>> >>> v3: >>> Move DCO amplitude default value to i915_reg.h. Suggested by Siva. >>> >>> Signed-off-by: Vandana Kannan<vandana.kannan@intel.com> >>> Reviewed-by: Sonika Jindal<sonika.jindal@intel.com> [v2] >>> --- >>> drivers/gpu/drm/i915/i915_reg.h | 1 + >>> drivers/gpu/drm/i915/intel_ddi.c | 15 +++++---------- >>> drivers/gpu/drm/i915/intel_display.c | 2 +- >>> 3 files changed, 7 insertions(+), 11 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h >>> b/drivers/gpu/drm/i915/i915_reg.h >>> index ac985c5..d1b8928 100644 >>> --- a/drivers/gpu/drm/i915/i915_reg.h >>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>> @@ -1211,6 +1211,7 @@ enum skl_disp_power_wells { >>> #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe >>> /* PORT_PLL_10_A */ >>> #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) >>> +#define PORT_PLL_DCO_AMP_DEFAULT 15 >>> #define PORT_PLL_DCO_AMP_MASK 0x3c00 >>> #define PORT_PLL_DCO_AMP(x) (x<<10) >>> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ >>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c >>> b/drivers/gpu/drm/i915/intel_ddi.c >>> index 42c1487..9c05cc0 100644 >>> --- a/drivers/gpu/drm/i915/intel_ddi.c >>> +++ b/drivers/gpu/drm/i915/intel_ddi.c >>> @@ -1455,7 +1455,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >>> struct bxt_clk_div clk_div = {0}; >>> int vco = 0; >>> uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; >>> - uint32_t dcoampovr_en_h, dco_amp, lanestagger; >>> + uint32_t lanestagger; >>> >>> if (intel_encoder->type == INTEL_OUTPUT_HDMI) { >>> intel_clock_t best_clock; >>> @@ -1494,9 +1494,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >>> vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; >>> } >>> >>> - dco_amp = 15; >>> - dcoampovr_en_h = 0; >>> - if (vco >= 6200000 && vco <= 6480000) { >>> + if (vco >= 6200000 && vco <= 6700000) { >>> prop_coef = 4; >>> int_coef = 9; >>> gain_ctl = 3; >>> @@ -1507,8 +1505,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >>> int_coef = 11; >>> gain_ctl = 3; >>> targ_cnt = 9; >>> - if (vco >= 4800000 && vco < 5400000) >>> - dcoampovr_en_h = 1; >>> } else if (vco == 5400000) { >>> prop_coef = 3; >>> int_coef = 8; >>> @@ -1550,10 +1546,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >>> >>> crtc_state->dpll_hw_state.pll8 = targ_cnt; >>> >>> - if (dcoampovr_en_h) >>> - crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; >>> - >>> - crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); >>> + crtc_state->dpll_hw_state.pll10 = >>> + PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) >>> + | PORT_PLL_DCO_AMP_OVR_EN_H; >>> >>> crtc_state->dpll_hw_state.pcsdw12 = >>> LANESTAGGER_STRAP_OVRD | lanestagger; >>> diff --git a/drivers/gpu/drm/i915/intel_display.c >>> b/drivers/gpu/drm/i915/intel_display.c >>> index eb665d7..e04be45 100644 >>> --- a/drivers/gpu/drm/i915/intel_display.c >>> +++ b/drivers/gpu/drm/i915/intel_display.c >>> @@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { >>> static const intel_limit_t intel_limits_bxt = { >>> /* FIXME: find real dot limits */ >>> .dot = { .min = 0, .max = INT_MAX }, >>> - .vco = { .min = 4800000, .max = 6480000 }, >>> + .vco = { .min = 4800000, .max = 6700000 }, >>> .n = { .min = 1, .max = 1 }, >>> .m1 = { .min = 2, .max = 2 }, >>> /* FIXME: find real m2 limits */ >> >> -- >> regards, >> Sivakumar >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-06 8:08 ` Kannan, Vandana @ 2015-07-06 8:21 ` Daniel Vetter 0 siblings, 0 replies; 15+ messages in thread From: Daniel Vetter @ 2015-07-06 8:21 UTC (permalink / raw) To: Kannan, Vandana; +Cc: Vetter, Daniel, intel-gfx On Mon, Jul 06, 2015 at 01:38:44PM +0530, Kannan, Vandana wrote: > Hi Daniel, > > Is there any other change required in this patch to consider before merge? > Please let me know. Oh I was kinda waiting for an ack from Imre. Merged now anyway. Btw for next time around please spell out BUN - not everyone knows what this means, especially outside of intel gfx teams (product teams, integration, customers, ...). And we write changelogs also for those external people. Maybe "Implement latest Bspec updates for ..." or similar. I've changed the summary for this patch. -Daniel > > - Vandana > > On 7/3/2015 10:23 AM, Kannan, Vandana wrote: > >Hi, > > > >Any other review comments on this patch? Do let me know. > >Siva and Sonika have given their R-b. > > > >Thanks, > >Vandana > > > >On 7/1/2015 4:41 PM, Sivakumar Thulasimani wrote: > >>thanks for the changes. > >> > >>Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> > >> > >> > >> > >>On 7/1/2015 5:02 PM, Vandana Kannan wrote: > >>>This patch contains changes based on 2 updates to the spec: > >>>Port PLL VCO restriction raised up to 6700. > >>>Port PLL now needs DCO amp override enable for all VCO frequencies. > >>> > >>>v2: Sonika's review comment addressed > >>> - dcoampovr_en_h variable not required > >>>Based on a discussion with Siva, the following changes have been made. > >>> - replace dco_amp var with #define BXT_DCO_AMPLITUDE > >>> - set pll10 in a single assignment > >>> > >>>v3: > >>>Move DCO amplitude default value to i915_reg.h. Suggested by Siva. > >>> > >>>Signed-off-by: Vandana Kannan<vandana.kannan@intel.com> > >>>Reviewed-by: Sonika Jindal<sonika.jindal@intel.com> [v2] > >>>--- > >>> drivers/gpu/drm/i915/i915_reg.h | 1 + > >>> drivers/gpu/drm/i915/intel_ddi.c | 15 +++++---------- > >>> drivers/gpu/drm/i915/intel_display.c | 2 +- > >>> 3 files changed, 7 insertions(+), 11 deletions(-) > >>> > >>>diff --git a/drivers/gpu/drm/i915/i915_reg.h > >>>b/drivers/gpu/drm/i915/i915_reg.h > >>>index ac985c5..d1b8928 100644 > >>>--- a/drivers/gpu/drm/i915/i915_reg.h > >>>+++ b/drivers/gpu/drm/i915/i915_reg.h > >>>@@ -1211,6 +1211,7 @@ enum skl_disp_power_wells { > >>> #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe > >>> /* PORT_PLL_10_A */ > >>> #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) > >>>+#define PORT_PLL_DCO_AMP_DEFAULT 15 > >>> #define PORT_PLL_DCO_AMP_MASK 0x3c00 > >>> #define PORT_PLL_DCO_AMP(x) (x<<10) > >>> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ > >>>diff --git a/drivers/gpu/drm/i915/intel_ddi.c > >>>b/drivers/gpu/drm/i915/intel_ddi.c > >>>index 42c1487..9c05cc0 100644 > >>>--- a/drivers/gpu/drm/i915/intel_ddi.c > >>>+++ b/drivers/gpu/drm/i915/intel_ddi.c > >>>@@ -1455,7 +1455,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > >>> struct bxt_clk_div clk_div = {0}; > >>> int vco = 0; > >>> uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; > >>>- uint32_t dcoampovr_en_h, dco_amp, lanestagger; > >>>+ uint32_t lanestagger; > >>> > >>> if (intel_encoder->type == INTEL_OUTPUT_HDMI) { > >>> intel_clock_t best_clock; > >>>@@ -1494,9 +1494,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > >>> vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; > >>> } > >>> > >>>- dco_amp = 15; > >>>- dcoampovr_en_h = 0; > >>>- if (vco >= 6200000 && vco <= 6480000) { > >>>+ if (vco >= 6200000 && vco <= 6700000) { > >>> prop_coef = 4; > >>> int_coef = 9; > >>> gain_ctl = 3; > >>>@@ -1507,8 +1505,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > >>> int_coef = 11; > >>> gain_ctl = 3; > >>> targ_cnt = 9; > >>>- if (vco >= 4800000 && vco < 5400000) > >>>- dcoampovr_en_h = 1; > >>> } else if (vco == 5400000) { > >>> prop_coef = 3; > >>> int_coef = 8; > >>>@@ -1550,10 +1546,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > >>> > >>> crtc_state->dpll_hw_state.pll8 = targ_cnt; > >>> > >>>- if (dcoampovr_en_h) > >>>- crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; > >>>- > >>>- crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); > >>>+ crtc_state->dpll_hw_state.pll10 = > >>>+ PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) > >>>+ | PORT_PLL_DCO_AMP_OVR_EN_H; > >>> > >>> crtc_state->dpll_hw_state.pcsdw12 = > >>> LANESTAGGER_STRAP_OVRD | lanestagger; > >>>diff --git a/drivers/gpu/drm/i915/intel_display.c > >>>b/drivers/gpu/drm/i915/intel_display.c > >>>index eb665d7..e04be45 100644 > >>>--- a/drivers/gpu/drm/i915/intel_display.c > >>>+++ b/drivers/gpu/drm/i915/intel_display.c > >>>@@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { > >>> static const intel_limit_t intel_limits_bxt = { > >>> /* FIXME: find real dot limits */ > >>> .dot = { .min = 0, .max = INT_MAX }, > >>>- .vco = { .min = 4800000, .max = 6480000 }, > >>>+ .vco = { .min = 4800000, .max = 6700000 }, > >>> .n = { .min = 1, .max = 1 }, > >>> .m1 = { .min = 2, .max = 2 }, > >>> /* FIXME: find real m2 limits */ > >> > >>-- > >>regards, > >>Sivakumar > >> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] drm/i915/bxt: BUNs related to port PLL 2015-07-01 11:32 ` [PATCH v3] " Vandana Kannan 2015-07-01 11:11 ` Sivakumar Thulasimani @ 2015-07-04 11:01 ` shuang.he 1 sibling, 0 replies; 15+ messages in thread From: shuang.he @ 2015-07-04 11:01 UTC (permalink / raw) To: shuang.he, lei.a.liu, intel-gfx, vandana.kannan Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6699 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied ILK 304/304 304/304 SNB 312/316 312/316 IVB 343/343 343/343 BYT -2 287/287 285/287 HSW 380/380 380/380 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *BYT igt@gem_partial_pwrite_pread@reads PASS(1) FAIL(1) *BYT igt@gem_tiled_partial_pwrite_pread@reads PASS(1) FAIL(1) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2] drm/i915/bxt: BUNs related to port PLL 2015-07-01 5:34 ` [PATCH v2] " Vandana Kannan 2015-07-01 9:31 ` Jindal, Sonika 2015-07-01 10:18 ` Sivakumar Thulasimani @ 2015-07-02 23:39 ` shuang.he 2 siblings, 0 replies; 15+ messages in thread From: shuang.he @ 2015-07-02 23:39 UTC (permalink / raw) To: shuang.he, lei.a.liu, intel-gfx, vandana.kannan Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6693 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied ILK 302/302 302/302 SNB 312/316 312/316 IVB 343/343 343/343 BYT -1 287/287 286/287 HSW 380/380 380/380 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *BYT igt@gem_partial_pwrite_pread@reads-uncached PASS(1) FAIL(1) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] drm/i915/bxt: BUNs related to port PLL 2015-07-01 4:36 [PATCH] drm/i915/bxt: BUNs related to port PLL Vandana Kannan 2015-07-01 4:21 ` Jindal, Sonika @ 2015-07-02 21:02 ` shuang.he 1 sibling, 0 replies; 15+ messages in thread From: shuang.he @ 2015-07-02 21:02 UTC (permalink / raw) To: shuang.he, lei.a.liu, intel-gfx, vandana.kannan Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6692 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied ILK 302/302 302/302 SNB 312/316 312/316 IVB 343/343 343/343 BYT -2 287/287 285/287 HSW 380/380 380/380 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *BYT igt@gem_partial_pwrite_pread@reads PASS(1) FAIL(1) *BYT igt@gem_tiled_partial_pwrite_pread@reads PASS(1) FAIL(1) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-07-06 8:18 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-07-01 4:36 [PATCH] drm/i915/bxt: BUNs related to port PLL Vandana Kannan 2015-07-01 4:21 ` Jindal, Sonika 2015-07-01 4:50 ` Kannan, Vandana 2015-07-01 5:34 ` [PATCH v2] " Vandana Kannan 2015-07-01 9:31 ` Jindal, Sonika 2015-07-01 10:18 ` Sivakumar Thulasimani 2015-07-01 10:42 ` Kannan, Vandana 2015-07-01 11:32 ` [PATCH v3] " Vandana Kannan 2015-07-01 11:11 ` Sivakumar Thulasimani 2015-07-03 4:53 ` Kannan, Vandana 2015-07-06 8:08 ` Kannan, Vandana 2015-07-06 8:21 ` Daniel Vetter 2015-07-04 11:01 ` shuang.he 2015-07-02 23:39 ` [PATCH v2] " shuang.he 2015-07-02 21:02 ` [PATCH] " shuang.he
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