From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions Date: Tue, 07 Jul 2015 13:37:57 +0530 Message-ID: <559B88DD.5030304@intel.com> References: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com> <1436184606-18729-4-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1232873230==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 330F96E981 for ; Tue, 7 Jul 2015 01:09:20 -0700 (PDT) In-Reply-To: <1436184606-18729-4-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============1232873230== Content-Type: multipart/alternative; boundary="------------080306090208050300010508" This is a multi-part message in MIME format. --------------080306090208050300010508 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > All the *_ddi_pll_select() functions get passed the port_clock and pipe > config as parameters. We only need to pass the pipe config, and the > functions can dig up the port_clock themselves. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/in= tel_ddi.c > index 0d3cc98..96fb472 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1262,9 +1262,10 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, > static bool > hsw_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_crtc_state *crtc_state, > - struct intel_encoder *intel_encoder, > - int clock) > + struct intel_encoder *intel_encoder) > { > + int clock =3D crtc_state->port_clock; > + > if (intel_encoder->type =3D=3D INTEL_OUTPUT_HDMI) { > struct intel_shared_dpll *pll; > uint32_t val; > @@ -1543,11 +1544,11 @@ skip_remaining_dividers: > static bool > skl_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_crtc_state *crtc_state, > - struct intel_encoder *intel_encoder, > - int clock) > + struct intel_encoder *intel_encoder) > { > struct intel_shared_dpll *pll; > uint32_t ctrl1, cfgcr1, cfgcr2; > + int clock =3D crtc_state->port_clock; > =20 > /* > * See comment in intel_dpll_hw_state to understand why we always us= e 0 > @@ -1635,14 +1636,14 @@ static const struct bxt_clk_div bxt_dp_clk_val[= ] =3D { > static bool > bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_crtc_state *crtc_state, > - struct intel_encoder *intel_encoder, > - int clock) > + struct intel_encoder *intel_encoder) > { > struct intel_shared_dpll *pll; > struct bxt_clk_div clk_div =3D {0}; > int vco =3D 0; > uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; > uint32_t lanestagger; > + int clock =3D crtc_state->port_clock; > =20 > if (intel_encoder->type =3D=3D INTEL_OUTPUT_HDMI) { > intel_clock_t best_clock; > @@ -1770,17 +1771,16 @@ bool intel_ddi_pll_select(struct intel_crtc *in= tel_crtc, > struct drm_device *dev =3D intel_crtc->base.dev; > struct intel_encoder *intel_encoder =3D > intel_ddi_get_crtc_new_encoder(crtc_state); > - int clock =3D crtc_state->port_clock; > =20 > if (IS_SKYLAKE(dev)) > return skl_ddi_pll_select(intel_crtc, crtc_state, > - intel_encoder, clock); > + intel_encoder); > else if (IS_BROXTON(dev)) > return bxt_ddi_pll_select(intel_crtc, crtc_state, > - intel_encoder, clock); > + intel_encoder); > else > return hsw_ddi_pll_select(intel_crtc, crtc_state, > - intel_encoder, clock); > + intel_encoder); > } > =20 > void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) --=20 regards, Sivakumar --------------080306090208050300010508 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

All the *_ddi_pll_select() functions get passed the port_clock and pipe
config as parameters. We only need to pass the pipe config, and the
functions can dig up the port_clock themselves.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/inte=
l_ddi.c
index 0d3cc98..96fb472 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1262,9 +1262,10 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 static bool
 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
+	int clock =3D crtc_state->port_clock;
+
 	if (intel_encoder->type =3D=3D INTEL_OUTPUT_HDMI) {
 		struct intel_shared_dpll *pll;
 		uint32_t val;
@@ -1543,11 +1544,11 @@ skip_remaining_dividers:
 static bool
 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
 	struct intel_shared_dpll *pll;
 	uint32_t ctrl1, cfgcr1, cfgcr2;
+	int clock =3D crtc_state->port_clock;
=20
 	/*
 	 * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1635,14 +1636,14 @@ static const struct bxt_clk_div bxt_dp_clk_val[] =
=3D {
 static bool
 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
 	struct intel_shared_dpll *pll;
 	struct bxt_clk_div clk_div =3D {0};
 	int vco =3D 0;
 	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
 	uint32_t lanestagger;
+	int clock =3D crtc_state->port_clock;
=20
 	if (intel_encoder->type =3D=3D INTEL_OUTPUT_HDMI) {
 		intel_clock_t best_clock;
@@ -1770,17 +1771,16 @@ bool intel_ddi_pll_select(struct intel_crtc *inte=
l_crtc,
 	struct drm_device *dev =3D intel_crtc->base.dev;
 	struct intel_encoder *intel_encoder =3D
 		intel_ddi_get_crtc_new_encoder(crtc_state);
-	int clock =3D crtc_state->port_clock;
=20
 	if (IS_SKYLAKE(dev))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 	else if (IS_BROXTON(dev))
 		return bxt_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 	else
 		return hsw_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 }
=20
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)


--=20
regards,
Sivakumar
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