From: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config()
Date: Tue, 07 Jul 2015 13:44:48 +0530 [thread overview]
Message-ID: <559B8A78.6090002@intel.com> (raw)
In-Reply-To: <1436184606-18729-5-git-send-email-ville.syrjala@linux.intel.com>
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Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use a separate variable for the TRANS_DP_CTL value instead of reusing
> 'tmp' that otherwise contains the DP port register value.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3dd4342..b6ba02e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2245,13 +2245,14 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
>
> if (HAS_PCH_CPT(dev) && port != PORT_A) {
> - tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> - if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> + u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> +
> + if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> flags |= DRM_MODE_FLAG_PHSYNC;
> else
> flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> + if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> flags |= DRM_MODE_FLAG_PVSYNC;
> else
> flags |= DRM_MODE_FLAG_NVSYNC;
--
regards,
Sivakumar
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next prev parent reply other threads:[~2015-07-07 8:16 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-06 12:09 [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp ville.syrjala
2015-07-06 12:10 ` [PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling ville.syrjala
2015-08-13 6:16 ` Sivakumar Thulasimani
2015-08-13 12:01 ` Ville Syrjälä
2015-07-06 12:10 ` [PATCH 2/7] drm/i915: Don't use link_bw for PLL setup ville.syrjala
2015-07-07 8:05 ` Sivakumar Thulasimani
2015-08-11 17:21 ` [PATCH v2 " ville.syrjala
2015-07-06 12:10 ` [PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions ville.syrjala
2015-07-07 8:07 ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config() ville.syrjala
2015-07-07 8:14 ` Sivakumar Thulasimani [this message]
2015-07-06 12:10 ` [PATCH 5/7] drm/i915: Move intel_dp->lane_count into pipe_config ville.syrjala
2015-07-06 13:39 ` [PATCH v2 " ville.syrjala
2015-08-13 7:00 ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3 ville.syrjala
2015-07-07 8:18 ` Sivakumar Thulasimani
2015-07-06 12:10 ` [PATCH 7/7] drm/i915: Kill intel_dp->{link_bw, rate_select} ville.syrjala
2015-07-07 8:46 ` Sivakumar Thulasimani
2015-07-10 23:13 ` shuang.he
2015-08-12 16:04 ` [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp Ville Syrjälä
2015-08-14 8:23 ` Daniel Vetter
2015-08-17 8:42 ` Maarten Lankhorst
2015-08-17 12:03 ` Ville Syrjälä
2015-08-25 12:57 ` Daniel Vetter
2015-08-25 14:11 ` Ville Syrjälä
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