From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3 Date: Tue, 07 Jul 2015 13:48:00 +0530 Message-ID: <559B8B38.9030501@intel.com> References: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com> <1436184606-18729-7-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1487328639==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 867906E987 for ; Tue, 7 Jul 2015 01:19:22 -0700 (PDT) In-Reply-To: <1436184606-18729-7-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============1487328639== Content-Type: multipart/alternative; boundary="------------050804040604090101090405" This is a multi-part message in MIME format. --------------050804040604090101090405 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > intel_dp->link_bw is going away, so consul the port_clock instead when > choosing between TP1 and TP3. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > index da036e8..46b734b 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3697,8 +3697,8 @@ intel_dp_complete_link_train(struct intel_dp *int= el_dp) > uint32_t DP =3D intel_dp->DP; > uint32_t training_pattern =3D DP_TRAINING_PATTERN_2; > =20 > - /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ > - if (intel_dp->link_bw =3D=3D DP_LINK_BW_5_4 || intel_dp->use_tps3) > + /* Training Pattern 3 for HBR2 or 1.2 devices that support it*/ > + if (crtc->config->port_clock =3D=3D 540000 || intel_dp->use_tps3) > training_pattern =3D DP_TRAINING_PATTERN_3; > =20 > /* channel equalization */ --=20 regards, Sivakumar --------------050804040604090101090405 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

intel_dp->link_bw is going away, so consul the port_clock instead when
choosing between TP1 and TP3.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel=
_dp.c
index da036e8..46b734b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3697,8 +3697,8 @@ intel_dp_complete_link_train(struct intel_dp *intel=
_dp)
 	uint32_t DP =3D intel_dp->DP;
 	uint32_t training_pattern =3D DP_TRAINING_PATTERN_2;
=20
-	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
-	if (intel_dp->link_bw =3D=3D DP_LINK_BW_5_4 || intel_dp->use_tps3=
)
+	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
+	if (crtc->config->port_clock =3D=3D 540000 || intel_dp->use_tp=
s3)
 		training_pattern =3D DP_TRAINING_PATTERN_3;
=20
 	/* channel equalization */


--=20
regards,
Sivakumar
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