From: "Goel, Akash" <akash.goel@intel.com>
To: Michel Thierry <michel.thierry@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 12/17] drm/i915/gen8: Add ppgtt info and debug_dump
Date: Tue, 7 Jul 2015 18:26:09 +0530 [thread overview]
Message-ID: <559BCC69.10101@intel.com> (raw)
In-Reply-To: <1435764453-11954-13-git-send-email-michel.thierry@intel.com>
On 7/1/2015 8:57 PM, Michel Thierry wrote:
> v2: Clean up patch after rebases.
> v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
> v4: Use used_pml4es/pdpes (Akash).
> v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v2+)
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++----
> drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 102 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ad9a737..8c3dcc9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2223,7 +2223,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> - struct drm_file *file;
> int i;
>
> if (INTEL_INFO(dev)->gen == 6)
> @@ -2246,13 +2245,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
> ppgtt->debug_dump(ppgtt, m);
> }
>
> - list_for_each_entry_reverse(file, &dev->filelist, lhead) {
> - struct drm_i915_file_private *file_priv = file->driver_priv;
> -
> - seq_printf(m, "proc: %s\n",
> - get_pid_task(file->pid, PIDTYPE_PID)->comm);
> - idr_for_each(&file_priv->context_idr, per_file_ctx, m);
> - }
> seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
> }
>
> @@ -2261,6 +2253,7 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
> struct drm_info_node *node = m->private;
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_file *file;
>
> int ret = mutex_lock_interruptible(&dev->struct_mutex);
> if (ret)
> @@ -2272,6 +2265,15 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
> else if (INTEL_INFO(dev)->gen >= 6)
> gen6_ppgtt_info(m, dev);
>
> + list_for_each_entry_reverse(file, &dev->filelist, lhead) {
> + struct drm_i915_file_private *file_priv = file->driver_priv;
> +
> + seq_printf(m, "\nproc: %s\n",
> + get_pid_task(file->pid, PIDTYPE_PID)->comm);
> + idr_for_each(&file_priv->context_idr, per_file_ctx,
> + (void *)(unsigned long)m);
> + }
> +
> intel_runtime_pm_put(dev_priv);
> mutex_unlock(&dev->struct_mutex);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c6fc0d3..0c41e5d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1337,6 +1337,97 @@ static int gen8_alloc_va_range(struct i915_address_space *vm,
> return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
> }
>
> +static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
> + uint64_t start, uint64_t length,
> + gen8_pte_t scratch_pte,
> + struct seq_file *m)
> +{
> + struct i915_page_directory *pd;
> + uint64_t temp;
> + uint32_t pdpe;
> +
> + gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
> + struct i915_page_table *pt;
> + uint64_t pd_len = length;
> + uint64_t pd_start = start;
> + uint32_t pde;
> +
> + if (!pd)
> + continue;
> +
> + if(!test_bit(pdpe, pdp->used_pdpes))
> + continue;
> +
> + seq_printf(m, "\tPDPE #%d\n", pdpe);
> + gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
> + uint32_t pte;
> + gen8_pte_t *pt_vaddr;
> +
> + if (!pt)
> + continue;
> +
> + pt_vaddr = kmap_px(pt);
> + for (pte = 0; pte < GEN8_PTES; pte+=4) {
> + uint64_t va =
> + (pdpe << GEN8_PDPE_SHIFT) |
> + (pde << GEN8_PDE_SHIFT) |
> + (pte << GEN8_PTE_SHIFT);
> + int i;
> + bool found = false;
> + for (i = 0; i < 4; i++)
> + if (pt_vaddr[pte + i] != scratch_pte)
> + found = true;
> + if (!found)
> + continue;
> +
> + seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
> + for (i = 0; i < 4; i++) {
> + if (pt_vaddr[pte + i] != scratch_pte)
> + seq_printf(m, " %llx", pt_vaddr[pte + i]);
> + else
> + seq_puts(m, " SCRATCH ");
> + }
> + seq_puts(m, "\n");
> + }
> + /* don't use kunmap_px, it could trigger
> + * an unnecessary flush.
> + */
> + kunmap_atomic(pt_vaddr);
> + }
> + }
> +}
> +
> +static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
> +{
> + struct i915_address_space *vm = &ppgtt->base;
> + uint64_t start = ppgtt->base.start;
> + uint64_t length = ppgtt->base.total;
> + gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
> + I915_CACHE_LLC, true);
> +
> + if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
> + gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
> + } else {
> + uint64_t templ4, pml4e;
> + struct i915_pml4 *pml4 = &ppgtt->pml4;
> + struct i915_page_directory_pointer *pdp;
> +
> + gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
> + uint64_t pdp_len = length;
> + uint64_t pdp_start = start;
> +
> + if (!pdp)
> + continue;
> +
I think the "if (!test_bit(pml4e, pml4->used_pml4es))" check is
foolproof & should suffice.
No real need of the extra check of 'if (!pdp)'.
Same for pdpe & pde loops in gen8_dump_pdp function
> + if (!test_bit(pml4e, pml4->used_pml4es))
> + continue;
> +
> + seq_printf(m, " PML4E #%llu\n", pml4e);
> + gen8_dump_pdp(pdp, pdp_start, pdp_len, scratch_pte, m);
> + }
> + }
> +}
> +
> /*
> * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
> * with a net effect resembling a 2-level page table in normal x86 terms. Each
> @@ -1359,6 +1450,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> ppgtt->base.clear_range = gen8_ppgtt_clear_range;
> ppgtt->base.unbind_vma = ppgtt_unbind_vma;
> ppgtt->base.bind_vma = ppgtt_bind_vma;
> + ppgtt->debug_dump = gen8_dump_ppgtt;
>
> if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
> ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
>
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next prev parent reply other threads:[~2015-07-07 12:56 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 16:46 [PATCH v2 00/18] 48-bit PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 01/18] drm/i915/lrc: Update PDPx registers with lri commands Michel Thierry
2015-06-11 18:04 ` Mika Kuoppala
2015-06-22 9:18 ` Michel Thierry
2015-06-26 12:46 ` [PATCH v3] " Michel Thierry
2015-06-26 14:45 ` Mika Kuoppala
2015-06-10 16:46 ` [PATCH v2 02/18] drm/i915/gtt: Switch gen8_free_page_tables params Michel Thierry
2015-06-11 18:05 ` Mika Kuoppala
2015-06-26 16:38 ` Daniel Vetter
2015-06-10 16:46 ` [PATCH v2 03/18] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-06-10 16:46 ` [PATCH v2 04/18] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-06-10 16:46 ` [PATCH v2 05/18] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-06-10 16:46 ` [PATCH v2 06/18] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-06-10 16:46 ` [PATCH v2 07/18] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-06-10 16:46 ` [PATCH v2 08/18] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-06-10 16:46 ` [PATCH v2 09/18] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 10/18] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-06-10 16:46 ` [PATCH v2 11/18] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-06-10 16:46 ` [PATCH v2 12/18] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-06-10 16:46 ` [PATCH v2 13/18] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-06-10 16:46 ` [PATCH v2 14/18] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-06-10 16:46 ` [PATCH v2 15/18] drm/i915: object size needs to be u64 Michel Thierry
2015-06-10 16:46 ` [PATCH v2 16/18] drm/i915: Check against correct user_size limit in 48b ppgtt mode Michel Thierry
2015-06-10 17:57 ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 17/18] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-06-10 18:09 ` Chris Wilson
2015-06-17 12:49 ` Daniel Vetter
2015-06-17 12:53 ` Chris Wilson
2015-06-17 15:03 ` Daniel Vetter
2015-06-17 17:37 ` Chris Wilson
2015-06-18 6:45 ` Daniel Vetter
2015-06-18 7:03 ` Chris Wilson
2015-06-18 7:11 ` Daniel Vetter
2015-06-18 7:34 ` Chris Wilson
2015-06-23 12:21 ` [PATCH v3] " Michel Thierry
2015-06-23 13:22 ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 18/18] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-06-10 16:46 ` [PATCH v2] tests/gem_ppgtt: Check Wa32bitOffsets workarounds Michel Thierry
2015-07-01 15:27 ` [PATCH v3 00/17] 48-bit PPGTT Michel Thierry
2015-07-01 15:27 ` [PATCH v3 01/17] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-01 15:27 ` [PATCH v3 02/17] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-07 12:36 ` Goel, Akash
2015-07-07 12:56 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 03/17] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-07 12:43 ` Goel, Akash
2015-07-07 13:35 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 04/17] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-01 15:27 ` [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-07 12:48 ` Goel, Akash
2015-07-07 13:40 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 06/17] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-01 15:27 ` [PATCH v3 07/17] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-01 15:27 ` [PATCH v3 08/17] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-01 15:27 ` [PATCH v3 09/17] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-07 12:51 ` Goel, Akash
2015-07-07 13:42 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 10/17] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-07-01 15:27 ` [PATCH v3 11/17] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-07 12:53 ` Goel, Akash
2015-07-07 13:50 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 12/17] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-07 12:56 ` Goel, Akash [this message]
2015-07-07 13:51 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 13/17] drm/i915: object size needs to be u64 Michel Thierry
2015-07-01 15:27 ` [PATCH v3 14/17] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-01 16:07 ` John Harrison
2015-07-01 15:27 ` [PATCH v3 15/17] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-01 15:31 ` Chris Wilson
2015-07-01 15:27 ` [PATCH v3 16/17] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-01 15:43 ` Chris Wilson
2015-07-01 15:54 ` Michel Thierry
2015-07-01 16:02 ` [PATCH v5] " Michel Thierry
2015-07-01 15:27 ` [PATCH v3 17/17] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-01 15:38 ` [PATCH v3 00/17] 48-bit PPGTT Daniel Vetter
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