From: Michel Thierry <michel.thierry@intel.com>
To: "Goel, Akash" <akash.goel@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 09/17] drm/i915/gen8: Add 4 level support in insert_entries and clear_range
Date: Tue, 7 Jul 2015 14:42:07 +0100 [thread overview]
Message-ID: <559BD72F.8000806@intel.com> (raw)
In-Reply-To: <559BCB67.1020806@intel.com>
On 7/7/2015 1:51 PM, Goel, Akash wrote:
> On 7/1/2015 8:57 PM, Michel Thierry wrote:
>> static void
>> @@ -781,9 +793,9 @@ gen8_ppgtt_insert_pte_entries(struct
>> i915_address_space *vm,
>> struct i915_hw_ppgtt *ppgtt =
>> container_of(vm, struct i915_hw_ppgtt, base);
>> gen8_pte_t *pt_vaddr;
>> - unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
>> - unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
>> - unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
>> + unsigned pdpe = gen8_pdpe_index(start);
>> + unsigned pde = gen8_pde_index(start);
>> + unsigned pte = gen8_pte_index(start);
>>
>> pt_vaddr = NULL;
>>
>> @@ -801,7 +813,8 @@ gen8_ppgtt_insert_pte_entries(struct
>> i915_address_space *vm,
>> kunmap_px(ppgtt, pt_vaddr);
>> pt_vaddr = NULL;
>> if (++pde == I915_PDES) {
>> - pdpe++;
>> + if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
>> + break;
>
> Can the same pdpe check (for Page directory pointer boundary) be added
> in the gen8_ppgtt_clear_pte_range function also, to make it consistent
> with gen8_ppgtt_insert_pte_entries and this will also obviate the need
> for gen8_clamp_pdp macro.
>
I will change gen8_ppgtt_clear_pte_range to stop at PDP boundary as you
suggests (and clamp_pdp will go away).
>> pde = 0;
>> }
>> pte = 0;
>> @@ -820,11 +833,25 @@ static void gen8_ppgtt_insert_entries(struct
>> i915_address_space *vm,
>> {
>> struct i915_hw_ppgtt *ppgtt =
>> container_of(vm, struct i915_hw_ppgtt, base);
>> - struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME:
>> 48b */
>> struct sg_page_iter sg_iter;
>>
>> __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl),
>> 0);
>> - gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, start,
>> cache_level);
>> +
>> + if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
>> + gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
>> + cache_level);
>> + } else {
>> + struct i915_page_directory_pointer *pdp;
>> + uint64_t templ4, pml4e;
>> + uint64_t length = (uint64_t)sg_nents(pages->sgl) << PAGE_SHIFT;
>> +
>> + gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4,
>> pml4e) {
>> + uint64_t pdp_start = start;
>> +
>
> Isn't the 'pdp_start' dispensable here ? ‘start’ can be used directly.
>
Yes, and the same applies in gen8_ppgtt_clear_range, pdp_len and
pdp_start are redundant there.
>> + gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
>> + pdp_start, cache_level);
>> + }
>> + }
>> }
>>
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next prev parent reply other threads:[~2015-07-07 13:42 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 16:46 [PATCH v2 00/18] 48-bit PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 01/18] drm/i915/lrc: Update PDPx registers with lri commands Michel Thierry
2015-06-11 18:04 ` Mika Kuoppala
2015-06-22 9:18 ` Michel Thierry
2015-06-26 12:46 ` [PATCH v3] " Michel Thierry
2015-06-26 14:45 ` Mika Kuoppala
2015-06-10 16:46 ` [PATCH v2 02/18] drm/i915/gtt: Switch gen8_free_page_tables params Michel Thierry
2015-06-11 18:05 ` Mika Kuoppala
2015-06-26 16:38 ` Daniel Vetter
2015-06-10 16:46 ` [PATCH v2 03/18] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-06-10 16:46 ` [PATCH v2 04/18] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-06-10 16:46 ` [PATCH v2 05/18] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-06-10 16:46 ` [PATCH v2 06/18] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-06-10 16:46 ` [PATCH v2 07/18] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-06-10 16:46 ` [PATCH v2 08/18] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-06-10 16:46 ` [PATCH v2 09/18] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-06-10 16:46 ` [PATCH v2 10/18] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-06-10 16:46 ` [PATCH v2 11/18] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-06-10 16:46 ` [PATCH v2 12/18] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-06-10 16:46 ` [PATCH v2 13/18] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-06-10 16:46 ` [PATCH v2 14/18] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-06-10 16:46 ` [PATCH v2 15/18] drm/i915: object size needs to be u64 Michel Thierry
2015-06-10 16:46 ` [PATCH v2 16/18] drm/i915: Check against correct user_size limit in 48b ppgtt mode Michel Thierry
2015-06-10 17:57 ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 17/18] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-06-10 18:09 ` Chris Wilson
2015-06-17 12:49 ` Daniel Vetter
2015-06-17 12:53 ` Chris Wilson
2015-06-17 15:03 ` Daniel Vetter
2015-06-17 17:37 ` Chris Wilson
2015-06-18 6:45 ` Daniel Vetter
2015-06-18 7:03 ` Chris Wilson
2015-06-18 7:11 ` Daniel Vetter
2015-06-18 7:34 ` Chris Wilson
2015-06-23 12:21 ` [PATCH v3] " Michel Thierry
2015-06-23 13:22 ` Chris Wilson
2015-06-10 16:46 ` [PATCH v2 18/18] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-06-10 16:46 ` [PATCH v2] tests/gem_ppgtt: Check Wa32bitOffsets workarounds Michel Thierry
2015-07-01 15:27 ` [PATCH v3 00/17] 48-bit PPGTT Michel Thierry
2015-07-01 15:27 ` [PATCH v3 01/17] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-01 15:27 ` [PATCH v3 02/17] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-07 12:36 ` Goel, Akash
2015-07-07 12:56 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 03/17] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-07 12:43 ` Goel, Akash
2015-07-07 13:35 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 04/17] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-01 15:27 ` [PATCH v3 05/17] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-07 12:48 ` Goel, Akash
2015-07-07 13:40 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 06/17] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-01 15:27 ` [PATCH v3 07/17] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-01 15:27 ` [PATCH v3 08/17] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-01 15:27 ` [PATCH v3 09/17] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-07 12:51 ` Goel, Akash
2015-07-07 13:42 ` Michel Thierry [this message]
2015-07-01 15:27 ` [PATCH v3 10/17] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-07-01 15:27 ` [PATCH v3 11/17] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-07 12:53 ` Goel, Akash
2015-07-07 13:50 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 12/17] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-07 12:56 ` Goel, Akash
2015-07-07 13:51 ` Michel Thierry
2015-07-01 15:27 ` [PATCH v3 13/17] drm/i915: object size needs to be u64 Michel Thierry
2015-07-01 15:27 ` [PATCH v3 14/17] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-01 16:07 ` John Harrison
2015-07-01 15:27 ` [PATCH v3 15/17] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-01 15:31 ` Chris Wilson
2015-07-01 15:27 ` [PATCH v3 16/17] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-01 15:43 ` Chris Wilson
2015-07-01 15:54 ` Michel Thierry
2015-07-01 16:02 ` [PATCH v5] " Michel Thierry
2015-07-01 15:27 ` [PATCH v3 17/17] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-01 15:38 ` [PATCH v3 00/17] 48-bit PPGTT Daniel Vetter
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